1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/delay.h>
7 #include <drm/drm_print.h>
8
9 #include "dp_reg.h"
10 #include "dp_aux.h"
11
12 #define DP_AUX_ENUM_STR(x) #x
13
14 struct dp_aux_private {
15 struct device *dev;
16 struct dp_catalog *catalog;
17
18 struct mutex mutex;
19 struct completion comp;
20
21 u32 aux_error_num;
22 u32 retry_cnt;
23 bool cmd_busy;
24 bool native;
25 bool read;
26 bool no_send_addr;
27 bool no_send_stop;
28 u32 offset;
29 u32 segment;
30 u32 isr;
31
32 struct drm_dp_aux dp_aux;
33 };
34
dp_aux_get_error(u32 aux_error)35 static const char *dp_aux_get_error(u32 aux_error)
36 {
37 switch (aux_error) {
38 case DP_AUX_ERR_NONE:
39 return DP_AUX_ENUM_STR(DP_AUX_ERR_NONE);
40 case DP_AUX_ERR_ADDR:
41 return DP_AUX_ENUM_STR(DP_AUX_ERR_ADDR);
42 case DP_AUX_ERR_TOUT:
43 return DP_AUX_ENUM_STR(DP_AUX_ERR_TOUT);
44 case DP_AUX_ERR_NACK:
45 return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK);
46 case DP_AUX_ERR_DEFER:
47 return DP_AUX_ENUM_STR(DP_AUX_ERR_DEFER);
48 case DP_AUX_ERR_NACK_DEFER:
49 return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK_DEFER);
50 default:
51 return "unknown";
52 }
53 }
54
dp_aux_write(struct dp_aux_private * aux,struct drm_dp_aux_msg * msg)55 static u32 dp_aux_write(struct dp_aux_private *aux,
56 struct drm_dp_aux_msg *msg)
57 {
58 u32 data[4], reg, len;
59 u8 *msgdata = msg->buffer;
60 int const AUX_CMD_FIFO_LEN = 128;
61 int i = 0;
62
63 if (aux->read)
64 len = 4;
65 else
66 len = msg->size + 4;
67
68 /*
69 * cmd fifo only has depth of 144 bytes
70 * limit buf length to 128 bytes here
71 */
72 if (len > AUX_CMD_FIFO_LEN) {
73 DRM_ERROR("buf size greater than allowed size of 128 bytes\n");
74 return 0;
75 }
76
77 /* Pack cmd and write to HW */
78 data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */
79 if (aux->read)
80 data[0] |= BIT(4); /* R/W */
81
82 data[1] = (msg->address >> 8) & 0xff; /* addr[15:8] */
83 data[2] = msg->address & 0xff; /* addr[7:0] */
84 data[3] = (msg->size - 1) & 0xff; /* len[7:0] */
85
86 for (i = 0; i < len; i++) {
87 reg = (i < 4) ? data[i] : msgdata[i - 4];
88 /* index = 0, write */
89 reg = (((reg) << DP_AUX_DATA_OFFSET)
90 & DP_AUX_DATA_MASK) | DP_AUX_DATA_WRITE;
91 if (i == 0)
92 reg |= DP_AUX_DATA_INDEX_WRITE;
93 aux->catalog->aux_data = reg;
94 dp_catalog_aux_write_data(aux->catalog);
95 }
96
97 dp_catalog_aux_clear_trans(aux->catalog, false);
98 dp_catalog_aux_clear_hw_interrupts(aux->catalog);
99
100 reg = 0; /* Transaction number == 1 */
101 if (!aux->native) { /* i2c */
102 reg |= DP_AUX_TRANS_CTRL_I2C;
103
104 if (aux->no_send_addr)
105 reg |= DP_AUX_TRANS_CTRL_NO_SEND_ADDR;
106
107 if (aux->no_send_stop)
108 reg |= DP_AUX_TRANS_CTRL_NO_SEND_STOP;
109 }
110
111 reg |= DP_AUX_TRANS_CTRL_GO;
112 aux->catalog->aux_data = reg;
113 dp_catalog_aux_write_trans(aux->catalog);
114
115 return len;
116 }
117
dp_aux_cmd_fifo_tx(struct dp_aux_private * aux,struct drm_dp_aux_msg * msg)118 static int dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
119 struct drm_dp_aux_msg *msg)
120 {
121 u32 ret, len, timeout;
122 int aux_timeout_ms = HZ/4;
123
124 reinit_completion(&aux->comp);
125
126 len = dp_aux_write(aux, msg);
127 if (len == 0) {
128 DRM_ERROR("DP AUX write failed\n");
129 return -EINVAL;
130 }
131
132 timeout = wait_for_completion_timeout(&aux->comp, aux_timeout_ms);
133 if (!timeout) {
134 DRM_ERROR("aux %s timeout\n", (aux->read ? "read" : "write"));
135 return -ETIMEDOUT;
136 }
137
138 if (aux->aux_error_num == DP_AUX_ERR_NONE) {
139 ret = len;
140 } else {
141 DRM_ERROR_RATELIMITED("aux err: %s\n",
142 dp_aux_get_error(aux->aux_error_num));
143
144 ret = -EINVAL;
145 }
146
147 return ret;
148 }
149
dp_aux_cmd_fifo_rx(struct dp_aux_private * aux,struct drm_dp_aux_msg * msg)150 static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
151 struct drm_dp_aux_msg *msg)
152 {
153 u32 data;
154 u8 *dp;
155 u32 i, actual_i;
156 u32 len = msg->size;
157
158 dp_catalog_aux_clear_trans(aux->catalog, true);
159
160 data = DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */
161 data |= DP_AUX_DATA_READ; /* read */
162
163 aux->catalog->aux_data = data;
164 dp_catalog_aux_write_data(aux->catalog);
165
166 dp = msg->buffer;
167
168 /* discard first byte */
169 data = dp_catalog_aux_read_data(aux->catalog);
170
171 for (i = 0; i < len; i++) {
172 data = dp_catalog_aux_read_data(aux->catalog);
173 *dp++ = (u8)((data >> DP_AUX_DATA_OFFSET) & 0xff);
174
175 actual_i = (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF;
176 if (i != actual_i)
177 DRM_ERROR("Index mismatch: expected %d, found %d\n",
178 i, actual_i);
179 }
180 }
181
dp_aux_native_handler(struct dp_aux_private * aux)182 static void dp_aux_native_handler(struct dp_aux_private *aux)
183 {
184 u32 isr = aux->isr;
185
186 if (isr & DP_INTR_AUX_I2C_DONE)
187 aux->aux_error_num = DP_AUX_ERR_NONE;
188 else if (isr & DP_INTR_WRONG_ADDR)
189 aux->aux_error_num = DP_AUX_ERR_ADDR;
190 else if (isr & DP_INTR_TIMEOUT)
191 aux->aux_error_num = DP_AUX_ERR_TOUT;
192 if (isr & DP_INTR_NACK_DEFER)
193 aux->aux_error_num = DP_AUX_ERR_NACK;
194 if (isr & DP_INTR_AUX_ERROR) {
195 aux->aux_error_num = DP_AUX_ERR_PHY;
196 dp_catalog_aux_clear_hw_interrupts(aux->catalog);
197 }
198
199 complete(&aux->comp);
200 }
201
dp_aux_i2c_handler(struct dp_aux_private * aux)202 static void dp_aux_i2c_handler(struct dp_aux_private *aux)
203 {
204 u32 isr = aux->isr;
205
206 if (isr & DP_INTR_AUX_I2C_DONE) {
207 if (isr & (DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER))
208 aux->aux_error_num = DP_AUX_ERR_NACK;
209 else
210 aux->aux_error_num = DP_AUX_ERR_NONE;
211 } else {
212 if (isr & DP_INTR_WRONG_ADDR)
213 aux->aux_error_num = DP_AUX_ERR_ADDR;
214 else if (isr & DP_INTR_TIMEOUT)
215 aux->aux_error_num = DP_AUX_ERR_TOUT;
216 if (isr & DP_INTR_NACK_DEFER)
217 aux->aux_error_num = DP_AUX_ERR_NACK_DEFER;
218 if (isr & DP_INTR_I2C_NACK)
219 aux->aux_error_num = DP_AUX_ERR_NACK;
220 if (isr & DP_INTR_I2C_DEFER)
221 aux->aux_error_num = DP_AUX_ERR_DEFER;
222 if (isr & DP_INTR_AUX_ERROR) {
223 aux->aux_error_num = DP_AUX_ERR_PHY;
224 dp_catalog_aux_clear_hw_interrupts(aux->catalog);
225 }
226 }
227
228 complete(&aux->comp);
229 }
230
dp_aux_update_offset_and_segment(struct dp_aux_private * aux,struct drm_dp_aux_msg * input_msg)231 static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux,
232 struct drm_dp_aux_msg *input_msg)
233 {
234 u32 edid_address = 0x50;
235 u32 segment_address = 0x30;
236 bool i2c_read = input_msg->request &
237 (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
238 u8 *data;
239
240 if (aux->native || i2c_read || ((input_msg->address != edid_address) &&
241 (input_msg->address != segment_address)))
242 return;
243
244
245 data = input_msg->buffer;
246 if (input_msg->address == segment_address)
247 aux->segment = *data;
248 else
249 aux->offset = *data;
250 }
251
252 /**
253 * dp_aux_transfer_helper() - helper function for EDID read transactions
254 *
255 * @aux: DP AUX private structure
256 * @input_msg: input message from DRM upstream APIs
257 * @send_seg: send the segment to sink
258 *
259 * return: void
260 *
261 * This helper function is used to fix EDID reads for non-compliant
262 * sinks that do not handle the i2c middle-of-transaction flag correctly.
263 */
dp_aux_transfer_helper(struct dp_aux_private * aux,struct drm_dp_aux_msg * input_msg,bool send_seg)264 static void dp_aux_transfer_helper(struct dp_aux_private *aux,
265 struct drm_dp_aux_msg *input_msg,
266 bool send_seg)
267 {
268 struct drm_dp_aux_msg helper_msg;
269 u32 message_size = 0x10;
270 u32 segment_address = 0x30;
271 u32 const edid_block_length = 0x80;
272 bool i2c_mot = input_msg->request & DP_AUX_I2C_MOT;
273 bool i2c_read = input_msg->request &
274 (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
275
276 if (!i2c_mot || !i2c_read || (input_msg->size == 0))
277 return;
278
279 /*
280 * Sending the segment value and EDID offset will be performed
281 * from the DRM upstream EDID driver for each block. Avoid
282 * duplicate AUX transactions related to this while reading the
283 * first 16 bytes of each block.
284 */
285 if (!(aux->offset % edid_block_length) || !send_seg)
286 goto end;
287
288 aux->read = false;
289 aux->cmd_busy = true;
290 aux->no_send_addr = true;
291 aux->no_send_stop = true;
292
293 /*
294 * Send the segment address for every i2c read in which the
295 * middle-of-tranaction flag is set. This is required to support EDID
296 * reads of more than 2 blocks as the segment address is reset to 0
297 * since we are overriding the middle-of-transaction flag for read
298 * transactions.
299 */
300
301 if (aux->segment) {
302 memset(&helper_msg, 0, sizeof(helper_msg));
303 helper_msg.address = segment_address;
304 helper_msg.buffer = &aux->segment;
305 helper_msg.size = 1;
306 dp_aux_cmd_fifo_tx(aux, &helper_msg);
307 }
308
309 /*
310 * Send the offset address for every i2c read in which the
311 * middle-of-transaction flag is set. This will ensure that the sink
312 * will update its read pointer and return the correct portion of the
313 * EDID buffer in the subsequent i2c read trasntion triggered in the
314 * native AUX transfer function.
315 */
316 memset(&helper_msg, 0, sizeof(helper_msg));
317 helper_msg.address = input_msg->address;
318 helper_msg.buffer = &aux->offset;
319 helper_msg.size = 1;
320 dp_aux_cmd_fifo_tx(aux, &helper_msg);
321
322 end:
323 aux->offset += message_size;
324 if (aux->offset == 0x80 || aux->offset == 0x100)
325 aux->segment = 0x0; /* reset segment at end of block */
326 }
327
328 /*
329 * This function does the real job to process an AUX transaction.
330 * It will call aux_reset() function to reset the AUX channel,
331 * if the waiting is timeout.
332 */
dp_aux_transfer(struct drm_dp_aux * dp_aux,struct drm_dp_aux_msg * msg)333 static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux,
334 struct drm_dp_aux_msg *msg)
335 {
336 ssize_t ret;
337 int const aux_cmd_native_max = 16;
338 int const aux_cmd_i2c_max = 128;
339 int const retry_count = 5;
340 struct dp_aux_private *aux = container_of(dp_aux,
341 struct dp_aux_private, dp_aux);
342
343 mutex_lock(&aux->mutex);
344
345 aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
346
347 /* Ignore address only message */
348 if ((msg->size == 0) || (msg->buffer == NULL)) {
349 msg->reply = aux->native ?
350 DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
351 ret = msg->size;
352 goto unlock_exit;
353 }
354
355 /* msg sanity check */
356 if ((aux->native && (msg->size > aux_cmd_native_max)) ||
357 (msg->size > aux_cmd_i2c_max)) {
358 DRM_ERROR("%s: invalid msg: size(%zu), request(%x)\n",
359 __func__, msg->size, msg->request);
360 ret = -EINVAL;
361 goto unlock_exit;
362 }
363
364 dp_aux_update_offset_and_segment(aux, msg);
365 dp_aux_transfer_helper(aux, msg, true);
366
367 aux->read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
368 aux->cmd_busy = true;
369
370 if (aux->read) {
371 aux->no_send_addr = true;
372 aux->no_send_stop = false;
373 } else {
374 aux->no_send_addr = true;
375 aux->no_send_stop = true;
376 }
377
378 ret = dp_aux_cmd_fifo_tx(aux, msg);
379
380 if (ret < 0) {
381 if (aux->native) {
382 aux->retry_cnt++;
383 if (!(aux->retry_cnt % retry_count))
384 dp_catalog_aux_update_cfg(aux->catalog);
385 dp_catalog_aux_reset(aux->catalog);
386 }
387 usleep_range(400, 500); /* at least 400us to next try */
388 goto unlock_exit;
389 }
390
391 if (aux->aux_error_num == DP_AUX_ERR_NONE) {
392 if (aux->read)
393 dp_aux_cmd_fifo_rx(aux, msg);
394
395 msg->reply = aux->native ?
396 DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
397 } else {
398 /* Reply defer to retry */
399 msg->reply = aux->native ?
400 DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
401 }
402
403 /* Return requested size for success or retry */
404 ret = msg->size;
405 aux->retry_cnt = 0;
406
407 unlock_exit:
408 aux->cmd_busy = false;
409 mutex_unlock(&aux->mutex);
410 return ret;
411 }
412
dp_aux_isr(struct drm_dp_aux * dp_aux)413 void dp_aux_isr(struct drm_dp_aux *dp_aux)
414 {
415 struct dp_aux_private *aux;
416
417 if (!dp_aux) {
418 DRM_ERROR("invalid input\n");
419 return;
420 }
421
422 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
423
424 aux->isr = dp_catalog_aux_get_irq(aux->catalog);
425
426 if (!aux->cmd_busy)
427 return;
428
429 if (aux->native)
430 dp_aux_native_handler(aux);
431 else
432 dp_aux_i2c_handler(aux);
433 }
434
dp_aux_reconfig(struct drm_dp_aux * dp_aux)435 void dp_aux_reconfig(struct drm_dp_aux *dp_aux)
436 {
437 struct dp_aux_private *aux;
438
439 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
440
441 dp_catalog_aux_update_cfg(aux->catalog);
442 dp_catalog_aux_reset(aux->catalog);
443 }
444
dp_aux_init(struct drm_dp_aux * dp_aux)445 void dp_aux_init(struct drm_dp_aux *dp_aux)
446 {
447 struct dp_aux_private *aux;
448
449 if (!dp_aux) {
450 DRM_ERROR("invalid input\n");
451 return;
452 }
453
454 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
455
456 dp_catalog_aux_enable(aux->catalog, true);
457 aux->retry_cnt = 0;
458 }
459
dp_aux_deinit(struct drm_dp_aux * dp_aux)460 void dp_aux_deinit(struct drm_dp_aux *dp_aux)
461 {
462 struct dp_aux_private *aux;
463
464 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
465
466 dp_catalog_aux_enable(aux->catalog, false);
467 }
468
dp_aux_register(struct drm_dp_aux * dp_aux)469 int dp_aux_register(struct drm_dp_aux *dp_aux)
470 {
471 struct dp_aux_private *aux;
472 int ret;
473
474 if (!dp_aux) {
475 DRM_ERROR("invalid input\n");
476 return -EINVAL;
477 }
478
479 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
480
481 aux->dp_aux.name = "dpu_dp_aux";
482 aux->dp_aux.dev = aux->dev;
483 aux->dp_aux.transfer = dp_aux_transfer;
484 ret = drm_dp_aux_register(&aux->dp_aux);
485 if (ret) {
486 DRM_ERROR("%s: failed to register drm aux: %d\n", __func__,
487 ret);
488 return ret;
489 }
490
491 return 0;
492 }
493
dp_aux_unregister(struct drm_dp_aux * dp_aux)494 void dp_aux_unregister(struct drm_dp_aux *dp_aux)
495 {
496 drm_dp_aux_unregister(dp_aux);
497 }
498
dp_aux_get(struct device * dev,struct dp_catalog * catalog)499 struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog)
500 {
501 struct dp_aux_private *aux;
502
503 if (!catalog) {
504 DRM_ERROR("invalid input\n");
505 return ERR_PTR(-ENODEV);
506 }
507
508 aux = devm_kzalloc(dev, sizeof(*aux), GFP_KERNEL);
509 if (!aux)
510 return ERR_PTR(-ENOMEM);
511
512 init_completion(&aux->comp);
513 aux->cmd_busy = false;
514 mutex_init(&aux->mutex);
515
516 aux->dev = dev;
517 aux->catalog = catalog;
518 aux->retry_cnt = 0;
519
520 return &aux->dp_aux;
521 }
522
dp_aux_put(struct drm_dp_aux * dp_aux)523 void dp_aux_put(struct drm_dp_aux *dp_aux)
524 {
525 struct dp_aux_private *aux;
526
527 if (!dp_aux)
528 return;
529
530 aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
531
532 mutex_destroy(&aux->mutex);
533
534 devm_kfree(aux->dev, aux);
535 }
536
