1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "smumgr.h"
25 #include "vega12_inc.h"
26 #include "soc15_common.h"
27 #include "smu9_smumgr.h"
28 #include "vega12_smumgr.h"
29 #include "vega12_ppsmc.h"
30 #include "vega12/smu9_driver_if.h"
31 #include "ppatomctrl.h"
32 #include "pp_debug.h"
33
34
35 /*
36 * Copy table from SMC into driver FB
37 * @param hwmgr the address of the HW manager
38 * @param table_id the driver's table ID to copy from
39 */
vega12_copy_table_from_smc(struct pp_hwmgr * hwmgr,uint8_t * table,int16_t table_id)40 static int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
41 uint8_t *table, int16_t table_id)
42 {
43 struct vega12_smumgr *priv =
44 (struct vega12_smumgr *)(hwmgr->smu_backend);
45 struct amdgpu_device *adev = hwmgr->adev;
46
47 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
48 "Invalid SMU Table ID!", return -EINVAL);
49 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
50 "Invalid SMU Table version!", return -EINVAL);
51 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
52 "Invalid SMU Table Length!", return -EINVAL);
53 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
54 PPSMC_MSG_SetDriverDramAddrHigh,
55 upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),
56 NULL) == 0,
57 "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL);
58 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
59 PPSMC_MSG_SetDriverDramAddrLow,
60 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
61 NULL) == 0,
62 "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
63 return -EINVAL);
64 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
65 PPSMC_MSG_TransferTableSmu2Dram,
66 table_id,
67 NULL) == 0,
68 "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
69 return -EINVAL);
70
71 /* flush hdp cache */
72 amdgpu_asic_flush_hdp(adev, NULL);
73
74 memcpy(table, priv->smu_tables.entry[table_id].table,
75 priv->smu_tables.entry[table_id].size);
76
77 return 0;
78 }
79
80 /*
81 * Copy table from Driver FB into SMC
82 * @param hwmgr the address of the HW manager
83 * @param table_id the table to copy from
84 */
vega12_copy_table_to_smc(struct pp_hwmgr * hwmgr,uint8_t * table,int16_t table_id)85 static int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr,
86 uint8_t *table, int16_t table_id)
87 {
88 struct vega12_smumgr *priv =
89 (struct vega12_smumgr *)(hwmgr->smu_backend);
90 struct amdgpu_device *adev = hwmgr->adev;
91
92 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
93 "Invalid SMU Table ID!", return -EINVAL);
94 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
95 "Invalid SMU Table version!", return -EINVAL);
96 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
97 "Invalid SMU Table Length!", return -EINVAL);
98
99 memcpy(priv->smu_tables.entry[table_id].table, table,
100 priv->smu_tables.entry[table_id].size);
101
102 amdgpu_asic_flush_hdp(adev, NULL);
103
104 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
105 PPSMC_MSG_SetDriverDramAddrHigh,
106 upper_32_bits(priv->smu_tables.entry[table_id].mc_addr),
107 NULL) == 0,
108 "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
109 return -EINVAL;);
110 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
111 PPSMC_MSG_SetDriverDramAddrLow,
112 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
113 NULL) == 0,
114 "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
115 return -EINVAL);
116 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
117 PPSMC_MSG_TransferTableDram2Smu,
118 table_id,
119 NULL) == 0,
120 "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
121 return -EINVAL);
122
123 return 0;
124 }
125
vega12_enable_smc_features(struct pp_hwmgr * hwmgr,bool enable,uint64_t feature_mask)126 int vega12_enable_smc_features(struct pp_hwmgr *hwmgr,
127 bool enable, uint64_t feature_mask)
128 {
129 uint32_t smu_features_low, smu_features_high;
130
131 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
132 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
133
134 if (enable) {
135 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
136 PPSMC_MSG_EnableSmuFeaturesLow, smu_features_low, NULL) == 0,
137 "[EnableDisableSMCFeatures] Attempt to enable SMU features Low failed!",
138 return -EINVAL);
139 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
140 PPSMC_MSG_EnableSmuFeaturesHigh, smu_features_high, NULL) == 0,
141 "[EnableDisableSMCFeatures] Attempt to enable SMU features High failed!",
142 return -EINVAL);
143 } else {
144 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
145 PPSMC_MSG_DisableSmuFeaturesLow, smu_features_low, NULL) == 0,
146 "[EnableDisableSMCFeatures] Attempt to disable SMU features Low failed!",
147 return -EINVAL);
148 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
149 PPSMC_MSG_DisableSmuFeaturesHigh, smu_features_high, NULL) == 0,
150 "[EnableDisableSMCFeatures] Attempt to disable SMU features High failed!",
151 return -EINVAL);
152 }
153
154 return 0;
155 }
156
vega12_get_enabled_smc_features(struct pp_hwmgr * hwmgr,uint64_t * features_enabled)157 int vega12_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
158 uint64_t *features_enabled)
159 {
160 uint32_t smc_features_low, smc_features_high;
161
162 if (features_enabled == NULL)
163 return -EINVAL;
164
165 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc(hwmgr,
166 PPSMC_MSG_GetEnabledSmuFeaturesLow,
167 &smc_features_low) == 0,
168 "[GetEnabledSMCFeatures] Attempt to get SMU features Low failed!",
169 return -EINVAL);
170
171 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc(hwmgr,
172 PPSMC_MSG_GetEnabledSmuFeaturesHigh,
173 &smc_features_high) == 0,
174 "[GetEnabledSMCFeatures] Attempt to get SMU features High failed!",
175 return -EINVAL);
176
177 *features_enabled = ((((uint64_t)smc_features_low << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
178 (((uint64_t)smc_features_high << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
179
180 return 0;
181 }
182
vega12_is_dpm_running(struct pp_hwmgr * hwmgr)183 static bool vega12_is_dpm_running(struct pp_hwmgr *hwmgr)
184 {
185 uint64_t features_enabled = 0;
186
187 vega12_get_enabled_smc_features(hwmgr, &features_enabled);
188
189 if (features_enabled & SMC_DPM_FEATURES)
190 return true;
191 else
192 return false;
193 }
194
vega12_set_tools_address(struct pp_hwmgr * hwmgr)195 static int vega12_set_tools_address(struct pp_hwmgr *hwmgr)
196 {
197 struct vega12_smumgr *priv =
198 (struct vega12_smumgr *)(hwmgr->smu_backend);
199
200 if (priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr) {
201 if (!smum_send_msg_to_smc_with_parameter(hwmgr,
202 PPSMC_MSG_SetToolsDramAddrHigh,
203 upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr),
204 NULL))
205 smum_send_msg_to_smc_with_parameter(hwmgr,
206 PPSMC_MSG_SetToolsDramAddrLow,
207 lower_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr),
208 NULL);
209 }
210 return 0;
211 }
212
vega12_smu_init(struct pp_hwmgr * hwmgr)213 static int vega12_smu_init(struct pp_hwmgr *hwmgr)
214 {
215 struct vega12_smumgr *priv;
216 unsigned long tools_size;
217 struct cgs_firmware_info info = {0};
218 int ret;
219
220 ret = cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU,
221 &info);
222 if (ret || !info.kptr)
223 return -EINVAL;
224
225 priv = kzalloc(sizeof(struct vega12_smumgr), GFP_KERNEL);
226 if (!priv)
227 return -ENOMEM;
228
229 hwmgr->smu_backend = priv;
230
231 /* allocate space for pptable */
232 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
233 sizeof(PPTable_t),
234 PAGE_SIZE,
235 AMDGPU_GEM_DOMAIN_VRAM,
236 &priv->smu_tables.entry[TABLE_PPTABLE].handle,
237 &priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
238 &priv->smu_tables.entry[TABLE_PPTABLE].table);
239 if (ret)
240 goto free_backend;
241
242 priv->smu_tables.entry[TABLE_PPTABLE].version = 0x01;
243 priv->smu_tables.entry[TABLE_PPTABLE].size = sizeof(PPTable_t);
244
245 /* allocate space for watermarks table */
246 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
247 sizeof(Watermarks_t),
248 PAGE_SIZE,
249 AMDGPU_GEM_DOMAIN_VRAM,
250 &priv->smu_tables.entry[TABLE_WATERMARKS].handle,
251 &priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
252 &priv->smu_tables.entry[TABLE_WATERMARKS].table);
253
254 if (ret)
255 goto err0;
256
257 priv->smu_tables.entry[TABLE_WATERMARKS].version = 0x01;
258 priv->smu_tables.entry[TABLE_WATERMARKS].size = sizeof(Watermarks_t);
259
260 tools_size = 0x19000;
261 if (tools_size) {
262 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
263 tools_size,
264 PAGE_SIZE,
265 AMDGPU_GEM_DOMAIN_VRAM,
266 &priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
267 &priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
268 &priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
269 if (ret)
270 goto err1;
271
272 priv->smu_tables.entry[TABLE_PMSTATUSLOG].version = 0x01;
273 priv->smu_tables.entry[TABLE_PMSTATUSLOG].size = tools_size;
274 }
275
276 /* allocate space for AVFS Fuse table */
277 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
278 sizeof(AvfsFuseOverride_t),
279 PAGE_SIZE,
280 AMDGPU_GEM_DOMAIN_VRAM,
281 &priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].handle,
282 &priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].mc_addr,
283 &priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].table);
284
285 if (ret)
286 goto err2;
287
288 priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].version = 0x01;
289 priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].size = sizeof(AvfsFuseOverride_t);
290
291 /* allocate space for OverDrive table */
292 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
293 sizeof(OverDriveTable_t),
294 PAGE_SIZE,
295 AMDGPU_GEM_DOMAIN_VRAM,
296 &priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
297 &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
298 &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
299 if (ret)
300 goto err3;
301
302 priv->smu_tables.entry[TABLE_OVERDRIVE].version = 0x01;
303 priv->smu_tables.entry[TABLE_OVERDRIVE].size = sizeof(OverDriveTable_t);
304
305 /* allocate space for SMU_METRICS table */
306 ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
307 sizeof(SmuMetrics_t),
308 PAGE_SIZE,
309 AMDGPU_GEM_DOMAIN_VRAM,
310 &priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
311 &priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
312 &priv->smu_tables.entry[TABLE_SMU_METRICS].table);
313 if (ret)
314 goto err4;
315
316 priv->smu_tables.entry[TABLE_SMU_METRICS].version = 0x01;
317 priv->smu_tables.entry[TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t);
318
319 return 0;
320
321 err4:
322 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
323 &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
324 &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
325 err3:
326 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].handle,
327 &priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].mc_addr,
328 &priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].table);
329 err2:
330 if (priv->smu_tables.entry[TABLE_PMSTATUSLOG].table)
331 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
332 &priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
333 &priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
334 err1:
335 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_WATERMARKS].handle,
336 &priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
337 &priv->smu_tables.entry[TABLE_WATERMARKS].table);
338 err0:
339 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PPTABLE].handle,
340 &priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
341 &priv->smu_tables.entry[TABLE_PPTABLE].table);
342 free_backend:
343 kfree(hwmgr->smu_backend);
344
345 return -EINVAL;
346 }
347
vega12_smu_fini(struct pp_hwmgr * hwmgr)348 static int vega12_smu_fini(struct pp_hwmgr *hwmgr)
349 {
350 struct vega12_smumgr *priv =
351 (struct vega12_smumgr *)(hwmgr->smu_backend);
352
353 if (priv) {
354 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PPTABLE].handle,
355 &priv->smu_tables.entry[TABLE_PPTABLE].mc_addr,
356 &priv->smu_tables.entry[TABLE_PPTABLE].table);
357 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_WATERMARKS].handle,
358 &priv->smu_tables.entry[TABLE_WATERMARKS].mc_addr,
359 &priv->smu_tables.entry[TABLE_WATERMARKS].table);
360 if (priv->smu_tables.entry[TABLE_PMSTATUSLOG].table)
361 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_PMSTATUSLOG].handle,
362 &priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr,
363 &priv->smu_tables.entry[TABLE_PMSTATUSLOG].table);
364 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].handle,
365 &priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].mc_addr,
366 &priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].table);
367 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
368 &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
369 &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
370 amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
371 &priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
372 &priv->smu_tables.entry[TABLE_SMU_METRICS].table);
373 kfree(hwmgr->smu_backend);
374 hwmgr->smu_backend = NULL;
375 }
376 return 0;
377 }
378
vega12_start_smu(struct pp_hwmgr * hwmgr)379 static int vega12_start_smu(struct pp_hwmgr *hwmgr)
380 {
381 PP_ASSERT_WITH_CODE(smu9_is_smc_ram_running(hwmgr),
382 "SMC is not running!",
383 return -EINVAL);
384
385 vega12_set_tools_address(hwmgr);
386
387 return 0;
388 }
389
vega12_smc_table_manager(struct pp_hwmgr * hwmgr,uint8_t * table,uint16_t table_id,bool rw)390 static int vega12_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
391 uint16_t table_id, bool rw)
392 {
393 int ret;
394
395 if (rw)
396 ret = vega12_copy_table_from_smc(hwmgr, table, table_id);
397 else
398 ret = vega12_copy_table_to_smc(hwmgr, table, table_id);
399
400 return ret;
401 }
402
403 const struct pp_smumgr_func vega12_smu_funcs = {
404 .name = "vega12_smu",
405 .smu_init = &vega12_smu_init,
406 .smu_fini = &vega12_smu_fini,
407 .start_smu = &vega12_start_smu,
408 .request_smu_load_specific_fw = NULL,
409 .send_msg_to_smc = &smu9_send_msg_to_smc,
410 .send_msg_to_smc_with_parameter = &smu9_send_msg_to_smc_with_parameter,
411 .download_pptable_settings = NULL,
412 .upload_pptable_settings = NULL,
413 .is_dpm_running = vega12_is_dpm_running,
414 .get_argument = smu9_get_argument,
415 .smc_table_manager = vega12_smc_table_manager,
416 };
417
