1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "core_status.h" 34 35 enum vline_select { 36 VLINE0, 37 VLINE1 38 }; 39 40 struct pipe_ctx; 41 struct dc_state; 42 struct dc_stream_status; 43 struct dc_writeback_info; 44 struct dchub_init_data; 45 struct dc_static_screen_params; 46 struct resource_pool; 47 struct dc_phy_addr_space_config; 48 struct dc_virtual_addr_space_config; 49 struct dpp; 50 struct dce_hwseq; 51 52 struct hw_sequencer_funcs { 53 /* Embedded Display Related */ 54 void (*edp_power_control)(struct dc_link *link, bool enable); 55 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 56 57 /* Pipe Programming Related */ 58 void (*init_hw)(struct dc *dc); 59 void (*power_down_on_boot)(struct dc *dc); 60 void (*enable_accelerated_mode)(struct dc *dc, 61 struct dc_state *context); 62 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 63 struct dc_state *context); 64 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); 65 void (*apply_ctx_for_surface)(struct dc *dc, 66 const struct dc_stream_state *stream, 67 int num_planes, struct dc_state *context); 68 void (*program_front_end_for_ctx)(struct dc *dc, 69 struct dc_state *context); 70 bool (*disconnect_pipes)(struct dc *dc, 71 struct dc_state *context); 72 void (*wait_for_pending_cleared)(struct dc *dc, 73 struct dc_state *context); 74 void (*post_unlock_program_front_end)(struct dc *dc, 75 struct dc_state *context); 76 void (*update_plane_addr)(const struct dc *dc, 77 struct pipe_ctx *pipe_ctx); 78 void (*update_dchub)(struct dce_hwseq *hws, 79 struct dchub_init_data *dh_data); 80 void (*wait_for_mpcc_disconnect)(struct dc *dc, 81 struct resource_pool *res_pool, 82 struct pipe_ctx *pipe_ctx); 83 void (*edp_backlight_control)( 84 struct dc_link *link, 85 bool enable); 86 void (*program_triplebuffer)(const struct dc *dc, 87 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 88 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 89 void (*power_down)(struct dc *dc); 90 91 /* Pipe Lock Related */ 92 void (*pipe_control_lock)(struct dc *dc, 93 struct pipe_ctx *pipe, bool lock); 94 void (*interdependent_update_lock)(struct dc *dc, 95 struct dc_state *context, bool lock); 96 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 97 bool flip_immediate); 98 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 99 100 /* Timing Related */ 101 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 102 struct crtc_position *position); 103 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 104 void (*calc_vupdate_position)( 105 struct dc *dc, 106 struct pipe_ctx *pipe_ctx, 107 uint32_t *start_line, 108 uint32_t *end_line); 109 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 110 int group_size, struct pipe_ctx *grouped_pipes[]); 111 void (*enable_timing_synchronization)(struct dc *dc, 112 int group_index, int group_size, 113 struct pipe_ctx *grouped_pipes[]); 114 void (*setup_periodic_interrupt)(struct dc *dc, 115 struct pipe_ctx *pipe_ctx, 116 enum vline_select vline); 117 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 118 unsigned int vmin, unsigned int vmax, 119 unsigned int vmid, unsigned int vmid_frame_number); 120 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 121 int num_pipes, 122 const struct dc_static_screen_params *events); 123 #ifndef TRIM_FSFT 124 bool (*optimize_timing_for_fsft)(struct dc *dc, 125 struct dc_crtc_timing *timing, 126 unsigned int max_input_rate_in_khz); 127 #endif 128 129 /* Stream Related */ 130 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 131 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 132 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 133 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 134 struct dc_link_settings *link_settings); 135 136 /* Bandwidth Related */ 137 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 138 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 139 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 140 141 /* Infopacket Related */ 142 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 143 void (*send_immediate_sdp_message)( 144 struct pipe_ctx *pipe_ctx, 145 const uint8_t *custom_sdp_message, 146 unsigned int sdp_message_size); 147 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 148 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 149 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 150 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 151 152 /* Cursor Related */ 153 void (*set_cursor_position)(struct pipe_ctx *pipe); 154 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 155 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 156 157 /* Colour Related */ 158 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 159 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 160 enum dc_color_space colorspace, 161 uint16_t *matrix, int opp_id); 162 163 /* VM Related */ 164 int (*init_sys_ctx)(struct dce_hwseq *hws, 165 struct dc *dc, 166 struct dc_phy_addr_space_config *pa_config); 167 void (*init_vm_ctx)(struct dce_hwseq *hws, 168 struct dc *dc, 169 struct dc_virtual_addr_space_config *va_config, 170 int vmid); 171 172 /* Writeback Related */ 173 void (*update_writeback)(struct dc *dc, 174 struct dc_writeback_info *wb_info, 175 struct dc_state *context); 176 void (*enable_writeback)(struct dc *dc, 177 struct dc_writeback_info *wb_info, 178 struct dc_state *context); 179 void (*disable_writeback)(struct dc *dc, 180 unsigned int dwb_pipe_inst); 181 182 bool (*mmhubbub_warmup)(struct dc *dc, 183 unsigned int num_dwb, 184 struct dc_writeback_info *wb_info); 185 186 /* Clock Related */ 187 enum dc_status (*set_clock)(struct dc *dc, 188 enum dc_clock_type clock_type, 189 uint32_t clk_khz, uint32_t stepping); 190 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 191 struct dc_clock_config *clock_cfg); 192 void (*optimize_pwr_state)(const struct dc *dc, 193 struct dc_state *context); 194 void (*exit_optimized_pwr_state)(const struct dc *dc, 195 struct dc_state *context); 196 197 /* Audio Related */ 198 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 199 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 200 201 /* Stereo 3D Related */ 202 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 203 204 /* HW State Logging Related */ 205 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 206 void (*get_hw_state)(struct dc *dc, char *pBuf, 207 unsigned int bufSize, unsigned int mask); 208 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 209 210 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 211 uint32_t backlight_pwm_u16_16, 212 uint32_t frame_ramp); 213 214 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 215 216 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 217 218 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 219 /* Idle Optimization Related */ 220 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 221 #endif 222 223 }; 224 225 void color_space_to_black_color( 226 const struct dc *dc, 227 enum dc_color_space colorspace, 228 struct tg_color *black_color); 229 230 bool hwss_wait_for_blank_complete( 231 struct timing_generator *tg); 232 233 const uint16_t *find_color_matrix( 234 enum dc_color_space color_space, 235 uint32_t *array_size); 236 237 #endif /* __DC_HW_SEQUENCER_H__ */ 238
