1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2017 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 */
7
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14
15 #include <dt-bindings/gpio/tegra186-gpio.h>
16 #include <dt-bindings/gpio/tegra194-gpio.h>
17
18 /* security registers */
19 #define TEGRA186_GPIO_CTL_SCR 0x0c
20 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
21 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
22
23 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
24
25 /* control registers */
26 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
27 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
28 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
29 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
30 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
35 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
36 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
37
38 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
39 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
40
41 #define TEGRA186_GPIO_INPUT 0x08
42 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
43
44 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
45 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
46
47 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
48 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
49
50 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
51
52 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
53
54 struct tegra_gpio_port {
55 const char *name;
56 unsigned int bank;
57 unsigned int port;
58 unsigned int pins;
59 };
60
61 struct tegra186_pin_range {
62 unsigned int offset;
63 const char *group;
64 };
65
66 struct tegra_gpio_soc {
67 const struct tegra_gpio_port *ports;
68 unsigned int num_ports;
69 const char *name;
70 unsigned int instance;
71
72 const struct tegra186_pin_range *pin_ranges;
73 unsigned int num_pin_ranges;
74 const char *pinmux;
75 };
76
77 struct tegra_gpio {
78 struct gpio_chip gpio;
79 struct irq_chip intc;
80 unsigned int num_irq;
81 unsigned int *irq;
82
83 const struct tegra_gpio_soc *soc;
84
85 void __iomem *secure;
86 void __iomem *base;
87 };
88
89 static const struct tegra_gpio_port *
tegra186_gpio_get_port(struct tegra_gpio * gpio,unsigned int * pin)90 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
91 {
92 unsigned int start = 0, i;
93
94 for (i = 0; i < gpio->soc->num_ports; i++) {
95 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
96
97 if (*pin >= start && *pin < start + port->pins) {
98 *pin -= start;
99 return port;
100 }
101
102 start += port->pins;
103 }
104
105 return NULL;
106 }
107
tegra186_gpio_get_base(struct tegra_gpio * gpio,unsigned int pin)108 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
109 unsigned int pin)
110 {
111 const struct tegra_gpio_port *port;
112 unsigned int offset;
113
114 port = tegra186_gpio_get_port(gpio, &pin);
115 if (!port)
116 return NULL;
117
118 offset = port->bank * 0x1000 + port->port * 0x200;
119
120 return gpio->base + offset + pin * 0x20;
121 }
122
tegra186_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)123 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
124 unsigned int offset)
125 {
126 struct tegra_gpio *gpio = gpiochip_get_data(chip);
127 void __iomem *base;
128 u32 value;
129
130 base = tegra186_gpio_get_base(gpio, offset);
131 if (WARN_ON(base == NULL))
132 return -ENODEV;
133
134 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
135 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
136 return GPIO_LINE_DIRECTION_OUT;
137
138 return GPIO_LINE_DIRECTION_IN;
139 }
140
tegra186_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)141 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
142 unsigned int offset)
143 {
144 struct tegra_gpio *gpio = gpiochip_get_data(chip);
145 void __iomem *base;
146 u32 value;
147
148 base = tegra186_gpio_get_base(gpio, offset);
149 if (WARN_ON(base == NULL))
150 return -ENODEV;
151
152 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
153 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
154 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
155
156 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
157 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
158 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
159 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
160
161 return 0;
162 }
163
tegra186_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int level)164 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
165 unsigned int offset, int level)
166 {
167 struct tegra_gpio *gpio = gpiochip_get_data(chip);
168 void __iomem *base;
169 u32 value;
170
171 /* configure output level first */
172 chip->set(chip, offset, level);
173
174 base = tegra186_gpio_get_base(gpio, offset);
175 if (WARN_ON(base == NULL))
176 return -EINVAL;
177
178 /* set the direction */
179 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
180 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
181 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
182
183 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
184 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
185 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
186 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
187
188 return 0;
189 }
190
tegra186_gpio_get(struct gpio_chip * chip,unsigned int offset)191 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
192 {
193 struct tegra_gpio *gpio = gpiochip_get_data(chip);
194 void __iomem *base;
195 u32 value;
196
197 base = tegra186_gpio_get_base(gpio, offset);
198 if (WARN_ON(base == NULL))
199 return -ENODEV;
200
201 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
202 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
203 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
204 else
205 value = readl(base + TEGRA186_GPIO_INPUT);
206
207 return value & BIT(0);
208 }
209
tegra186_gpio_set(struct gpio_chip * chip,unsigned int offset,int level)210 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
211 int level)
212 {
213 struct tegra_gpio *gpio = gpiochip_get_data(chip);
214 void __iomem *base;
215 u32 value;
216
217 base = tegra186_gpio_get_base(gpio, offset);
218 if (WARN_ON(base == NULL))
219 return;
220
221 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
222 if (level == 0)
223 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
224 else
225 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
226
227 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
228 }
229
tegra186_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)230 static int tegra186_gpio_set_config(struct gpio_chip *chip,
231 unsigned int offset,
232 unsigned long config)
233 {
234 struct tegra_gpio *gpio = gpiochip_get_data(chip);
235 u32 debounce, value;
236 void __iomem *base;
237
238 base = tegra186_gpio_get_base(gpio, offset);
239 if (base == NULL)
240 return -ENXIO;
241
242 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
243 return -ENOTSUPP;
244
245 debounce = pinconf_to_config_argument(config);
246
247 /*
248 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
249 * time.
250 */
251 if (debounce > 255000)
252 return -EINVAL;
253
254 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
255
256 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
257 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
258
259 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
260 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
261 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
262
263 return 0;
264 }
265
tegra186_gpio_add_pin_ranges(struct gpio_chip * chip)266 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
267 {
268 struct tegra_gpio *gpio = gpiochip_get_data(chip);
269 struct pinctrl_dev *pctldev;
270 struct device_node *np;
271 unsigned int i, j;
272 int err;
273
274 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
275 return 0;
276
277 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
278 if (!np)
279 return -ENODEV;
280
281 pctldev = of_pinctrl_get(np);
282 of_node_put(np);
283 if (!pctldev)
284 return -EPROBE_DEFER;
285
286 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
287 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
288 const char *group = gpio->soc->pin_ranges[i].group;
289
290 port = pin / 8;
291 pin = pin % 8;
292
293 if (port >= gpio->soc->num_ports) {
294 dev_warn(chip->parent, "invalid port %u for %s\n",
295 port, group);
296 continue;
297 }
298
299 for (j = 0; j < port; j++)
300 pin += gpio->soc->ports[j].pins;
301
302 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
303 if (err < 0)
304 return err;
305 }
306
307 return 0;
308 }
309
tegra186_gpio_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * spec,u32 * flags)310 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
311 const struct of_phandle_args *spec,
312 u32 *flags)
313 {
314 struct tegra_gpio *gpio = gpiochip_get_data(chip);
315 unsigned int port, pin, i, offset = 0;
316
317 if (WARN_ON(chip->of_gpio_n_cells < 2))
318 return -EINVAL;
319
320 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
321 return -EINVAL;
322
323 port = spec->args[0] / 8;
324 pin = spec->args[0] % 8;
325
326 if (port >= gpio->soc->num_ports) {
327 dev_err(chip->parent, "invalid port number: %u\n", port);
328 return -EINVAL;
329 }
330
331 for (i = 0; i < port; i++)
332 offset += gpio->soc->ports[i].pins;
333
334 if (flags)
335 *flags = spec->args[1];
336
337 return offset + pin;
338 }
339
tegra186_irq_ack(struct irq_data * data)340 static void tegra186_irq_ack(struct irq_data *data)
341 {
342 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
343 void __iomem *base;
344
345 base = tegra186_gpio_get_base(gpio, data->hwirq);
346 if (WARN_ON(base == NULL))
347 return;
348
349 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
350 }
351
tegra186_irq_mask(struct irq_data * data)352 static void tegra186_irq_mask(struct irq_data *data)
353 {
354 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
355 void __iomem *base;
356 u32 value;
357
358 base = tegra186_gpio_get_base(gpio, data->hwirq);
359 if (WARN_ON(base == NULL))
360 return;
361
362 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
363 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
364 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
365 }
366
tegra186_irq_unmask(struct irq_data * data)367 static void tegra186_irq_unmask(struct irq_data *data)
368 {
369 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
370 void __iomem *base;
371 u32 value;
372
373 base = tegra186_gpio_get_base(gpio, data->hwirq);
374 if (WARN_ON(base == NULL))
375 return;
376
377 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
378 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
379 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
380 }
381
tegra186_irq_set_type(struct irq_data * data,unsigned int type)382 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
383 {
384 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
385 void __iomem *base;
386 u32 value;
387
388 base = tegra186_gpio_get_base(gpio, data->hwirq);
389 if (WARN_ON(base == NULL))
390 return -ENODEV;
391
392 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
393 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
394 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
395
396 switch (type & IRQ_TYPE_SENSE_MASK) {
397 case IRQ_TYPE_NONE:
398 break;
399
400 case IRQ_TYPE_EDGE_RISING:
401 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
402 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
403 break;
404
405 case IRQ_TYPE_EDGE_FALLING:
406 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
407 break;
408
409 case IRQ_TYPE_EDGE_BOTH:
410 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
411 break;
412
413 case IRQ_TYPE_LEVEL_HIGH:
414 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
415 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
416 break;
417
418 case IRQ_TYPE_LEVEL_LOW:
419 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
420 break;
421
422 default:
423 return -EINVAL;
424 }
425
426 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
427
428 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
429 irq_set_handler_locked(data, handle_level_irq);
430 else
431 irq_set_handler_locked(data, handle_edge_irq);
432
433 if (data->parent_data)
434 return irq_chip_set_type_parent(data, type);
435
436 return 0;
437 }
438
tegra186_irq_set_wake(struct irq_data * data,unsigned int on)439 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
440 {
441 if (data->parent_data)
442 return irq_chip_set_wake_parent(data, on);
443
444 return 0;
445 }
446
tegra186_gpio_irq(struct irq_desc * desc)447 static void tegra186_gpio_irq(struct irq_desc *desc)
448 {
449 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
450 struct irq_domain *domain = gpio->gpio.irq.domain;
451 struct irq_chip *chip = irq_desc_get_chip(desc);
452 unsigned int parent = irq_desc_get_irq(desc);
453 unsigned int i, offset = 0;
454
455 chained_irq_enter(chip, desc);
456
457 for (i = 0; i < gpio->soc->num_ports; i++) {
458 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
459 unsigned int pin, irq;
460 unsigned long value;
461 void __iomem *base;
462
463 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
464
465 /* skip ports that are not associated with this bank */
466 if (parent != gpio->irq[port->bank])
467 goto skip;
468
469 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
470
471 for_each_set_bit(pin, &value, port->pins) {
472 irq = irq_find_mapping(domain, offset + pin);
473 if (WARN_ON(irq == 0))
474 continue;
475
476 generic_handle_irq(irq);
477 }
478
479 skip:
480 offset += port->pins;
481 }
482
483 chained_irq_exit(chip, desc);
484 }
485
tegra186_gpio_irq_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)486 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
487 struct irq_fwspec *fwspec,
488 unsigned long *hwirq,
489 unsigned int *type)
490 {
491 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
492 unsigned int port, pin, i, offset = 0;
493
494 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
495 return -EINVAL;
496
497 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
498 return -EINVAL;
499
500 port = fwspec->param[0] / 8;
501 pin = fwspec->param[0] % 8;
502
503 if (port >= gpio->soc->num_ports)
504 return -EINVAL;
505
506 for (i = 0; i < port; i++)
507 offset += gpio->soc->ports[i].pins;
508
509 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
510 *hwirq = offset + pin;
511
512 return 0;
513 }
514
tegra186_gpio_populate_parent_fwspec(struct gpio_chip * chip,unsigned int parent_hwirq,unsigned int parent_type)515 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
516 unsigned int parent_hwirq,
517 unsigned int parent_type)
518 {
519 struct tegra_gpio *gpio = gpiochip_get_data(chip);
520 struct irq_fwspec *fwspec;
521
522 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
523 if (!fwspec)
524 return NULL;
525
526 fwspec->fwnode = chip->irq.parent_domain->fwnode;
527 fwspec->param_count = 3;
528 fwspec->param[0] = gpio->soc->instance;
529 fwspec->param[1] = parent_hwirq;
530 fwspec->param[2] = parent_type;
531
532 return fwspec;
533 }
534
tegra186_gpio_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int hwirq,unsigned int type,unsigned int * parent_hwirq,unsigned int * parent_type)535 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
536 unsigned int hwirq,
537 unsigned int type,
538 unsigned int *parent_hwirq,
539 unsigned int *parent_type)
540 {
541 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
542 *parent_type = type;
543
544 return 0;
545 }
546
tegra186_gpio_child_offset_to_irq(struct gpio_chip * chip,unsigned int offset)547 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
548 unsigned int offset)
549 {
550 struct tegra_gpio *gpio = gpiochip_get_data(chip);
551 unsigned int i;
552
553 for (i = 0; i < gpio->soc->num_ports; i++) {
554 if (offset < gpio->soc->ports[i].pins)
555 break;
556
557 offset -= gpio->soc->ports[i].pins;
558 }
559
560 return offset + i * 8;
561 }
562
563 static const struct of_device_id tegra186_pmc_of_match[] = {
564 { .compatible = "nvidia,tegra186-pmc" },
565 { .compatible = "nvidia,tegra194-pmc" },
566 { /* sentinel */ }
567 };
568
tegra186_gpio_init_route_mapping(struct tegra_gpio * gpio)569 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
570 {
571 unsigned int i, j;
572 u32 value;
573
574 for (i = 0; i < gpio->soc->num_ports; i++) {
575 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
576 unsigned int offset, p = port->port;
577 void __iomem *base;
578
579 base = gpio->secure + port->bank * 0x1000 + 0x800;
580
581 value = readl(base + TEGRA186_GPIO_CTL_SCR);
582
583 /*
584 * For controllers that haven't been locked down yet, make
585 * sure to program the default interrupt route mapping.
586 */
587 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
588 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
589 for (j = 0; j < 8; j++) {
590 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
591
592 value = readl(base + offset);
593 value = BIT(port->pins) - 1;
594 writel(value, base + offset);
595 }
596 }
597 }
598 }
599
tegra186_gpio_probe(struct platform_device * pdev)600 static int tegra186_gpio_probe(struct platform_device *pdev)
601 {
602 unsigned int i, j, offset;
603 struct gpio_irq_chip *irq;
604 struct tegra_gpio *gpio;
605 struct device_node *np;
606 char **names;
607 int err;
608
609 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
610 if (!gpio)
611 return -ENOMEM;
612
613 gpio->soc = of_device_get_match_data(&pdev->dev);
614
615 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
616 if (IS_ERR(gpio->secure))
617 return PTR_ERR(gpio->secure);
618
619 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
620 if (IS_ERR(gpio->base))
621 return PTR_ERR(gpio->base);
622
623 err = platform_irq_count(pdev);
624 if (err < 0)
625 return err;
626
627 gpio->num_irq = err;
628
629 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
630 GFP_KERNEL);
631 if (!gpio->irq)
632 return -ENOMEM;
633
634 for (i = 0; i < gpio->num_irq; i++) {
635 err = platform_get_irq(pdev, i);
636 if (err < 0)
637 return err;
638
639 gpio->irq[i] = err;
640 }
641
642 gpio->gpio.label = gpio->soc->name;
643 gpio->gpio.parent = &pdev->dev;
644
645 gpio->gpio.request = gpiochip_generic_request;
646 gpio->gpio.free = gpiochip_generic_free;
647 gpio->gpio.get_direction = tegra186_gpio_get_direction;
648 gpio->gpio.direction_input = tegra186_gpio_direction_input;
649 gpio->gpio.direction_output = tegra186_gpio_direction_output;
650 gpio->gpio.get = tegra186_gpio_get,
651 gpio->gpio.set = tegra186_gpio_set;
652 gpio->gpio.set_config = tegra186_gpio_set_config;
653 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
654
655 gpio->gpio.base = -1;
656
657 for (i = 0; i < gpio->soc->num_ports; i++)
658 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
659
660 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
661 sizeof(*names), GFP_KERNEL);
662 if (!names)
663 return -ENOMEM;
664
665 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
666 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
667 char *name;
668
669 for (j = 0; j < port->pins; j++) {
670 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
671 "P%s.%02x", port->name, j);
672 if (!name)
673 return -ENOMEM;
674
675 names[offset + j] = name;
676 }
677
678 offset += port->pins;
679 }
680
681 gpio->gpio.names = (const char * const *)names;
682
683 gpio->gpio.of_node = pdev->dev.of_node;
684 gpio->gpio.of_gpio_n_cells = 2;
685 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
686
687 gpio->intc.name = pdev->dev.of_node->name;
688 gpio->intc.irq_ack = tegra186_irq_ack;
689 gpio->intc.irq_mask = tegra186_irq_mask;
690 gpio->intc.irq_unmask = tegra186_irq_unmask;
691 gpio->intc.irq_set_type = tegra186_irq_set_type;
692 gpio->intc.irq_set_wake = tegra186_irq_set_wake;
693
694 irq = &gpio->gpio.irq;
695 irq->chip = &gpio->intc;
696 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
697 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
698 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
699 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
700 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
701 irq->handler = handle_simple_irq;
702 irq->default_type = IRQ_TYPE_NONE;
703 irq->parent_handler = tegra186_gpio_irq;
704 irq->parent_handler_data = gpio;
705 irq->num_parents = gpio->num_irq;
706 irq->parents = gpio->irq;
707
708 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
709 if (np) {
710 irq->parent_domain = irq_find_host(np);
711 of_node_put(np);
712
713 if (!irq->parent_domain)
714 return -EPROBE_DEFER;
715 }
716
717 tegra186_gpio_init_route_mapping(gpio);
718
719 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
720 sizeof(*irq->map), GFP_KERNEL);
721 if (!irq->map)
722 return -ENOMEM;
723
724 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
725 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
726
727 for (j = 0; j < port->pins; j++)
728 irq->map[offset + j] = irq->parents[port->bank];
729
730 offset += port->pins;
731 }
732
733 platform_set_drvdata(pdev, gpio);
734
735 err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
736 if (err < 0)
737 return err;
738
739 return 0;
740 }
741
tegra186_gpio_remove(struct platform_device * pdev)742 static int tegra186_gpio_remove(struct platform_device *pdev)
743 {
744 return 0;
745 }
746
747 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
748 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
749 .name = #_name, \
750 .bank = _bank, \
751 .port = _port, \
752 .pins = _pins, \
753 }
754
755 static const struct tegra_gpio_port tegra186_main_ports[] = {
756 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
757 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
758 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
759 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
760 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
761 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
762 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
763 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
764 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
765 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
766 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
767 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
768 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
769 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
770 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
771 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
772 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
773 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
774 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
775 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
776 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
777 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
778 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
779 };
780
781 static const struct tegra_gpio_soc tegra186_main_soc = {
782 .num_ports = ARRAY_SIZE(tegra186_main_ports),
783 .ports = tegra186_main_ports,
784 .name = "tegra186-gpio",
785 .instance = 0,
786 };
787
788 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
789 [TEGRA186_AON_GPIO_PORT_##_name] = { \
790 .name = #_name, \
791 .bank = _bank, \
792 .port = _port, \
793 .pins = _pins, \
794 }
795
796 static const struct tegra_gpio_port tegra186_aon_ports[] = {
797 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
798 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
799 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
800 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
801 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
802 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
803 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
804 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
805 };
806
807 static const struct tegra_gpio_soc tegra186_aon_soc = {
808 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
809 .ports = tegra186_aon_ports,
810 .name = "tegra186-gpio-aon",
811 .instance = 1,
812 };
813
814 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
815 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
816 .name = #_name, \
817 .bank = _bank, \
818 .port = _port, \
819 .pins = _pins, \
820 }
821
822 static const struct tegra_gpio_port tegra194_main_ports[] = {
823 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
824 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
825 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
826 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
827 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
828 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
829 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
830 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
831 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
832 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
833 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
834 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
835 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
836 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
837 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
838 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
839 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
840 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
841 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
842 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
843 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
844 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
845 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
846 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
847 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
848 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
849 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
850 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
851 };
852
853 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
854 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
855 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
856 };
857
858 static const struct tegra_gpio_soc tegra194_main_soc = {
859 .num_ports = ARRAY_SIZE(tegra194_main_ports),
860 .ports = tegra194_main_ports,
861 .name = "tegra194-gpio",
862 .instance = 0,
863 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
864 .pin_ranges = tegra194_main_pin_ranges,
865 .pinmux = "nvidia,tegra194-pinmux",
866 };
867
868 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
869 [TEGRA194_AON_GPIO_PORT_##_name] = { \
870 .name = #_name, \
871 .bank = _bank, \
872 .port = _port, \
873 .pins = _pins, \
874 }
875
876 static const struct tegra_gpio_port tegra194_aon_ports[] = {
877 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
878 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
879 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
880 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
881 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
882 };
883
884 static const struct tegra_gpio_soc tegra194_aon_soc = {
885 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
886 .ports = tegra194_aon_ports,
887 .name = "tegra194-gpio-aon",
888 .instance = 1,
889 };
890
891 static const struct of_device_id tegra186_gpio_of_match[] = {
892 {
893 .compatible = "nvidia,tegra186-gpio",
894 .data = &tegra186_main_soc
895 }, {
896 .compatible = "nvidia,tegra186-gpio-aon",
897 .data = &tegra186_aon_soc
898 }, {
899 .compatible = "nvidia,tegra194-gpio",
900 .data = &tegra194_main_soc
901 }, {
902 .compatible = "nvidia,tegra194-gpio-aon",
903 .data = &tegra194_aon_soc
904 }, {
905 /* sentinel */
906 }
907 };
908 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
909
910 static struct platform_driver tegra186_gpio_driver = {
911 .driver = {
912 .name = "tegra186-gpio",
913 .of_match_table = tegra186_gpio_of_match,
914 },
915 .probe = tegra186_gpio_probe,
916 .remove = tegra186_gpio_remove,
917 };
918 module_platform_driver(tegra186_gpio_driver);
919
920 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
921 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
922 MODULE_LICENSE("GPL v2");
923
