1 /*
2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2016 Freescale Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
15 #include <linux/io.h>
16 #include <linux/of.h>
17 #include <linux/of_gpio.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/slab.h>
22 #include <linux/irq.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/bitops.h>
25 #include <linux/interrupt.h>
26
27 #define MPC8XXX_GPIO_PINS 32
28
29 #define GPIO_DIR 0x00
30 #define GPIO_ODR 0x04
31 #define GPIO_DAT 0x08
32 #define GPIO_IER 0x0c
33 #define GPIO_IMR 0x10
34 #define GPIO_ICR 0x14
35 #define GPIO_ICR2 0x18
36 #define GPIO_IBE 0x18
37
38 struct mpc8xxx_gpio_chip {
39 struct gpio_chip gc;
40 void __iomem *regs;
41 raw_spinlock_t lock;
42
43 int (*direction_output)(struct gpio_chip *chip,
44 unsigned offset, int value);
45
46 struct irq_domain *irq;
47 unsigned int irqn;
48 };
49
50 /*
51 * This hardware has a big endian bit assignment such that GPIO line 0 is
52 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
53 * This inline helper give the right bitmask for a certain line.
54 */
mpc_pin2mask(unsigned int offset)55 static inline u32 mpc_pin2mask(unsigned int offset)
56 {
57 return BIT(31 - offset);
58 }
59
60 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
61 * defined as output cannot be determined by reading GPDAT register,
62 * so we use shadow data register instead. The status of input pins
63 * is determined by reading GPDAT register.
64 */
mpc8572_gpio_get(struct gpio_chip * gc,unsigned int gpio)65 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
66 {
67 u32 val;
68 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
69 u32 out_mask, out_shadow;
70
71 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
72 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
73 out_shadow = gc->bgpio_data & out_mask;
74
75 return !!((val | out_shadow) & mpc_pin2mask(gpio));
76 }
77
mpc5121_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)78 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
79 unsigned int gpio, int val)
80 {
81 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
82 /* GPIO 28..31 are input only on MPC5121 */
83 if (gpio >= 28)
84 return -EINVAL;
85
86 return mpc8xxx_gc->direction_output(gc, gpio, val);
87 }
88
mpc5125_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)89 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
90 unsigned int gpio, int val)
91 {
92 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
93 /* GPIO 0..3 are input only on MPC5125 */
94 if (gpio <= 3)
95 return -EINVAL;
96
97 return mpc8xxx_gc->direction_output(gc, gpio, val);
98 }
99
mpc8xxx_gpio_to_irq(struct gpio_chip * gc,unsigned offset)100 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
101 {
102 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
103
104 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
105 return irq_create_mapping(mpc8xxx_gc->irq, offset);
106 else
107 return -ENXIO;
108 }
109
mpc8xxx_gpio_irq_cascade(int irq,void * data)110 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
111 {
112 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
113 struct gpio_chip *gc = &mpc8xxx_gc->gc;
114 unsigned long mask;
115 int i;
116
117 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
118 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
119 for_each_set_bit(i, &mask, 32)
120 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));
121
122 return IRQ_HANDLED;
123 }
124
mpc8xxx_irq_unmask(struct irq_data * d)125 static void mpc8xxx_irq_unmask(struct irq_data *d)
126 {
127 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
128 struct gpio_chip *gc = &mpc8xxx_gc->gc;
129 unsigned long flags;
130
131 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
132
133 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
134 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
135 | mpc_pin2mask(irqd_to_hwirq(d)));
136
137 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
138 }
139
mpc8xxx_irq_mask(struct irq_data * d)140 static void mpc8xxx_irq_mask(struct irq_data *d)
141 {
142 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
143 struct gpio_chip *gc = &mpc8xxx_gc->gc;
144 unsigned long flags;
145
146 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
147
148 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
149 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
150 & ~mpc_pin2mask(irqd_to_hwirq(d)));
151
152 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
153 }
154
mpc8xxx_irq_ack(struct irq_data * d)155 static void mpc8xxx_irq_ack(struct irq_data *d)
156 {
157 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
158 struct gpio_chip *gc = &mpc8xxx_gc->gc;
159
160 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
161 mpc_pin2mask(irqd_to_hwirq(d)));
162 }
163
mpc8xxx_irq_set_type(struct irq_data * d,unsigned int flow_type)164 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
165 {
166 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
167 struct gpio_chip *gc = &mpc8xxx_gc->gc;
168 unsigned long flags;
169
170 switch (flow_type) {
171 case IRQ_TYPE_EDGE_FALLING:
172 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
173 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
174 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
175 | mpc_pin2mask(irqd_to_hwirq(d)));
176 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
177 break;
178
179 case IRQ_TYPE_EDGE_BOTH:
180 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
181 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
182 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
183 & ~mpc_pin2mask(irqd_to_hwirq(d)));
184 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
185 break;
186
187 default:
188 return -EINVAL;
189 }
190
191 return 0;
192 }
193
mpc512x_irq_set_type(struct irq_data * d,unsigned int flow_type)194 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
195 {
196 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
197 struct gpio_chip *gc = &mpc8xxx_gc->gc;
198 unsigned long gpio = irqd_to_hwirq(d);
199 void __iomem *reg;
200 unsigned int shift;
201 unsigned long flags;
202
203 if (gpio < 16) {
204 reg = mpc8xxx_gc->regs + GPIO_ICR;
205 shift = (15 - gpio) * 2;
206 } else {
207 reg = mpc8xxx_gc->regs + GPIO_ICR2;
208 shift = (15 - (gpio % 16)) * 2;
209 }
210
211 switch (flow_type) {
212 case IRQ_TYPE_EDGE_FALLING:
213 case IRQ_TYPE_LEVEL_LOW:
214 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
215 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
216 | (2 << shift));
217 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
218 break;
219
220 case IRQ_TYPE_EDGE_RISING:
221 case IRQ_TYPE_LEVEL_HIGH:
222 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
223 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
224 | (1 << shift));
225 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
226 break;
227
228 case IRQ_TYPE_EDGE_BOTH:
229 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
230 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
231 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
232 break;
233
234 default:
235 return -EINVAL;
236 }
237
238 return 0;
239 }
240
241 static struct irq_chip mpc8xxx_irq_chip = {
242 .name = "mpc8xxx-gpio",
243 .irq_unmask = mpc8xxx_irq_unmask,
244 .irq_mask = mpc8xxx_irq_mask,
245 .irq_ack = mpc8xxx_irq_ack,
246 /* this might get overwritten in mpc8xxx_probe() */
247 .irq_set_type = mpc8xxx_irq_set_type,
248 };
249
mpc8xxx_gpio_irq_map(struct irq_domain * h,unsigned int irq,irq_hw_number_t hwirq)250 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
251 irq_hw_number_t hwirq)
252 {
253 irq_set_chip_data(irq, h->host_data);
254 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
255
256 return 0;
257 }
258
259 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
260 .map = mpc8xxx_gpio_irq_map,
261 .xlate = irq_domain_xlate_twocell,
262 };
263
264 struct mpc8xxx_gpio_devtype {
265 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
266 int (*gpio_get)(struct gpio_chip *, unsigned int);
267 int (*irq_set_type)(struct irq_data *, unsigned int);
268 };
269
270 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
271 .gpio_dir_out = mpc5121_gpio_dir_out,
272 .irq_set_type = mpc512x_irq_set_type,
273 };
274
275 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
276 .gpio_dir_out = mpc5125_gpio_dir_out,
277 .irq_set_type = mpc512x_irq_set_type,
278 };
279
280 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
281 .gpio_get = mpc8572_gpio_get,
282 };
283
284 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
285 .irq_set_type = mpc8xxx_irq_set_type,
286 };
287
288 static const struct of_device_id mpc8xxx_gpio_ids[] = {
289 { .compatible = "fsl,mpc8349-gpio", },
290 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
291 { .compatible = "fsl,mpc8610-gpio", },
292 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
293 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
294 { .compatible = "fsl,pq3-gpio", },
295 { .compatible = "fsl,ls1028a-gpio", },
296 { .compatible = "fsl,ls1088a-gpio", },
297 { .compatible = "fsl,qoriq-gpio", },
298 {}
299 };
300
mpc8xxx_probe(struct platform_device * pdev)301 static int mpc8xxx_probe(struct platform_device *pdev)
302 {
303 struct device_node *np = pdev->dev.of_node;
304 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
305 struct gpio_chip *gc;
306 const struct mpc8xxx_gpio_devtype *devtype =
307 of_device_get_match_data(&pdev->dev);
308 int ret;
309
310 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
311 if (!mpc8xxx_gc)
312 return -ENOMEM;
313
314 platform_set_drvdata(pdev, mpc8xxx_gc);
315
316 raw_spin_lock_init(&mpc8xxx_gc->lock);
317
318 mpc8xxx_gc->regs = of_iomap(np, 0);
319 if (!mpc8xxx_gc->regs)
320 return -ENOMEM;
321
322 gc = &mpc8xxx_gc->gc;
323 gc->parent = &pdev->dev;
324
325 if (of_property_read_bool(np, "little-endian")) {
326 ret = bgpio_init(gc, &pdev->dev, 4,
327 mpc8xxx_gc->regs + GPIO_DAT,
328 NULL, NULL,
329 mpc8xxx_gc->regs + GPIO_DIR, NULL,
330 BGPIOF_BIG_ENDIAN);
331 if (ret)
332 goto err;
333 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
334 } else {
335 ret = bgpio_init(gc, &pdev->dev, 4,
336 mpc8xxx_gc->regs + GPIO_DAT,
337 NULL, NULL,
338 mpc8xxx_gc->regs + GPIO_DIR, NULL,
339 BGPIOF_BIG_ENDIAN
340 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
341 if (ret)
342 goto err;
343 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
344 }
345
346 mpc8xxx_gc->direction_output = gc->direction_output;
347
348 if (!devtype)
349 devtype = &mpc8xxx_gpio_devtype_default;
350
351 /*
352 * It's assumed that only a single type of gpio controller is available
353 * on the current machine, so overwriting global data is fine.
354 */
355 if (devtype->irq_set_type)
356 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
357
358 if (devtype->gpio_dir_out)
359 gc->direction_output = devtype->gpio_dir_out;
360 if (devtype->gpio_get)
361 gc->get = devtype->gpio_get;
362
363 gc->to_irq = mpc8xxx_gpio_to_irq;
364
365 /*
366 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
367 * the input enable of each individual GPIO port. When an individual
368 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
369 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
370 * the port value to the GPIO Data Register.
371 */
372 if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
373 of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
374 of_device_is_compatible(np, "fsl,ls1088a-gpio"))
375 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
376
377 ret = gpiochip_add_data(gc, mpc8xxx_gc);
378 if (ret) {
379 pr_err("%pOF: GPIO chip registration failed with status %d\n",
380 np, ret);
381 goto err;
382 }
383
384 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
385 if (!mpc8xxx_gc->irqn)
386 return 0;
387
388 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
389 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
390 if (!mpc8xxx_gc->irq)
391 return 0;
392
393 /* ack and mask all irqs */
394 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
395 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
396
397 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
398 mpc8xxx_gpio_irq_cascade,
399 IRQF_SHARED, "gpio-cascade",
400 mpc8xxx_gc);
401 if (ret) {
402 dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n",
403 np->full_name, mpc8xxx_gc->irqn, ret);
404 goto err;
405 }
406
407 return 0;
408 err:
409 iounmap(mpc8xxx_gc->regs);
410 return ret;
411 }
412
mpc8xxx_remove(struct platform_device * pdev)413 static int mpc8xxx_remove(struct platform_device *pdev)
414 {
415 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
416
417 if (mpc8xxx_gc->irq) {
418 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
419 irq_domain_remove(mpc8xxx_gc->irq);
420 }
421
422 gpiochip_remove(&mpc8xxx_gc->gc);
423 iounmap(mpc8xxx_gc->regs);
424
425 return 0;
426 }
427
428 static struct platform_driver mpc8xxx_plat_driver = {
429 .probe = mpc8xxx_probe,
430 .remove = mpc8xxx_remove,
431 .driver = {
432 .name = "gpio-mpc8xxx",
433 .of_match_table = mpc8xxx_gpio_ids,
434 },
435 };
436
mpc8xxx_init(void)437 static int __init mpc8xxx_init(void)
438 {
439 return platform_driver_register(&mpc8xxx_plat_driver);
440 }
441
442 arch_initcall(mpc8xxx_init);
443
