1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADMA driver for Nvidia's Tegra210 ADMA controller.
4 *
5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/iopoll.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/of_dma.h>
13 #include <linux/of_irq.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/slab.h>
16
17 #include "virt-dma.h"
18
19 #define ADMA_CH_CMD 0x00
20 #define ADMA_CH_STATUS 0x0c
21 #define ADMA_CH_STATUS_XFER_EN BIT(0)
22 #define ADMA_CH_STATUS_XFER_PAUSED BIT(1)
23
24 #define ADMA_CH_INT_STATUS 0x10
25 #define ADMA_CH_INT_STATUS_XFER_DONE BIT(0)
26
27 #define ADMA_CH_INT_CLEAR 0x1c
28 #define ADMA_CH_CTRL 0x24
29 #define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12)
30 #define ADMA_CH_CTRL_DIR_AHUB2MEM 2
31 #define ADMA_CH_CTRL_DIR_MEM2AHUB 4
32 #define ADMA_CH_CTRL_MODE_CONTINUOUS (2 << 8)
33 #define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1)
34 #define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0
35
36 #define ADMA_CH_CONFIG 0x28
37 #define ADMA_CH_CONFIG_SRC_BUF(val) (((val) & 0x7) << 28)
38 #define ADMA_CH_CONFIG_TRG_BUF(val) (((val) & 0x7) << 24)
39 #define ADMA_CH_CONFIG_BURST_SIZE_SHIFT 20
40 #define ADMA_CH_CONFIG_MAX_BURST_SIZE 16
41 #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf)
42 #define ADMA_CH_CONFIG_MAX_BUFS 8
43 #define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4)
44
45 #define ADMA_CH_FIFO_CTRL 0x2c
46 #define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0xf) << 8)
47 #define TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0xf)
48 #define TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0x1f) << 8)
49 #define TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0x1f)
50
51 #define ADMA_CH_LOWER_SRC_ADDR 0x34
52 #define ADMA_CH_LOWER_TRG_ADDR 0x3c
53 #define ADMA_CH_TC 0x44
54 #define ADMA_CH_TC_COUNT_MASK 0x3ffffffc
55
56 #define ADMA_CH_XFER_STATUS 0x54
57 #define ADMA_CH_XFER_STATUS_COUNT_MASK 0xffff
58
59 #define ADMA_GLOBAL_CMD 0x00
60 #define ADMA_GLOBAL_SOFT_RESET 0x04
61
62 #define TEGRA_ADMA_BURST_COMPLETE_TIME 20
63
64 #define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
65 TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(3))
66
67 #define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
68 TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(3))
69
70 #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
71
72 struct tegra_adma;
73
74 /*
75 * struct tegra_adma_chip_data - Tegra chip specific data
76 * @global_reg_offset: Register offset of DMA global register.
77 * @global_int_clear: Register offset of DMA global interrupt clear.
78 * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
79 * @ch_req_rx_shift: Register offset for AHUB receive channel select.
80 * @ch_base_offset: Register offset of DMA channel registers.
81 * @has_outstanding_reqs: If DMA channel can have outstanding requests.
82 * @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
83 * @ch_req_mask: Mask for Tx or Rx channel select.
84 * @ch_req_max: Maximum number of Tx or Rx channels available.
85 * @ch_reg_size: Size of DMA channel register space.
86 * @nr_channels: Number of DMA channels available.
87 */
88 struct tegra_adma_chip_data {
89 unsigned int (*adma_get_burst_config)(unsigned int burst_size);
90 unsigned int global_reg_offset;
91 unsigned int global_int_clear;
92 unsigned int ch_req_tx_shift;
93 unsigned int ch_req_rx_shift;
94 unsigned int ch_base_offset;
95 unsigned int ch_fifo_ctrl;
96 unsigned int ch_req_mask;
97 unsigned int ch_req_max;
98 unsigned int ch_reg_size;
99 unsigned int nr_channels;
100 bool has_outstanding_reqs;
101 };
102
103 /*
104 * struct tegra_adma_chan_regs - Tegra ADMA channel registers
105 */
106 struct tegra_adma_chan_regs {
107 unsigned int ctrl;
108 unsigned int config;
109 unsigned int src_addr;
110 unsigned int trg_addr;
111 unsigned int fifo_ctrl;
112 unsigned int cmd;
113 unsigned int tc;
114 };
115
116 /*
117 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
118 */
119 struct tegra_adma_desc {
120 struct virt_dma_desc vd;
121 struct tegra_adma_chan_regs ch_regs;
122 size_t buf_len;
123 size_t period_len;
124 size_t num_periods;
125 };
126
127 /*
128 * struct tegra_adma_chan - Tegra ADMA channel information
129 */
130 struct tegra_adma_chan {
131 struct virt_dma_chan vc;
132 struct tegra_adma_desc *desc;
133 struct tegra_adma *tdma;
134 int irq;
135 void __iomem *chan_addr;
136
137 /* Slave channel configuration info */
138 struct dma_slave_config sconfig;
139 enum dma_transfer_direction sreq_dir;
140 unsigned int sreq_index;
141 bool sreq_reserved;
142 struct tegra_adma_chan_regs ch_regs;
143
144 /* Transfer count and position info */
145 unsigned int tx_buf_count;
146 unsigned int tx_buf_pos;
147 };
148
149 /*
150 * struct tegra_adma - Tegra ADMA controller information
151 */
152 struct tegra_adma {
153 struct dma_device dma_dev;
154 struct device *dev;
155 void __iomem *base_addr;
156 struct clk *ahub_clk;
157 unsigned int nr_channels;
158 unsigned long rx_requests_reserved;
159 unsigned long tx_requests_reserved;
160
161 /* Used to store global command register state when suspending */
162 unsigned int global_cmd;
163
164 const struct tegra_adma_chip_data *cdata;
165
166 /* Last member of the structure */
167 struct tegra_adma_chan channels[];
168 };
169
tdma_write(struct tegra_adma * tdma,u32 reg,u32 val)170 static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val)
171 {
172 writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);
173 }
174
tdma_read(struct tegra_adma * tdma,u32 reg)175 static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg)
176 {
177 return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg);
178 }
179
tdma_ch_write(struct tegra_adma_chan * tdc,u32 reg,u32 val)180 static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
181 {
182 writel(val, tdc->chan_addr + reg);
183 }
184
tdma_ch_read(struct tegra_adma_chan * tdc,u32 reg)185 static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg)
186 {
187 return readl(tdc->chan_addr + reg);
188 }
189
to_tegra_adma_chan(struct dma_chan * dc)190 static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc)
191 {
192 return container_of(dc, struct tegra_adma_chan, vc.chan);
193 }
194
to_tegra_adma_desc(struct dma_async_tx_descriptor * td)195 static inline struct tegra_adma_desc *to_tegra_adma_desc(
196 struct dma_async_tx_descriptor *td)
197 {
198 return container_of(td, struct tegra_adma_desc, vd.tx);
199 }
200
tdc2dev(struct tegra_adma_chan * tdc)201 static inline struct device *tdc2dev(struct tegra_adma_chan *tdc)
202 {
203 return tdc->tdma->dev;
204 }
205
tegra_adma_desc_free(struct virt_dma_desc * vd)206 static void tegra_adma_desc_free(struct virt_dma_desc *vd)
207 {
208 kfree(container_of(vd, struct tegra_adma_desc, vd));
209 }
210
tegra_adma_slave_config(struct dma_chan * dc,struct dma_slave_config * sconfig)211 static int tegra_adma_slave_config(struct dma_chan *dc,
212 struct dma_slave_config *sconfig)
213 {
214 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
215
216 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig));
217
218 return 0;
219 }
220
tegra_adma_init(struct tegra_adma * tdma)221 static int tegra_adma_init(struct tegra_adma *tdma)
222 {
223 u32 status;
224 int ret;
225
226 /* Clear any interrupts */
227 tdma_write(tdma, tdma->cdata->global_int_clear, 0x1);
228
229 /* Assert soft reset */
230 tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
231
232 /* Wait for reset to clear */
233 ret = readx_poll_timeout(readl,
234 tdma->base_addr +
235 tdma->cdata->global_reg_offset +
236 ADMA_GLOBAL_SOFT_RESET,
237 status, status == 0, 20, 10000);
238 if (ret)
239 return ret;
240
241 /* Enable global ADMA registers */
242 tdma_write(tdma, ADMA_GLOBAL_CMD, 1);
243
244 return 0;
245 }
246
tegra_adma_request_alloc(struct tegra_adma_chan * tdc,enum dma_transfer_direction direction)247 static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc,
248 enum dma_transfer_direction direction)
249 {
250 struct tegra_adma *tdma = tdc->tdma;
251 unsigned int sreq_index = tdc->sreq_index;
252
253 if (tdc->sreq_reserved)
254 return tdc->sreq_dir == direction ? 0 : -EINVAL;
255
256 if (sreq_index > tdma->cdata->ch_req_max) {
257 dev_err(tdma->dev, "invalid DMA request\n");
258 return -EINVAL;
259 }
260
261 switch (direction) {
262 case DMA_MEM_TO_DEV:
263 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) {
264 dev_err(tdma->dev, "DMA request reserved\n");
265 return -EINVAL;
266 }
267 break;
268
269 case DMA_DEV_TO_MEM:
270 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) {
271 dev_err(tdma->dev, "DMA request reserved\n");
272 return -EINVAL;
273 }
274 break;
275
276 default:
277 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
278 dma_chan_name(&tdc->vc.chan));
279 return -EINVAL;
280 }
281
282 tdc->sreq_dir = direction;
283 tdc->sreq_reserved = true;
284
285 return 0;
286 }
287
tegra_adma_request_free(struct tegra_adma_chan * tdc)288 static void tegra_adma_request_free(struct tegra_adma_chan *tdc)
289 {
290 struct tegra_adma *tdma = tdc->tdma;
291
292 if (!tdc->sreq_reserved)
293 return;
294
295 switch (tdc->sreq_dir) {
296 case DMA_MEM_TO_DEV:
297 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved);
298 break;
299
300 case DMA_DEV_TO_MEM:
301 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved);
302 break;
303
304 default:
305 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
306 dma_chan_name(&tdc->vc.chan));
307 return;
308 }
309
310 tdc->sreq_reserved = false;
311 }
312
tegra_adma_irq_status(struct tegra_adma_chan * tdc)313 static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc)
314 {
315 u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS);
316
317 return status & ADMA_CH_INT_STATUS_XFER_DONE;
318 }
319
tegra_adma_irq_clear(struct tegra_adma_chan * tdc)320 static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc)
321 {
322 u32 status = tegra_adma_irq_status(tdc);
323
324 if (status)
325 tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status);
326
327 return status;
328 }
329
tegra_adma_stop(struct tegra_adma_chan * tdc)330 static void tegra_adma_stop(struct tegra_adma_chan *tdc)
331 {
332 unsigned int status;
333
334 /* Disable ADMA */
335 tdma_ch_write(tdc, ADMA_CH_CMD, 0);
336
337 /* Clear interrupt status */
338 tegra_adma_irq_clear(tdc);
339
340 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS,
341 status, !(status & ADMA_CH_STATUS_XFER_EN),
342 20, 10000)) {
343 dev_err(tdc2dev(tdc), "unable to stop DMA channel\n");
344 return;
345 }
346
347 kfree(tdc->desc);
348 tdc->desc = NULL;
349 }
350
tegra_adma_start(struct tegra_adma_chan * tdc)351 static void tegra_adma_start(struct tegra_adma_chan *tdc)
352 {
353 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc);
354 struct tegra_adma_chan_regs *ch_regs;
355 struct tegra_adma_desc *desc;
356
357 if (!vd)
358 return;
359
360 list_del(&vd->node);
361
362 desc = to_tegra_adma_desc(&vd->tx);
363
364 if (!desc) {
365 dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n");
366 return;
367 }
368
369 ch_regs = &desc->ch_regs;
370
371 tdc->tx_buf_pos = 0;
372 tdc->tx_buf_count = 0;
373 tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc);
374 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
375 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr);
376 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr);
377 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
378 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
379
380 /* Start ADMA */
381 tdma_ch_write(tdc, ADMA_CH_CMD, 1);
382
383 tdc->desc = desc;
384 }
385
tegra_adma_get_residue(struct tegra_adma_chan * tdc)386 static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc)
387 {
388 struct tegra_adma_desc *desc = tdc->desc;
389 unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1;
390 unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS);
391 unsigned int periods_remaining;
392
393 /*
394 * Handle wrap around of buffer count register
395 */
396 if (pos < tdc->tx_buf_pos)
397 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos);
398 else
399 tdc->tx_buf_count += pos - tdc->tx_buf_pos;
400
401 periods_remaining = tdc->tx_buf_count % desc->num_periods;
402 tdc->tx_buf_pos = pos;
403
404 return desc->buf_len - (periods_remaining * desc->period_len);
405 }
406
tegra_adma_isr(int irq,void * dev_id)407 static irqreturn_t tegra_adma_isr(int irq, void *dev_id)
408 {
409 struct tegra_adma_chan *tdc = dev_id;
410 unsigned long status;
411 unsigned long flags;
412
413 spin_lock_irqsave(&tdc->vc.lock, flags);
414
415 status = tegra_adma_irq_clear(tdc);
416 if (status == 0 || !tdc->desc) {
417 spin_unlock_irqrestore(&tdc->vc.lock, flags);
418 return IRQ_NONE;
419 }
420
421 vchan_cyclic_callback(&tdc->desc->vd);
422
423 spin_unlock_irqrestore(&tdc->vc.lock, flags);
424
425 return IRQ_HANDLED;
426 }
427
tegra_adma_issue_pending(struct dma_chan * dc)428 static void tegra_adma_issue_pending(struct dma_chan *dc)
429 {
430 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
431 unsigned long flags;
432
433 spin_lock_irqsave(&tdc->vc.lock, flags);
434
435 if (vchan_issue_pending(&tdc->vc)) {
436 if (!tdc->desc)
437 tegra_adma_start(tdc);
438 }
439
440 spin_unlock_irqrestore(&tdc->vc.lock, flags);
441 }
442
tegra_adma_is_paused(struct tegra_adma_chan * tdc)443 static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc)
444 {
445 u32 csts;
446
447 csts = tdma_ch_read(tdc, ADMA_CH_STATUS);
448 csts &= ADMA_CH_STATUS_XFER_PAUSED;
449
450 return csts ? true : false;
451 }
452
tegra_adma_pause(struct dma_chan * dc)453 static int tegra_adma_pause(struct dma_chan *dc)
454 {
455 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
456 struct tegra_adma_desc *desc = tdc->desc;
457 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
458 int dcnt = 10;
459
460 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
461 ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
462 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
463
464 while (dcnt-- && !tegra_adma_is_paused(tdc))
465 udelay(TEGRA_ADMA_BURST_COMPLETE_TIME);
466
467 if (dcnt < 0) {
468 dev_err(tdc2dev(tdc), "unable to pause DMA channel\n");
469 return -EBUSY;
470 }
471
472 return 0;
473 }
474
tegra_adma_resume(struct dma_chan * dc)475 static int tegra_adma_resume(struct dma_chan *dc)
476 {
477 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
478 struct tegra_adma_desc *desc = tdc->desc;
479 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
480
481 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
482 ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
483 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
484
485 return 0;
486 }
487
tegra_adma_terminate_all(struct dma_chan * dc)488 static int tegra_adma_terminate_all(struct dma_chan *dc)
489 {
490 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
491 unsigned long flags;
492 LIST_HEAD(head);
493
494 spin_lock_irqsave(&tdc->vc.lock, flags);
495
496 if (tdc->desc)
497 tegra_adma_stop(tdc);
498
499 tegra_adma_request_free(tdc);
500 vchan_get_all_descriptors(&tdc->vc, &head);
501 spin_unlock_irqrestore(&tdc->vc.lock, flags);
502 vchan_dma_desc_free_list(&tdc->vc, &head);
503
504 return 0;
505 }
506
tegra_adma_tx_status(struct dma_chan * dc,dma_cookie_t cookie,struct dma_tx_state * txstate)507 static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,
508 dma_cookie_t cookie,
509 struct dma_tx_state *txstate)
510 {
511 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
512 struct tegra_adma_desc *desc;
513 struct virt_dma_desc *vd;
514 enum dma_status ret;
515 unsigned long flags;
516 unsigned int residual;
517
518 ret = dma_cookie_status(dc, cookie, txstate);
519 if (ret == DMA_COMPLETE || !txstate)
520 return ret;
521
522 spin_lock_irqsave(&tdc->vc.lock, flags);
523
524 vd = vchan_find_desc(&tdc->vc, cookie);
525 if (vd) {
526 desc = to_tegra_adma_desc(&vd->tx);
527 residual = desc->ch_regs.tc;
528 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) {
529 residual = tegra_adma_get_residue(tdc);
530 } else {
531 residual = 0;
532 }
533
534 spin_unlock_irqrestore(&tdc->vc.lock, flags);
535
536 dma_set_residue(txstate, residual);
537
538 return ret;
539 }
540
tegra210_adma_get_burst_config(unsigned int burst_size)541 static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size)
542 {
543 if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
544 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
545
546 return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
547 }
548
tegra186_adma_get_burst_config(unsigned int burst_size)549 static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size)
550 {
551 if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
552 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
553
554 return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
555 }
556
tegra_adma_set_xfer_params(struct tegra_adma_chan * tdc,struct tegra_adma_desc * desc,dma_addr_t buf_addr,enum dma_transfer_direction direction)557 static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
558 struct tegra_adma_desc *desc,
559 dma_addr_t buf_addr,
560 enum dma_transfer_direction direction)
561 {
562 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
563 const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;
564 unsigned int burst_size, adma_dir;
565
566 if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS)
567 return -EINVAL;
568
569 switch (direction) {
570 case DMA_MEM_TO_DEV:
571 adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB;
572 burst_size = tdc->sconfig.dst_maxburst;
573 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1);
574 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
575 cdata->ch_req_mask,
576 cdata->ch_req_tx_shift);
577 ch_regs->src_addr = buf_addr;
578 break;
579
580 case DMA_DEV_TO_MEM:
581 adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM;
582 burst_size = tdc->sconfig.src_maxburst;
583 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1);
584 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
585 cdata->ch_req_mask,
586 cdata->ch_req_rx_shift);
587 ch_regs->trg_addr = buf_addr;
588 break;
589
590 default:
591 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
592 return -EINVAL;
593 }
594
595 ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) |
596 ADMA_CH_CTRL_MODE_CONTINUOUS |
597 ADMA_CH_CTRL_FLOWCTRL_EN;
598 ch_regs->config |= cdata->adma_get_burst_config(burst_size);
599 ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
600 if (cdata->has_outstanding_reqs)
601 ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8);
602 ch_regs->fifo_ctrl = cdata->ch_fifo_ctrl;
603 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
604
605 return tegra_adma_request_alloc(tdc, direction);
606 }
607
tegra_adma_prep_dma_cyclic(struct dma_chan * dc,dma_addr_t buf_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)608 static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic(
609 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
610 size_t period_len, enum dma_transfer_direction direction,
611 unsigned long flags)
612 {
613 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
614 struct tegra_adma_desc *desc = NULL;
615
616 if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) {
617 dev_err(tdc2dev(tdc), "invalid buffer/period len\n");
618 return NULL;
619 }
620
621 if (buf_len % period_len) {
622 dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n");
623 return NULL;
624 }
625
626 if (!IS_ALIGNED(buf_addr, 4)) {
627 dev_err(tdc2dev(tdc), "invalid buffer alignment\n");
628 return NULL;
629 }
630
631 desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
632 if (!desc)
633 return NULL;
634
635 desc->buf_len = buf_len;
636 desc->period_len = period_len;
637 desc->num_periods = buf_len / period_len;
638
639 if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) {
640 kfree(desc);
641 return NULL;
642 }
643
644 return vchan_tx_prep(&tdc->vc, &desc->vd, flags);
645 }
646
tegra_adma_alloc_chan_resources(struct dma_chan * dc)647 static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)
648 {
649 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
650 int ret;
651
652 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);
653 if (ret) {
654 dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n",
655 dma_chan_name(dc));
656 return ret;
657 }
658
659 ret = pm_runtime_get_sync(tdc2dev(tdc));
660 if (ret < 0) {
661 pm_runtime_put_noidle(tdc2dev(tdc));
662 free_irq(tdc->irq, tdc);
663 return ret;
664 }
665
666 dma_cookie_init(&tdc->vc.chan);
667
668 return 0;
669 }
670
tegra_adma_free_chan_resources(struct dma_chan * dc)671 static void tegra_adma_free_chan_resources(struct dma_chan *dc)
672 {
673 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
674
675 tegra_adma_terminate_all(dc);
676 vchan_free_chan_resources(&tdc->vc);
677 tasklet_kill(&tdc->vc.task);
678 free_irq(tdc->irq, tdc);
679 pm_runtime_put(tdc2dev(tdc));
680
681 tdc->sreq_index = 0;
682 tdc->sreq_dir = DMA_TRANS_NONE;
683 }
684
tegra_dma_of_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)685 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
686 struct of_dma *ofdma)
687 {
688 struct tegra_adma *tdma = ofdma->of_dma_data;
689 struct tegra_adma_chan *tdc;
690 struct dma_chan *chan;
691 unsigned int sreq_index;
692
693 if (dma_spec->args_count != 1)
694 return NULL;
695
696 sreq_index = dma_spec->args[0];
697
698 if (sreq_index == 0) {
699 dev_err(tdma->dev, "DMA request must not be 0\n");
700 return NULL;
701 }
702
703 chan = dma_get_any_slave_channel(&tdma->dma_dev);
704 if (!chan)
705 return NULL;
706
707 tdc = to_tegra_adma_chan(chan);
708 tdc->sreq_index = sreq_index;
709
710 return chan;
711 }
712
tegra_adma_runtime_suspend(struct device * dev)713 static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev)
714 {
715 struct tegra_adma *tdma = dev_get_drvdata(dev);
716 struct tegra_adma_chan_regs *ch_reg;
717 struct tegra_adma_chan *tdc;
718 int i;
719
720 tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD);
721 if (!tdma->global_cmd)
722 goto clk_disable;
723
724 for (i = 0; i < tdma->nr_channels; i++) {
725 tdc = &tdma->channels[i];
726 ch_reg = &tdc->ch_regs;
727 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD);
728 /* skip if channel is not active */
729 if (!ch_reg->cmd)
730 continue;
731 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC);
732 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR);
733 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR);
734 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
735 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
736 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG);
737 }
738
739 clk_disable:
740 clk_disable_unprepare(tdma->ahub_clk);
741
742 return 0;
743 }
744
tegra_adma_runtime_resume(struct device * dev)745 static int __maybe_unused tegra_adma_runtime_resume(struct device *dev)
746 {
747 struct tegra_adma *tdma = dev_get_drvdata(dev);
748 struct tegra_adma_chan_regs *ch_reg;
749 struct tegra_adma_chan *tdc;
750 int ret, i;
751
752 ret = clk_prepare_enable(tdma->ahub_clk);
753 if (ret) {
754 dev_err(dev, "ahub clk_enable failed: %d\n", ret);
755 return ret;
756 }
757 tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd);
758
759 if (!tdma->global_cmd)
760 return 0;
761
762 for (i = 0; i < tdma->nr_channels; i++) {
763 tdc = &tdma->channels[i];
764 ch_reg = &tdc->ch_regs;
765 /* skip if channel was not active earlier */
766 if (!ch_reg->cmd)
767 continue;
768 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc);
769 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr);
770 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr);
771 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
772 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
773 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
774 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd);
775 }
776
777 return 0;
778 }
779
780 static const struct tegra_adma_chip_data tegra210_chip_data = {
781 .adma_get_burst_config = tegra210_adma_get_burst_config,
782 .global_reg_offset = 0xc00,
783 .global_int_clear = 0x20,
784 .ch_req_tx_shift = 28,
785 .ch_req_rx_shift = 24,
786 .ch_base_offset = 0,
787 .has_outstanding_reqs = false,
788 .ch_fifo_ctrl = TEGRA210_FIFO_CTRL_DEFAULT,
789 .ch_req_mask = 0xf,
790 .ch_req_max = 10,
791 .ch_reg_size = 0x80,
792 .nr_channels = 22,
793 };
794
795 static const struct tegra_adma_chip_data tegra186_chip_data = {
796 .adma_get_burst_config = tegra186_adma_get_burst_config,
797 .global_reg_offset = 0,
798 .global_int_clear = 0x402c,
799 .ch_req_tx_shift = 27,
800 .ch_req_rx_shift = 22,
801 .ch_base_offset = 0x10000,
802 .has_outstanding_reqs = true,
803 .ch_fifo_ctrl = TEGRA186_FIFO_CTRL_DEFAULT,
804 .ch_req_mask = 0x1f,
805 .ch_req_max = 20,
806 .ch_reg_size = 0x100,
807 .nr_channels = 32,
808 };
809
810 static const struct of_device_id tegra_adma_of_match[] = {
811 { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
812 { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
813 { },
814 };
815 MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
816
tegra_adma_probe(struct platform_device * pdev)817 static int tegra_adma_probe(struct platform_device *pdev)
818 {
819 const struct tegra_adma_chip_data *cdata;
820 struct tegra_adma *tdma;
821 struct resource *res;
822 int ret, i;
823
824 cdata = of_device_get_match_data(&pdev->dev);
825 if (!cdata) {
826 dev_err(&pdev->dev, "device match data not found\n");
827 return -ENODEV;
828 }
829
830 tdma = devm_kzalloc(&pdev->dev,
831 struct_size(tdma, channels, cdata->nr_channels),
832 GFP_KERNEL);
833 if (!tdma)
834 return -ENOMEM;
835
836 tdma->dev = &pdev->dev;
837 tdma->cdata = cdata;
838 tdma->nr_channels = cdata->nr_channels;
839 platform_set_drvdata(pdev, tdma);
840
841 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
842 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
843 if (IS_ERR(tdma->base_addr))
844 return PTR_ERR(tdma->base_addr);
845
846 tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio");
847 if (IS_ERR(tdma->ahub_clk)) {
848 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n");
849 return PTR_ERR(tdma->ahub_clk);
850 }
851
852 INIT_LIST_HEAD(&tdma->dma_dev.channels);
853 for (i = 0; i < tdma->nr_channels; i++) {
854 struct tegra_adma_chan *tdc = &tdma->channels[i];
855
856 tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset
857 + (cdata->ch_reg_size * i);
858
859 tdc->irq = of_irq_get(pdev->dev.of_node, i);
860 if (tdc->irq <= 0) {
861 ret = tdc->irq ?: -ENXIO;
862 goto irq_dispose;
863 }
864
865 vchan_init(&tdc->vc, &tdma->dma_dev);
866 tdc->vc.desc_free = tegra_adma_desc_free;
867 tdc->tdma = tdma;
868 }
869
870 pm_runtime_enable(&pdev->dev);
871
872 ret = pm_runtime_get_sync(&pdev->dev);
873 if (ret < 0) {
874 pm_runtime_put_noidle(&pdev->dev);
875 goto rpm_disable;
876 }
877
878 ret = tegra_adma_init(tdma);
879 if (ret)
880 goto rpm_put;
881
882 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
883 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
884 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
885
886 tdma->dma_dev.dev = &pdev->dev;
887 tdma->dma_dev.device_alloc_chan_resources =
888 tegra_adma_alloc_chan_resources;
889 tdma->dma_dev.device_free_chan_resources =
890 tegra_adma_free_chan_resources;
891 tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending;
892 tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic;
893 tdma->dma_dev.device_config = tegra_adma_slave_config;
894 tdma->dma_dev.device_tx_status = tegra_adma_tx_status;
895 tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all;
896 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
897 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
898 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
899 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
900 tdma->dma_dev.device_pause = tegra_adma_pause;
901 tdma->dma_dev.device_resume = tegra_adma_resume;
902
903 ret = dma_async_device_register(&tdma->dma_dev);
904 if (ret < 0) {
905 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret);
906 goto rpm_put;
907 }
908
909 ret = of_dma_controller_register(pdev->dev.of_node,
910 tegra_dma_of_xlate, tdma);
911 if (ret < 0) {
912 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret);
913 goto dma_remove;
914 }
915
916 pm_runtime_put(&pdev->dev);
917
918 dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n",
919 tdma->nr_channels);
920
921 return 0;
922
923 dma_remove:
924 dma_async_device_unregister(&tdma->dma_dev);
925 rpm_put:
926 pm_runtime_put_sync(&pdev->dev);
927 rpm_disable:
928 pm_runtime_disable(&pdev->dev);
929 irq_dispose:
930 while (--i >= 0)
931 irq_dispose_mapping(tdma->channels[i].irq);
932
933 return ret;
934 }
935
tegra_adma_remove(struct platform_device * pdev)936 static int tegra_adma_remove(struct platform_device *pdev)
937 {
938 struct tegra_adma *tdma = platform_get_drvdata(pdev);
939 int i;
940
941 of_dma_controller_free(pdev->dev.of_node);
942 dma_async_device_unregister(&tdma->dma_dev);
943
944 for (i = 0; i < tdma->nr_channels; ++i)
945 irq_dispose_mapping(tdma->channels[i].irq);
946
947 pm_runtime_put_sync(&pdev->dev);
948 pm_runtime_disable(&pdev->dev);
949
950 return 0;
951 }
952
953 static const struct dev_pm_ops tegra_adma_dev_pm_ops = {
954 SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend,
955 tegra_adma_runtime_resume, NULL)
956 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
957 pm_runtime_force_resume)
958 };
959
960 static struct platform_driver tegra_admac_driver = {
961 .driver = {
962 .name = "tegra-adma",
963 .pm = &tegra_adma_dev_pm_ops,
964 .of_match_table = tegra_adma_of_match,
965 },
966 .probe = tegra_adma_probe,
967 .remove = tegra_adma_remove,
968 };
969
970 module_platform_driver(tegra_admac_driver);
971
972 MODULE_ALIAS("platform:tegra210-adma");
973 MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver");
974 MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>");
975 MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>");
976 MODULE_LICENSE("GPL v2");
977
