1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019, Intel Corporation
4 */
5 #include <linux/slab.h>
6 #include <linux/clk-provider.h>
7 #include <linux/of_device.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10
11 #include <dt-bindings/clock/agilex-clock.h>
12
13 #include "stratix10-clk.h"
14
15 static const struct clk_parent_data pll_mux[] = {
16 { .fw_name = "osc1",
17 .name = "osc1", },
18 { .fw_name = "cb-intosc-hs-div2-clk",
19 .name = "cb-intosc-hs-div2-clk", },
20 { .fw_name = "f2s-free-clk",
21 .name = "f2s-free-clk", },
22 };
23
24 static const struct clk_parent_data boot_mux[] = {
25 { .fw_name = "osc1",
26 .name = "osc1", },
27 { .fw_name = "cb-intosc-hs-div2-clk",
28 .name = "cb-intosc-hs-div2-clk", },
29 };
30
31 static const struct clk_parent_data mpu_free_mux[] = {
32 { .fw_name = "main_pll_c0",
33 .name = "main_pll_c0", },
34 { .fw_name = "peri_pll_c0",
35 .name = "peri_pll_c0", },
36 { .fw_name = "osc1",
37 .name = "osc1", },
38 { .fw_name = "cb-intosc-hs-div2-clk",
39 .name = "cb-intosc-hs-div2-clk", },
40 { .fw_name = "f2s-free-clk",
41 .name = "f2s-free-clk", },
42 };
43
44 static const struct clk_parent_data noc_free_mux[] = {
45 { .fw_name = "main_pll_c1",
46 .name = "main_pll_c1", },
47 { .fw_name = "peri_pll_c1",
48 .name = "peri_pll_c1", },
49 { .fw_name = "osc1",
50 .name = "osc1", },
51 { .fw_name = "cb-intosc-hs-div2-clk",
52 .name = "cb-intosc-hs-div2-clk", },
53 { .fw_name = "f2s-free-clk",
54 .name = "f2s-free-clk", },
55 };
56
57 static const struct clk_parent_data emaca_free_mux[] = {
58 { .fw_name = "main_pll_c2",
59 .name = "main_pll_c2", },
60 { .fw_name = "peri_pll_c2",
61 .name = "peri_pll_c2", },
62 { .fw_name = "osc1",
63 .name = "osc1", },
64 { .fw_name = "cb-intosc-hs-div2-clk",
65 .name = "cb-intosc-hs-div2-clk", },
66 { .fw_name = "f2s-free-clk",
67 .name = "f2s-free-clk", },
68 };
69
70 static const struct clk_parent_data emacb_free_mux[] = {
71 { .fw_name = "main_pll_c3",
72 .name = "main_pll_c3", },
73 { .fw_name = "peri_pll_c3",
74 .name = "peri_pll_c3", },
75 { .fw_name = "osc1",
76 .name = "osc1", },
77 { .fw_name = "cb-intosc-hs-div2-clk",
78 .name = "cb-intosc-hs-div2-clk", },
79 { .fw_name = "f2s-free-clk",
80 .name = "f2s-free-clk", },
81 };
82
83 static const struct clk_parent_data emac_ptp_free_mux[] = {
84 { .fw_name = "main_pll_c3",
85 .name = "main_pll_c3", },
86 { .fw_name = "peri_pll_c3",
87 .name = "peri_pll_c3", },
88 { .fw_name = "osc1",
89 .name = "osc1", },
90 { .fw_name = "cb-intosc-hs-div2-clk",
91 .name = "cb-intosc-hs-div2-clk", },
92 { .fw_name = "f2s-free-clk",
93 .name = "f2s-free-clk", },
94 };
95
96 static const struct clk_parent_data gpio_db_free_mux[] = {
97 { .fw_name = "main_pll_c3",
98 .name = "main_pll_c3", },
99 { .fw_name = "peri_pll_c3",
100 .name = "peri_pll_c3", },
101 { .fw_name = "osc1",
102 .name = "osc1", },
103 { .fw_name = "cb-intosc-hs-div2-clk",
104 .name = "cb-intosc-hs-div2-clk", },
105 { .fw_name = "f2s-free-clk",
106 .name = "f2s-free-clk", },
107 };
108
109 static const struct clk_parent_data psi_ref_free_mux[] = {
110 { .fw_name = "main_pll_c3",
111 .name = "main_pll_c3", },
112 { .fw_name = "peri_pll_c3",
113 .name = "peri_pll_c3", },
114 { .fw_name = "osc1",
115 .name = "osc1", },
116 { .fw_name = "cb-intosc-hs-div2-clk",
117 .name = "cb-intosc-hs-div2-clk", },
118 { .fw_name = "f2s-free-clk",
119 .name = "f2s-free-clk", },
120 };
121
122 static const struct clk_parent_data sdmmc_free_mux[] = {
123 { .fw_name = "main_pll_c3",
124 .name = "main_pll_c3", },
125 { .fw_name = "peri_pll_c3",
126 .name = "peri_pll_c3", },
127 { .fw_name = "osc1",
128 .name = "osc1", },
129 { .fw_name = "cb-intosc-hs-div2-clk",
130 .name = "cb-intosc-hs-div2-clk", },
131 { .fw_name = "f2s-free-clk",
132 .name = "f2s-free-clk", },
133 };
134
135 static const struct clk_parent_data s2f_usr0_free_mux[] = {
136 { .fw_name = "main_pll_c2",
137 .name = "main_pll_c2", },
138 { .fw_name = "peri_pll_c2",
139 .name = "peri_pll_c2", },
140 { .fw_name = "osc1",
141 .name = "osc1", },
142 { .fw_name = "cb-intosc-hs-div2-clk",
143 .name = "cb-intosc-hs-div2-clk", },
144 { .fw_name = "f2s-free-clk",
145 .name = "f2s-free-clk", },
146 };
147
148 static const struct clk_parent_data s2f_usr1_free_mux[] = {
149 { .fw_name = "main_pll_c2",
150 .name = "main_pll_c2", },
151 { .fw_name = "peri_pll_c2",
152 .name = "peri_pll_c2", },
153 { .fw_name = "osc1",
154 .name = "osc1", },
155 { .fw_name = "cb-intosc-hs-div2-clk",
156 .name = "cb-intosc-hs-div2-clk", },
157 { .fw_name = "f2s-free-clk",
158 .name = "f2s-free-clk", },
159 };
160
161 static const struct clk_parent_data mpu_mux[] = {
162 { .fw_name = "mpu_free_clk",
163 .name = "mpu_free_clk", },
164 { .fw_name = "boot_clk",
165 .name = "boot_clk", },
166 };
167
168 static const struct clk_parent_data s2f_usr0_mux[] = {
169 { .fw_name = "f2s-free-clk",
170 .name = "f2s-free-clk", },
171 { .fw_name = "boot_clk",
172 .name = "boot_clk", },
173 };
174
175 static const struct clk_parent_data emac_mux[] = {
176 { .fw_name = "emaca_free_clk",
177 .name = "emaca_free_clk", },
178 { .fw_name = "emacb_free_clk",
179 .name = "emacb_free_clk", },
180 };
181
182 static const struct clk_parent_data noc_mux[] = {
183 { .fw_name = "noc_free_clk",
184 .name = "noc_free_clk", },
185 { .fw_name = "boot_clk",
186 .name = "boot_clk", },
187 };
188
189 /* clocks in AO (always on) controller */
190 static const struct stratix10_pll_clock agilex_pll_clks[] = {
191 { AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
192 0x0},
193 { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
194 0, 0x48},
195 { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
196 0, 0x9c},
197 };
198
199 static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
200 { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
201 { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
202 { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x64},
203 { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x68},
204 { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xAC},
205 { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xB0},
206 { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xB8},
207 { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC},
208 };
209
210 static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
211 { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
212 0, 0x3C, 0, 0, 0},
213 { AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
214 0, 0x40, 0, 0, 1},
215 { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
216 0, 4, 0, 0},
217 { AGILEX_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
218 0, 0, 0, 0x30, 1},
219 { AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
220 0, 0xD4, 0, 0x88, 0},
221 { AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
222 0, 0xD8, 0, 0x88, 1},
223 { AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
224 ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2},
225 { AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
226 ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
227 { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
228 ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0x88, 4},
229 { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
230 ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0},
231 { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
232 ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
233 { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
234 ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
235 };
236
237 static const struct stratix10_gate_clock agilex_gate_clks[] = {
238 { AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24,
239 0, 0, 0, 0, 0x30, 0, 0},
240 { AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
241 0, 0, 0, 0, 0, 0, 4},
242 { AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,
243 0, 0, 0, 0, 0, 0, 2},
244 { AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24,
245 1, 0x44, 0, 2, 0, 0, 0},
246 { AGILEX_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x24,
247 2, 0x44, 8, 2, 0, 0, 0},
248 /*
249 * The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them
250 * being the SP timers, thus cannot get gated.
251 */
252 { AGILEX_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x24,
253 3, 0x44, 16, 2, 0, 0, 0},
254 { AGILEX_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x24,
255 4, 0x44, 24, 2, 0, 0, 0},
256 { AGILEX_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x24,
257 4, 0x44, 26, 2, 0, 0, 0},
258 { AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24,
259 4, 0x44, 28, 1, 0, 0, 0},
260 { AGILEX_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x24,
261 5, 0, 0, 0, 0, 0, 0},
262 { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24,
263 6, 0, 0, 0, 0, 0, 0},
264 { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
265 0, 0, 0, 0, 0x94, 26, 0},
266 { AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
267 1, 0, 0, 0, 0x94, 27, 0},
268 { AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
269 2, 0, 0, 0, 0x94, 28, 0},
270 { AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0x7C,
271 3, 0, 0, 0, 0, 0, 0},
272 { AGILEX_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0x7C,
273 4, 0x98, 0, 16, 0, 0, 0},
274 { AGILEX_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0x7C,
275 5, 0, 0, 0, 0, 0, 4},
276 { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0x7C,
277 6, 0, 0, 0, 0, 0, 0},
278 { AGILEX_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0x7C,
279 7, 0, 0, 0, 0, 0, 0},
280 { AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
281 8, 0, 0, 0, 0, 0, 0},
282 { AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
283 9, 0, 0, 0, 0, 0, 0},
284 { AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
285 10, 0, 0, 0, 0, 0, 0},
286 { AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
287 10, 0, 0, 0, 0, 0, 4},
288 { AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
289 10, 0, 0, 0, 0, 0, 4},
290 };
291
agilex_clk_register_c_perip(const struct stratix10_perip_c_clock * clks,int nums,struct stratix10_clock_data * data)292 static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
293 int nums, struct stratix10_clock_data *data)
294 {
295 struct clk *clk;
296 void __iomem *base = data->base;
297 int i;
298
299 for (i = 0; i < nums; i++) {
300 clk = s10_register_periph(&clks[i], base);
301 if (IS_ERR(clk)) {
302 pr_err("%s: failed to register clock %s\n",
303 __func__, clks[i].name);
304 continue;
305 }
306 data->clk_data.clks[clks[i].id] = clk;
307 }
308 return 0;
309 }
310
agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock * clks,int nums,struct stratix10_clock_data * data)311 static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
312 int nums, struct stratix10_clock_data *data)
313 {
314 struct clk *clk;
315 void __iomem *base = data->base;
316 int i;
317
318 for (i = 0; i < nums; i++) {
319 clk = s10_register_cnt_periph(&clks[i], base);
320 if (IS_ERR(clk)) {
321 pr_err("%s: failed to register clock %s\n",
322 __func__, clks[i].name);
323 continue;
324 }
325 data->clk_data.clks[clks[i].id] = clk;
326 }
327
328 return 0;
329 }
330
agilex_clk_register_gate(const struct stratix10_gate_clock * clks,int nums,struct stratix10_clock_data * data)331 static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks, int nums, struct stratix10_clock_data *data)
332 {
333 struct clk *clk;
334 void __iomem *base = data->base;
335 int i;
336
337 for (i = 0; i < nums; i++) {
338 clk = s10_register_gate(&clks[i], base);
339 if (IS_ERR(clk)) {
340 pr_err("%s: failed to register clock %s\n",
341 __func__, clks[i].name);
342 continue;
343 }
344 data->clk_data.clks[clks[i].id] = clk;
345 }
346
347 return 0;
348 }
349
agilex_clk_register_pll(const struct stratix10_pll_clock * clks,int nums,struct stratix10_clock_data * data)350 static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
351 int nums, struct stratix10_clock_data *data)
352 {
353 struct clk *clk;
354 void __iomem *base = data->base;
355 int i;
356
357 for (i = 0; i < nums; i++) {
358 clk = agilex_register_pll(&clks[i], base);
359 if (IS_ERR(clk)) {
360 pr_err("%s: failed to register clock %s\n",
361 __func__, clks[i].name);
362 continue;
363 }
364 data->clk_data.clks[clks[i].id] = clk;
365 }
366
367 return 0;
368 }
369
__socfpga_agilex_clk_init(struct platform_device * pdev,int nr_clks)370 static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev,
371 int nr_clks)
372 {
373 struct device_node *np = pdev->dev.of_node;
374 struct device *dev = &pdev->dev;
375 struct stratix10_clock_data *clk_data;
376 struct clk **clk_table;
377 struct resource *res;
378 void __iomem *base;
379 int ret;
380
381 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
382 base = devm_ioremap_resource(dev, res);
383 if (IS_ERR(base))
384 return ERR_CAST(base);
385
386 clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
387 if (!clk_data)
388 return ERR_PTR(-ENOMEM);
389
390 clk_data->base = base;
391 clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
392 if (!clk_table)
393 return ERR_PTR(-ENOMEM);
394
395 clk_data->clk_data.clks = clk_table;
396 clk_data->clk_data.clk_num = nr_clks;
397 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
398 if (ret)
399 return ERR_PTR(ret);
400
401 return clk_data;
402 }
403
agilex_clkmgr_probe(struct platform_device * pdev)404 static int agilex_clkmgr_probe(struct platform_device *pdev)
405 {
406 struct stratix10_clock_data *clk_data;
407
408 clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
409 if (IS_ERR(clk_data))
410 return PTR_ERR(clk_data);
411
412 agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
413
414 agilex_clk_register_c_perip(agilex_main_perip_c_clks,
415 ARRAY_SIZE(agilex_main_perip_c_clks), clk_data);
416
417 agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
418 ARRAY_SIZE(agilex_main_perip_cnt_clks),
419 clk_data);
420
421 agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
422 clk_data);
423 return 0;
424 }
425
426 static const struct of_device_id agilex_clkmgr_match_table[] = {
427 { .compatible = "intel,agilex-clkmgr",
428 .data = agilex_clkmgr_probe },
429 { }
430 };
431
432 static struct platform_driver agilex_clkmgr_driver = {
433 .probe = agilex_clkmgr_probe,
434 .driver = {
435 .name = "agilex-clkmgr",
436 .suppress_bind_attrs = true,
437 .of_match_table = agilex_clkmgr_match_table,
438 },
439 };
440
agilex_clk_init(void)441 static int __init agilex_clk_init(void)
442 {
443 return platform_driver_register(&agilex_clkmgr_driver);
444 }
445 core_initcall(agilex_clk_init);
446
