1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4 * Author: Olivier Bideau <olivier.bideau@st.com> for STMicroelectronics.
5 * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/io.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17
18 #include <dt-bindings/clock/stm32mp1-clks.h>
19
20 static DEFINE_SPINLOCK(rlock);
21
22 #define RCC_OCENSETR 0x0C
23 #define RCC_HSICFGR 0x18
24 #define RCC_RDLSICR 0x144
25 #define RCC_PLL1CR 0x80
26 #define RCC_PLL1CFGR1 0x84
27 #define RCC_PLL1CFGR2 0x88
28 #define RCC_PLL2CR 0x94
29 #define RCC_PLL2CFGR1 0x98
30 #define RCC_PLL2CFGR2 0x9C
31 #define RCC_PLL3CR 0x880
32 #define RCC_PLL3CFGR1 0x884
33 #define RCC_PLL3CFGR2 0x888
34 #define RCC_PLL4CR 0x894
35 #define RCC_PLL4CFGR1 0x898
36 #define RCC_PLL4CFGR2 0x89C
37 #define RCC_APB1ENSETR 0xA00
38 #define RCC_APB2ENSETR 0xA08
39 #define RCC_APB3ENSETR 0xA10
40 #define RCC_APB4ENSETR 0x200
41 #define RCC_APB5ENSETR 0x208
42 #define RCC_AHB2ENSETR 0xA18
43 #define RCC_AHB3ENSETR 0xA20
44 #define RCC_AHB4ENSETR 0xA28
45 #define RCC_AHB5ENSETR 0x210
46 #define RCC_AHB6ENSETR 0x218
47 #define RCC_AHB6LPENSETR 0x318
48 #define RCC_RCK12SELR 0x28
49 #define RCC_RCK3SELR 0x820
50 #define RCC_RCK4SELR 0x824
51 #define RCC_MPCKSELR 0x20
52 #define RCC_ASSCKSELR 0x24
53 #define RCC_MSSCKSELR 0x48
54 #define RCC_SPI6CKSELR 0xC4
55 #define RCC_SDMMC12CKSELR 0x8F4
56 #define RCC_SDMMC3CKSELR 0x8F8
57 #define RCC_FMCCKSELR 0x904
58 #define RCC_I2C46CKSELR 0xC0
59 #define RCC_I2C12CKSELR 0x8C0
60 #define RCC_I2C35CKSELR 0x8C4
61 #define RCC_UART1CKSELR 0xC8
62 #define RCC_QSPICKSELR 0x900
63 #define RCC_ETHCKSELR 0x8FC
64 #define RCC_RNG1CKSELR 0xCC
65 #define RCC_RNG2CKSELR 0x920
66 #define RCC_GPUCKSELR 0x938
67 #define RCC_USBCKSELR 0x91C
68 #define RCC_STGENCKSELR 0xD4
69 #define RCC_SPDIFCKSELR 0x914
70 #define RCC_SPI2S1CKSELR 0x8D8
71 #define RCC_SPI2S23CKSELR 0x8DC
72 #define RCC_SPI2S45CKSELR 0x8E0
73 #define RCC_CECCKSELR 0x918
74 #define RCC_LPTIM1CKSELR 0x934
75 #define RCC_LPTIM23CKSELR 0x930
76 #define RCC_LPTIM45CKSELR 0x92C
77 #define RCC_UART24CKSELR 0x8E8
78 #define RCC_UART35CKSELR 0x8EC
79 #define RCC_UART6CKSELR 0x8E4
80 #define RCC_UART78CKSELR 0x8F0
81 #define RCC_FDCANCKSELR 0x90C
82 #define RCC_SAI1CKSELR 0x8C8
83 #define RCC_SAI2CKSELR 0x8CC
84 #define RCC_SAI3CKSELR 0x8D0
85 #define RCC_SAI4CKSELR 0x8D4
86 #define RCC_ADCCKSELR 0x928
87 #define RCC_MPCKDIVR 0x2C
88 #define RCC_DSICKSELR 0x924
89 #define RCC_CPERCKSELR 0xD0
90 #define RCC_MCO1CFGR 0x800
91 #define RCC_MCO2CFGR 0x804
92 #define RCC_BDCR 0x140
93 #define RCC_AXIDIVR 0x30
94 #define RCC_MCUDIVR 0x830
95 #define RCC_APB1DIVR 0x834
96 #define RCC_APB2DIVR 0x838
97 #define RCC_APB3DIVR 0x83C
98 #define RCC_APB4DIVR 0x3C
99 #define RCC_APB5DIVR 0x40
100 #define RCC_TIMG1PRER 0x828
101 #define RCC_TIMG2PRER 0x82C
102 #define RCC_RTCDIVR 0x44
103 #define RCC_DBGCFGR 0x80C
104
105 #define RCC_CLR 0x4
106
107 static const char * const ref12_parents[] = {
108 "ck_hsi", "ck_hse"
109 };
110
111 static const char * const ref3_parents[] = {
112 "ck_hsi", "ck_hse", "ck_csi"
113 };
114
115 static const char * const ref4_parents[] = {
116 "ck_hsi", "ck_hse", "ck_csi"
117 };
118
119 static const char * const cpu_src[] = {
120 "ck_hsi", "ck_hse", "pll1_p"
121 };
122
123 static const char * const axi_src[] = {
124 "ck_hsi", "ck_hse", "pll2_p"
125 };
126
127 static const char * const per_src[] = {
128 "ck_hsi", "ck_csi", "ck_hse"
129 };
130
131 static const char * const mcu_src[] = {
132 "ck_hsi", "ck_hse", "ck_csi", "pll3_p"
133 };
134
135 static const char * const sdmmc12_src[] = {
136 "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
137 };
138
139 static const char * const sdmmc3_src[] = {
140 "ck_mcu", "pll3_r", "pll4_p", "ck_hsi"
141 };
142
143 static const char * const fmc_src[] = {
144 "ck_axi", "pll3_r", "pll4_p", "ck_per"
145 };
146
147 static const char * const qspi_src[] = {
148 "ck_axi", "pll3_r", "pll4_p", "ck_per"
149 };
150
151 static const char * const eth_src[] = {
152 "pll4_p", "pll3_q"
153 };
154
155 static const char * const rng_src[] = {
156 "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
157 };
158
159 static const char * const usbphy_src[] = {
160 "ck_hse", "pll4_r", "clk-hse-div2"
161 };
162
163 static const char * const usbo_src[] = {
164 "pll4_r", "ck_usbo_48m"
165 };
166
167 static const char * const stgen_src[] = {
168 "ck_hsi", "ck_hse"
169 };
170
171 static const char * const spdif_src[] = {
172 "pll4_p", "pll3_q", "ck_hsi"
173 };
174
175 static const char * const spi123_src[] = {
176 "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
177 };
178
179 static const char * const spi45_src[] = {
180 "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
181 };
182
183 static const char * const spi6_src[] = {
184 "pclk5", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "pll3_q"
185 };
186
187 static const char * const cec_src[] = {
188 "ck_lse", "ck_lsi", "ck_csi"
189 };
190
191 static const char * const i2c12_src[] = {
192 "pclk1", "pll4_r", "ck_hsi", "ck_csi"
193 };
194
195 static const char * const i2c35_src[] = {
196 "pclk1", "pll4_r", "ck_hsi", "ck_csi"
197 };
198
199 static const char * const i2c46_src[] = {
200 "pclk5", "pll3_q", "ck_hsi", "ck_csi"
201 };
202
203 static const char * const lptim1_src[] = {
204 "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
205 };
206
207 static const char * const lptim23_src[] = {
208 "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
209 };
210
211 static const char * const lptim45_src[] = {
212 "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
213 };
214
215 static const char * const usart1_src[] = {
216 "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
217 };
218
219 static const char * const usart234578_src[] = {
220 "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
221 };
222
223 static const char * const usart6_src[] = {
224 "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
225 };
226
227 static const char * const fdcan_src[] = {
228 "ck_hse", "pll3_q", "pll4_q", "pll4_r"
229 };
230
231 static const char * const sai_src[] = {
232 "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
233 };
234
235 static const char * const sai2_src[] = {
236 "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
237 };
238
239 static const char * const adc12_src[] = {
240 "pll4_r", "ck_per", "pll3_q"
241 };
242
243 static const char * const dsi_src[] = {
244 "ck_dsi_phy", "pll4_p"
245 };
246
247 static const char * const rtc_src[] = {
248 "off", "ck_lse", "ck_lsi", "ck_hse_rtc"
249 };
250
251 static const char * const mco1_src[] = {
252 "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
253 };
254
255 static const char * const mco2_src[] = {
256 "ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
257 };
258
259 static const char * const ck_trace_src[] = {
260 "ck_axi"
261 };
262
263 static const struct clk_div_table axi_div_table[] = {
264 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
265 { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
266 { 0 },
267 };
268
269 static const struct clk_div_table mcu_div_table[] = {
270 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
271 { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
272 { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
273 { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
274 { 0 },
275 };
276
277 static const struct clk_div_table apb_div_table[] = {
278 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
279 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
280 { 0 },
281 };
282
283 static const struct clk_div_table ck_trace_div_table[] = {
284 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
285 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
286 { 0 },
287 };
288
289 #define MAX_MUX_CLK 2
290
291 struct stm32_mmux {
292 u8 nbr_clk;
293 struct clk_hw *hws[MAX_MUX_CLK];
294 };
295
296 struct stm32_clk_mmux {
297 struct clk_mux mux;
298 struct stm32_mmux *mmux;
299 };
300
301 struct stm32_mgate {
302 u8 nbr_clk;
303 u32 flag;
304 };
305
306 struct stm32_clk_mgate {
307 struct clk_gate gate;
308 struct stm32_mgate *mgate;
309 u32 mask;
310 };
311
312 struct clock_config {
313 u32 id;
314 const char *name;
315 const char *parent_name;
316 const char * const *parent_names;
317 int num_parents;
318 unsigned long flags;
319 void *cfg;
320 struct clk_hw * (*func)(struct device *dev,
321 struct clk_hw_onecell_data *clk_data,
322 void __iomem *base, spinlock_t *lock,
323 const struct clock_config *cfg);
324 };
325
326 #define NO_ID ~0
327
328 struct gate_cfg {
329 u32 reg_off;
330 u8 bit_idx;
331 u8 gate_flags;
332 };
333
334 struct fixed_factor_cfg {
335 unsigned int mult;
336 unsigned int div;
337 };
338
339 struct div_cfg {
340 u32 reg_off;
341 u8 shift;
342 u8 width;
343 u8 div_flags;
344 const struct clk_div_table *table;
345 };
346
347 struct mux_cfg {
348 u32 reg_off;
349 u8 shift;
350 u8 width;
351 u8 mux_flags;
352 u32 *table;
353 };
354
355 struct stm32_gate_cfg {
356 struct gate_cfg *gate;
357 struct stm32_mgate *mgate;
358 const struct clk_ops *ops;
359 };
360
361 struct stm32_div_cfg {
362 struct div_cfg *div;
363 const struct clk_ops *ops;
364 };
365
366 struct stm32_mux_cfg {
367 struct mux_cfg *mux;
368 struct stm32_mmux *mmux;
369 const struct clk_ops *ops;
370 };
371
372 /* STM32 Composite clock */
373 struct stm32_composite_cfg {
374 const struct stm32_gate_cfg *gate;
375 const struct stm32_div_cfg *div;
376 const struct stm32_mux_cfg *mux;
377 };
378
379 static struct clk_hw *
_clk_hw_register_gate(struct device * dev,struct clk_hw_onecell_data * clk_data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)380 _clk_hw_register_gate(struct device *dev,
381 struct clk_hw_onecell_data *clk_data,
382 void __iomem *base, spinlock_t *lock,
383 const struct clock_config *cfg)
384 {
385 struct gate_cfg *gate_cfg = cfg->cfg;
386
387 return clk_hw_register_gate(dev,
388 cfg->name,
389 cfg->parent_name,
390 cfg->flags,
391 gate_cfg->reg_off + base,
392 gate_cfg->bit_idx,
393 gate_cfg->gate_flags,
394 lock);
395 }
396
397 static struct clk_hw *
_clk_hw_register_fixed_factor(struct device * dev,struct clk_hw_onecell_data * clk_data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)398 _clk_hw_register_fixed_factor(struct device *dev,
399 struct clk_hw_onecell_data *clk_data,
400 void __iomem *base, spinlock_t *lock,
401 const struct clock_config *cfg)
402 {
403 struct fixed_factor_cfg *ff_cfg = cfg->cfg;
404
405 return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,
406 cfg->flags, ff_cfg->mult,
407 ff_cfg->div);
408 }
409
410 static struct clk_hw *
_clk_hw_register_divider_table(struct device * dev,struct clk_hw_onecell_data * clk_data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)411 _clk_hw_register_divider_table(struct device *dev,
412 struct clk_hw_onecell_data *clk_data,
413 void __iomem *base, spinlock_t *lock,
414 const struct clock_config *cfg)
415 {
416 struct div_cfg *div_cfg = cfg->cfg;
417
418 return clk_hw_register_divider_table(dev,
419 cfg->name,
420 cfg->parent_name,
421 cfg->flags,
422 div_cfg->reg_off + base,
423 div_cfg->shift,
424 div_cfg->width,
425 div_cfg->div_flags,
426 div_cfg->table,
427 lock);
428 }
429
430 static struct clk_hw *
_clk_hw_register_mux(struct device * dev,struct clk_hw_onecell_data * clk_data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)431 _clk_hw_register_mux(struct device *dev,
432 struct clk_hw_onecell_data *clk_data,
433 void __iomem *base, spinlock_t *lock,
434 const struct clock_config *cfg)
435 {
436 struct mux_cfg *mux_cfg = cfg->cfg;
437
438 return clk_hw_register_mux(dev, cfg->name, cfg->parent_names,
439 cfg->num_parents, cfg->flags,
440 mux_cfg->reg_off + base, mux_cfg->shift,
441 mux_cfg->width, mux_cfg->mux_flags, lock);
442 }
443
444 /* MP1 Gate clock with set & clear registers */
445
mp1_gate_clk_enable(struct clk_hw * hw)446 static int mp1_gate_clk_enable(struct clk_hw *hw)
447 {
448 if (!clk_gate_ops.is_enabled(hw))
449 clk_gate_ops.enable(hw);
450
451 return 0;
452 }
453
mp1_gate_clk_disable(struct clk_hw * hw)454 static void mp1_gate_clk_disable(struct clk_hw *hw)
455 {
456 struct clk_gate *gate = to_clk_gate(hw);
457 unsigned long flags = 0;
458
459 if (clk_gate_ops.is_enabled(hw)) {
460 spin_lock_irqsave(gate->lock, flags);
461 writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR);
462 spin_unlock_irqrestore(gate->lock, flags);
463 }
464 }
465
466 static const struct clk_ops mp1_gate_clk_ops = {
467 .enable = mp1_gate_clk_enable,
468 .disable = mp1_gate_clk_disable,
469 .is_enabled = clk_gate_is_enabled,
470 };
471
_get_stm32_mux(void __iomem * base,const struct stm32_mux_cfg * cfg,spinlock_t * lock)472 static struct clk_hw *_get_stm32_mux(void __iomem *base,
473 const struct stm32_mux_cfg *cfg,
474 spinlock_t *lock)
475 {
476 struct stm32_clk_mmux *mmux;
477 struct clk_mux *mux;
478 struct clk_hw *mux_hw;
479
480 if (cfg->mmux) {
481 mmux = kzalloc(sizeof(*mmux), GFP_KERNEL);
482 if (!mmux)
483 return ERR_PTR(-ENOMEM);
484
485 mmux->mux.reg = cfg->mux->reg_off + base;
486 mmux->mux.shift = cfg->mux->shift;
487 mmux->mux.mask = (1 << cfg->mux->width) - 1;
488 mmux->mux.flags = cfg->mux->mux_flags;
489 mmux->mux.table = cfg->mux->table;
490 mmux->mux.lock = lock;
491 mmux->mmux = cfg->mmux;
492 mux_hw = &mmux->mux.hw;
493 cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
494
495 } else {
496 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
497 if (!mux)
498 return ERR_PTR(-ENOMEM);
499
500 mux->reg = cfg->mux->reg_off + base;
501 mux->shift = cfg->mux->shift;
502 mux->mask = (1 << cfg->mux->width) - 1;
503 mux->flags = cfg->mux->mux_flags;
504 mux->table = cfg->mux->table;
505 mux->lock = lock;
506 mux_hw = &mux->hw;
507 }
508
509 return mux_hw;
510 }
511
_get_stm32_div(void __iomem * base,const struct stm32_div_cfg * cfg,spinlock_t * lock)512 static struct clk_hw *_get_stm32_div(void __iomem *base,
513 const struct stm32_div_cfg *cfg,
514 spinlock_t *lock)
515 {
516 struct clk_divider *div;
517
518 div = kzalloc(sizeof(*div), GFP_KERNEL);
519
520 if (!div)
521 return ERR_PTR(-ENOMEM);
522
523 div->reg = cfg->div->reg_off + base;
524 div->shift = cfg->div->shift;
525 div->width = cfg->div->width;
526 div->flags = cfg->div->div_flags;
527 div->table = cfg->div->table;
528 div->lock = lock;
529
530 return &div->hw;
531 }
532
533 static struct clk_hw *
_get_stm32_gate(void __iomem * base,const struct stm32_gate_cfg * cfg,spinlock_t * lock)534 _get_stm32_gate(void __iomem *base,
535 const struct stm32_gate_cfg *cfg, spinlock_t *lock)
536 {
537 struct stm32_clk_mgate *mgate;
538 struct clk_gate *gate;
539 struct clk_hw *gate_hw;
540
541 if (cfg->mgate) {
542 mgate = kzalloc(sizeof(*mgate), GFP_KERNEL);
543 if (!mgate)
544 return ERR_PTR(-ENOMEM);
545
546 mgate->gate.reg = cfg->gate->reg_off + base;
547 mgate->gate.bit_idx = cfg->gate->bit_idx;
548 mgate->gate.flags = cfg->gate->gate_flags;
549 mgate->gate.lock = lock;
550 mgate->mask = BIT(cfg->mgate->nbr_clk++);
551
552 mgate->mgate = cfg->mgate;
553
554 gate_hw = &mgate->gate.hw;
555
556 } else {
557 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
558 if (!gate)
559 return ERR_PTR(-ENOMEM);
560
561 gate->reg = cfg->gate->reg_off + base;
562 gate->bit_idx = cfg->gate->bit_idx;
563 gate->flags = cfg->gate->gate_flags;
564 gate->lock = lock;
565
566 gate_hw = &gate->hw;
567 }
568
569 return gate_hw;
570 }
571
572 static struct clk_hw *
clk_stm32_register_gate_ops(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * base,const struct stm32_gate_cfg * cfg,spinlock_t * lock)573 clk_stm32_register_gate_ops(struct device *dev,
574 const char *name,
575 const char *parent_name,
576 unsigned long flags,
577 void __iomem *base,
578 const struct stm32_gate_cfg *cfg,
579 spinlock_t *lock)
580 {
581 struct clk_init_data init = { NULL };
582 struct clk_hw *hw;
583 int ret;
584
585 init.name = name;
586 init.parent_names = &parent_name;
587 init.num_parents = 1;
588 init.flags = flags;
589
590 init.ops = &clk_gate_ops;
591
592 if (cfg->ops)
593 init.ops = cfg->ops;
594
595 hw = _get_stm32_gate(base, cfg, lock);
596 if (IS_ERR(hw))
597 return ERR_PTR(-ENOMEM);
598
599 hw->init = &init;
600
601 ret = clk_hw_register(dev, hw);
602 if (ret)
603 hw = ERR_PTR(ret);
604
605 return hw;
606 }
607
608 static struct clk_hw *
clk_stm32_register_composite(struct device * dev,const char * name,const char * const * parent_names,int num_parents,void __iomem * base,const struct stm32_composite_cfg * cfg,unsigned long flags,spinlock_t * lock)609 clk_stm32_register_composite(struct device *dev,
610 const char *name, const char * const *parent_names,
611 int num_parents, void __iomem *base,
612 const struct stm32_composite_cfg *cfg,
613 unsigned long flags, spinlock_t *lock)
614 {
615 const struct clk_ops *mux_ops, *div_ops, *gate_ops;
616 struct clk_hw *mux_hw, *div_hw, *gate_hw;
617
618 mux_hw = NULL;
619 div_hw = NULL;
620 gate_hw = NULL;
621 mux_ops = NULL;
622 div_ops = NULL;
623 gate_ops = NULL;
624
625 if (cfg->mux) {
626 mux_hw = _get_stm32_mux(base, cfg->mux, lock);
627
628 if (!IS_ERR(mux_hw)) {
629 mux_ops = &clk_mux_ops;
630
631 if (cfg->mux->ops)
632 mux_ops = cfg->mux->ops;
633 }
634 }
635
636 if (cfg->div) {
637 div_hw = _get_stm32_div(base, cfg->div, lock);
638
639 if (!IS_ERR(div_hw)) {
640 div_ops = &clk_divider_ops;
641
642 if (cfg->div->ops)
643 div_ops = cfg->div->ops;
644 }
645 }
646
647 if (cfg->gate) {
648 gate_hw = _get_stm32_gate(base, cfg->gate, lock);
649
650 if (!IS_ERR(gate_hw)) {
651 gate_ops = &clk_gate_ops;
652
653 if (cfg->gate->ops)
654 gate_ops = cfg->gate->ops;
655 }
656 }
657
658 return clk_hw_register_composite(dev, name, parent_names, num_parents,
659 mux_hw, mux_ops, div_hw, div_ops,
660 gate_hw, gate_ops, flags);
661 }
662
663 #define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate)
664
mp1_mgate_clk_enable(struct clk_hw * hw)665 static int mp1_mgate_clk_enable(struct clk_hw *hw)
666 {
667 struct clk_gate *gate = to_clk_gate(hw);
668 struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
669
670 clk_mgate->mgate->flag |= clk_mgate->mask;
671
672 mp1_gate_clk_enable(hw);
673
674 return 0;
675 }
676
mp1_mgate_clk_disable(struct clk_hw * hw)677 static void mp1_mgate_clk_disable(struct clk_hw *hw)
678 {
679 struct clk_gate *gate = to_clk_gate(hw);
680 struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
681
682 clk_mgate->mgate->flag &= ~clk_mgate->mask;
683
684 if (clk_mgate->mgate->flag == 0)
685 mp1_gate_clk_disable(hw);
686 }
687
688 static const struct clk_ops mp1_mgate_clk_ops = {
689 .enable = mp1_mgate_clk_enable,
690 .disable = mp1_mgate_clk_disable,
691 .is_enabled = clk_gate_is_enabled,
692
693 };
694
695 #define to_clk_mmux(_mux) container_of(_mux, struct stm32_clk_mmux, mux)
696
clk_mmux_get_parent(struct clk_hw * hw)697 static u8 clk_mmux_get_parent(struct clk_hw *hw)
698 {
699 return clk_mux_ops.get_parent(hw);
700 }
701
clk_mmux_set_parent(struct clk_hw * hw,u8 index)702 static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
703 {
704 struct clk_mux *mux = to_clk_mux(hw);
705 struct stm32_clk_mmux *clk_mmux = to_clk_mmux(mux);
706 struct clk_hw *hwp;
707 int ret, n;
708
709 ret = clk_mux_ops.set_parent(hw, index);
710 if (ret)
711 return ret;
712
713 hwp = clk_hw_get_parent(hw);
714
715 for (n = 0; n < clk_mmux->mmux->nbr_clk; n++)
716 if (clk_mmux->mmux->hws[n] != hw)
717 clk_hw_reparent(clk_mmux->mmux->hws[n], hwp);
718
719 return 0;
720 }
721
722 static const struct clk_ops clk_mmux_ops = {
723 .get_parent = clk_mmux_get_parent,
724 .set_parent = clk_mmux_set_parent,
725 .determine_rate = __clk_mux_determine_rate,
726 };
727
728 /* STM32 PLL */
729 struct stm32_pll_obj {
730 /* lock pll enable/disable registers */
731 spinlock_t *lock;
732 void __iomem *reg;
733 struct clk_hw hw;
734 };
735
736 #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
737
738 #define PLL_ON BIT(0)
739 #define PLL_RDY BIT(1)
740 #define DIVN_MASK 0x1FF
741 #define DIVM_MASK 0x3F
742 #define DIVM_SHIFT 16
743 #define DIVN_SHIFT 0
744 #define FRAC_OFFSET 0xC
745 #define FRAC_MASK 0x1FFF
746 #define FRAC_SHIFT 3
747 #define FRACLE BIT(16)
748
__pll_is_enabled(struct clk_hw * hw)749 static int __pll_is_enabled(struct clk_hw *hw)
750 {
751 struct stm32_pll_obj *clk_elem = to_pll(hw);
752
753 return readl_relaxed(clk_elem->reg) & PLL_ON;
754 }
755
756 #define TIMEOUT 5
757
pll_enable(struct clk_hw * hw)758 static int pll_enable(struct clk_hw *hw)
759 {
760 struct stm32_pll_obj *clk_elem = to_pll(hw);
761 u32 reg;
762 unsigned long flags = 0;
763 unsigned int timeout = TIMEOUT;
764 int bit_status = 0;
765
766 spin_lock_irqsave(clk_elem->lock, flags);
767
768 if (__pll_is_enabled(hw))
769 goto unlock;
770
771 reg = readl_relaxed(clk_elem->reg);
772 reg |= PLL_ON;
773 writel_relaxed(reg, clk_elem->reg);
774
775 /* We can't use readl_poll_timeout() because we can be blocked if
776 * someone enables this clock before clocksource changes.
777 * Only jiffies counter is available. Jiffies are incremented by
778 * interruptions and enable op does not allow to be interrupted.
779 */
780 do {
781 bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY);
782
783 if (bit_status)
784 udelay(120);
785
786 } while (bit_status && --timeout);
787
788 unlock:
789 spin_unlock_irqrestore(clk_elem->lock, flags);
790
791 return bit_status;
792 }
793
pll_disable(struct clk_hw * hw)794 static void pll_disable(struct clk_hw *hw)
795 {
796 struct stm32_pll_obj *clk_elem = to_pll(hw);
797 u32 reg;
798 unsigned long flags = 0;
799
800 spin_lock_irqsave(clk_elem->lock, flags);
801
802 reg = readl_relaxed(clk_elem->reg);
803 reg &= ~PLL_ON;
804 writel_relaxed(reg, clk_elem->reg);
805
806 spin_unlock_irqrestore(clk_elem->lock, flags);
807 }
808
pll_frac_val(struct clk_hw * hw)809 static u32 pll_frac_val(struct clk_hw *hw)
810 {
811 struct stm32_pll_obj *clk_elem = to_pll(hw);
812 u32 reg, frac = 0;
813
814 reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET);
815 if (reg & FRACLE)
816 frac = (reg >> FRAC_SHIFT) & FRAC_MASK;
817
818 return frac;
819 }
820
pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)821 static unsigned long pll_recalc_rate(struct clk_hw *hw,
822 unsigned long parent_rate)
823 {
824 struct stm32_pll_obj *clk_elem = to_pll(hw);
825 u32 reg;
826 u32 frac, divm, divn;
827 u64 rate, rate_frac = 0;
828
829 reg = readl_relaxed(clk_elem->reg + 4);
830
831 divm = ((reg >> DIVM_SHIFT) & DIVM_MASK) + 1;
832 divn = ((reg >> DIVN_SHIFT) & DIVN_MASK) + 1;
833 rate = (u64)parent_rate * divn;
834
835 do_div(rate, divm);
836
837 frac = pll_frac_val(hw);
838 if (frac) {
839 rate_frac = (u64)parent_rate * (u64)frac;
840 do_div(rate_frac, (divm * 8192));
841 }
842
843 return rate + rate_frac;
844 }
845
pll_is_enabled(struct clk_hw * hw)846 static int pll_is_enabled(struct clk_hw *hw)
847 {
848 struct stm32_pll_obj *clk_elem = to_pll(hw);
849 unsigned long flags = 0;
850 int ret;
851
852 spin_lock_irqsave(clk_elem->lock, flags);
853 ret = __pll_is_enabled(hw);
854 spin_unlock_irqrestore(clk_elem->lock, flags);
855
856 return ret;
857 }
858
859 static const struct clk_ops pll_ops = {
860 .enable = pll_enable,
861 .disable = pll_disable,
862 .recalc_rate = pll_recalc_rate,
863 .is_enabled = pll_is_enabled,
864 };
865
clk_register_pll(struct device * dev,const char * name,const char * parent_name,void __iomem * reg,unsigned long flags,spinlock_t * lock)866 static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
867 const char *parent_name,
868 void __iomem *reg,
869 unsigned long flags,
870 spinlock_t *lock)
871 {
872 struct stm32_pll_obj *element;
873 struct clk_init_data init;
874 struct clk_hw *hw;
875 int err;
876
877 element = kzalloc(sizeof(*element), GFP_KERNEL);
878 if (!element)
879 return ERR_PTR(-ENOMEM);
880
881 init.name = name;
882 init.ops = &pll_ops;
883 init.flags = flags;
884 init.parent_names = &parent_name;
885 init.num_parents = 1;
886
887 element->hw.init = &init;
888 element->reg = reg;
889 element->lock = lock;
890
891 hw = &element->hw;
892 err = clk_hw_register(dev, hw);
893
894 if (err) {
895 kfree(element);
896 return ERR_PTR(err);
897 }
898
899 return hw;
900 }
901
902 /* Kernel Timer */
903 struct timer_cker {
904 /* lock the kernel output divider register */
905 spinlock_t *lock;
906 void __iomem *apbdiv;
907 void __iomem *timpre;
908 struct clk_hw hw;
909 };
910
911 #define to_timer_cker(_hw) container_of(_hw, struct timer_cker, hw)
912
913 #define APB_DIV_MASK 0x07
914 #define TIM_PRE_MASK 0x01
915
__bestmult(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)916 static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
917 unsigned long parent_rate)
918 {
919 struct timer_cker *tim_ker = to_timer_cker(hw);
920 u32 prescaler;
921 unsigned int mult = 0;
922
923 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
924 if (prescaler < 2)
925 return 1;
926
927 mult = 2;
928
929 if (rate / parent_rate >= 4)
930 mult = 4;
931
932 return mult;
933 }
934
timer_ker_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)935 static long timer_ker_round_rate(struct clk_hw *hw, unsigned long rate,
936 unsigned long *parent_rate)
937 {
938 unsigned long factor = __bestmult(hw, rate, *parent_rate);
939
940 return *parent_rate * factor;
941 }
942
timer_ker_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)943 static int timer_ker_set_rate(struct clk_hw *hw, unsigned long rate,
944 unsigned long parent_rate)
945 {
946 struct timer_cker *tim_ker = to_timer_cker(hw);
947 unsigned long flags = 0;
948 unsigned long factor = __bestmult(hw, rate, parent_rate);
949 int ret = 0;
950
951 spin_lock_irqsave(tim_ker->lock, flags);
952
953 switch (factor) {
954 case 1:
955 break;
956 case 2:
957 writel_relaxed(0, tim_ker->timpre);
958 break;
959 case 4:
960 writel_relaxed(1, tim_ker->timpre);
961 break;
962 default:
963 ret = -EINVAL;
964 }
965 spin_unlock_irqrestore(tim_ker->lock, flags);
966
967 return ret;
968 }
969
timer_ker_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)970 static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
971 unsigned long parent_rate)
972 {
973 struct timer_cker *tim_ker = to_timer_cker(hw);
974 u32 prescaler, timpre;
975 u32 mul;
976
977 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
978
979 timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK;
980
981 if (!prescaler)
982 return parent_rate;
983
984 mul = (timpre + 1) * 2;
985
986 return parent_rate * mul;
987 }
988
989 static const struct clk_ops timer_ker_ops = {
990 .recalc_rate = timer_ker_recalc_rate,
991 .round_rate = timer_ker_round_rate,
992 .set_rate = timer_ker_set_rate,
993
994 };
995
clk_register_cktim(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * apbdiv,void __iomem * timpre,spinlock_t * lock)996 static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
997 const char *parent_name,
998 unsigned long flags,
999 void __iomem *apbdiv,
1000 void __iomem *timpre,
1001 spinlock_t *lock)
1002 {
1003 struct timer_cker *tim_ker;
1004 struct clk_init_data init;
1005 struct clk_hw *hw;
1006 int err;
1007
1008 tim_ker = kzalloc(sizeof(*tim_ker), GFP_KERNEL);
1009 if (!tim_ker)
1010 return ERR_PTR(-ENOMEM);
1011
1012 init.name = name;
1013 init.ops = &timer_ker_ops;
1014 init.flags = flags;
1015 init.parent_names = &parent_name;
1016 init.num_parents = 1;
1017
1018 tim_ker->hw.init = &init;
1019 tim_ker->lock = lock;
1020 tim_ker->apbdiv = apbdiv;
1021 tim_ker->timpre = timpre;
1022
1023 hw = &tim_ker->hw;
1024 err = clk_hw_register(dev, hw);
1025
1026 if (err) {
1027 kfree(tim_ker);
1028 return ERR_PTR(err);
1029 }
1030
1031 return hw;
1032 }
1033
1034 struct stm32_pll_cfg {
1035 u32 offset;
1036 };
1037
_clk_register_pll(struct device * dev,struct clk_hw_onecell_data * clk_data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)1038 static struct clk_hw *_clk_register_pll(struct device *dev,
1039 struct clk_hw_onecell_data *clk_data,
1040 void __iomem *base, spinlock_t *lock,
1041 const struct clock_config *cfg)
1042 {
1043 struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
1044
1045 return clk_register_pll(dev, cfg->name, cfg->parent_name,
1046 base + stm_pll_cfg->offset, cfg->flags, lock);
1047 }
1048
1049 struct stm32_cktim_cfg {
1050 u32 offset_apbdiv;
1051 u32 offset_timpre;
1052 };
1053
_clk_register_cktim(struct device * dev,struct clk_hw_onecell_data * clk_data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)1054 static struct clk_hw *_clk_register_cktim(struct device *dev,
1055 struct clk_hw_onecell_data *clk_data,
1056 void __iomem *base, spinlock_t *lock,
1057 const struct clock_config *cfg)
1058 {
1059 struct stm32_cktim_cfg *cktim_cfg = cfg->cfg;
1060
1061 return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags,
1062 cktim_cfg->offset_apbdiv + base,
1063 cktim_cfg->offset_timpre + base, lock);
1064 }
1065
1066 static struct clk_hw *
_clk_stm32_register_gate(struct device * dev,struct clk_hw_onecell_data * clk_data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)1067 _clk_stm32_register_gate(struct device *dev,
1068 struct clk_hw_onecell_data *clk_data,
1069 void __iomem *base, spinlock_t *lock,
1070 const struct clock_config *cfg)
1071 {
1072 return clk_stm32_register_gate_ops(dev,
1073 cfg->name,
1074 cfg->parent_name,
1075 cfg->flags,
1076 base,
1077 cfg->cfg,
1078 lock);
1079 }
1080
1081 static struct clk_hw *
_clk_stm32_register_composite(struct device * dev,struct clk_hw_onecell_data * clk_data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)1082 _clk_stm32_register_composite(struct device *dev,
1083 struct clk_hw_onecell_data *clk_data,
1084 void __iomem *base, spinlock_t *lock,
1085 const struct clock_config *cfg)
1086 {
1087 return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,
1088 cfg->num_parents, base, cfg->cfg,
1089 cfg->flags, lock);
1090 }
1091
1092 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1093 {\
1094 .id = _id,\
1095 .name = _name,\
1096 .parent_name = _parent,\
1097 .flags = _flags,\
1098 .cfg = &(struct gate_cfg) {\
1099 .reg_off = _offset,\
1100 .bit_idx = _bit_idx,\
1101 .gate_flags = _gate_flags,\
1102 },\
1103 .func = _clk_hw_register_gate,\
1104 }
1105
1106 #define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\
1107 {\
1108 .id = _id,\
1109 .name = _name,\
1110 .parent_name = _parent,\
1111 .flags = _flags,\
1112 .cfg = &(struct fixed_factor_cfg) {\
1113 .mult = _mult,\
1114 .div = _div,\
1115 },\
1116 .func = _clk_hw_register_fixed_factor,\
1117 }
1118
1119 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1120 _div_flags, _div_table)\
1121 {\
1122 .id = _id,\
1123 .name = _name,\
1124 .parent_name = _parent,\
1125 .flags = _flags,\
1126 .cfg = &(struct div_cfg) {\
1127 .reg_off = _offset,\
1128 .shift = _shift,\
1129 .width = _width,\
1130 .div_flags = _div_flags,\
1131 .table = _div_table,\
1132 },\
1133 .func = _clk_hw_register_divider_table,\
1134 }
1135
1136 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\
1137 DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1138 _div_flags, NULL)
1139
1140 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\
1141 {\
1142 .id = _id,\
1143 .name = _name,\
1144 .parent_names = _parents,\
1145 .num_parents = ARRAY_SIZE(_parents),\
1146 .flags = _flags,\
1147 .cfg = &(struct mux_cfg) {\
1148 .reg_off = _offset,\
1149 .shift = _shift,\
1150 .width = _width,\
1151 .mux_flags = _mux_flags,\
1152 },\
1153 .func = _clk_hw_register_mux,\
1154 }
1155
1156 #define PLL(_id, _name, _parent, _flags, _offset)\
1157 {\
1158 .id = _id,\
1159 .name = _name,\
1160 .parent_name = _parent,\
1161 .flags = _flags,\
1162 .cfg = &(struct stm32_pll_cfg) {\
1163 .offset = _offset,\
1164 },\
1165 .func = _clk_register_pll,\
1166 }
1167
1168 #define STM32_CKTIM(_name, _parent, _flags, _offset_apbdiv, _offset_timpre)\
1169 {\
1170 .id = NO_ID,\
1171 .name = _name,\
1172 .parent_name = _parent,\
1173 .flags = _flags,\
1174 .cfg = &(struct stm32_cktim_cfg) {\
1175 .offset_apbdiv = _offset_apbdiv,\
1176 .offset_timpre = _offset_timpre,\
1177 },\
1178 .func = _clk_register_cktim,\
1179 }
1180
1181 #define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\
1182 GATE_MP1(_id, _name, _parent, CLK_SET_RATE_PARENT,\
1183 _offset_set, _bit_idx, 0)
1184
1185 /* STM32 GATE */
1186 #define STM32_GATE(_id, _name, _parent, _flags, _gate)\
1187 {\
1188 .id = _id,\
1189 .name = _name,\
1190 .parent_name = _parent,\
1191 .flags = _flags,\
1192 .cfg = (struct stm32_gate_cfg *) {_gate},\
1193 .func = _clk_stm32_register_gate,\
1194 }
1195
1196 #define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\
1197 (&(struct stm32_gate_cfg) {\
1198 &(struct gate_cfg) {\
1199 .reg_off = _gate_offset,\
1200 .bit_idx = _gate_bit_idx,\
1201 .gate_flags = _gate_flags,\
1202 },\
1203 .mgate = _mgate,\
1204 .ops = _ops,\
1205 })
1206
1207 #define _STM32_MGATE(_mgate)\
1208 (&per_gate_cfg[_mgate])
1209
1210 #define _GATE(_gate_offset, _gate_bit_idx, _gate_flags)\
1211 _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1212 NULL, NULL)\
1213
1214 #define _GATE_MP1(_gate_offset, _gate_bit_idx, _gate_flags)\
1215 _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1216 NULL, &mp1_gate_clk_ops)\
1217
1218 #define _MGATE_MP1(_mgate)\
1219 .gate = &per_gate_cfg[_mgate]
1220
1221 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1222 STM32_GATE(_id, _name, _parent, _flags,\
1223 _GATE_MP1(_offset, _bit_idx, _gate_flags))
1224
1225 #define MGATE_MP1(_id, _name, _parent, _flags, _mgate)\
1226 STM32_GATE(_id, _name, _parent, _flags,\
1227 _STM32_MGATE(_mgate))
1228
1229 #define _STM32_DIV(_div_offset, _div_shift, _div_width,\
1230 _div_flags, _div_table, _ops)\
1231 .div = &(struct stm32_div_cfg) {\
1232 &(struct div_cfg) {\
1233 .reg_off = _div_offset,\
1234 .shift = _div_shift,\
1235 .width = _div_width,\
1236 .div_flags = _div_flags,\
1237 .table = _div_table,\
1238 },\
1239 .ops = _ops,\
1240 }
1241
1242 #define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
1243 _STM32_DIV(_div_offset, _div_shift, _div_width,\
1244 _div_flags, _div_table, NULL)\
1245
1246 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
1247 .mux = &(struct stm32_mux_cfg) {\
1248 &(struct mux_cfg) {\
1249 .reg_off = _offset,\
1250 .shift = _shift,\
1251 .width = _width,\
1252 .mux_flags = _mux_flags,\
1253 .table = NULL,\
1254 },\
1255 .mmux = _mmux,\
1256 .ops = _ops,\
1257 }
1258
1259 #define _MUX(_offset, _shift, _width, _mux_flags)\
1260 _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\
1261
1262 #define _MMUX(_mmux) .mux = &ker_mux_cfg[_mmux]
1263
1264 #define PARENT(_parent) ((const char *[]) { _parent})
1265
1266 #define _NO_MUX .mux = NULL
1267 #define _NO_DIV .div = NULL
1268 #define _NO_GATE .gate = NULL
1269
1270 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\
1271 {\
1272 .id = _id,\
1273 .name = _name,\
1274 .parent_names = _parents,\
1275 .num_parents = ARRAY_SIZE(_parents),\
1276 .flags = _flags,\
1277 .cfg = &(struct stm32_composite_cfg) {\
1278 _gate,\
1279 _mux,\
1280 _div,\
1281 },\
1282 .func = _clk_stm32_register_composite,\
1283 }
1284
1285 #define PCLK(_id, _name, _parent, _flags, _mgate)\
1286 MGATE_MP1(_id, _name, _parent, _flags, _mgate)
1287
1288 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
1289 COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
1290 CLK_SET_RATE_NO_REPARENT | _flags,\
1291 _MGATE_MP1(_mgate),\
1292 _MMUX(_mmux),\
1293 _NO_DIV)
1294
1295 enum {
1296 G_SAI1,
1297 G_SAI2,
1298 G_SAI3,
1299 G_SAI4,
1300 G_SPI1,
1301 G_SPI2,
1302 G_SPI3,
1303 G_SPI4,
1304 G_SPI5,
1305 G_SPI6,
1306 G_SPDIF,
1307 G_I2C1,
1308 G_I2C2,
1309 G_I2C3,
1310 G_I2C4,
1311 G_I2C5,
1312 G_I2C6,
1313 G_USART2,
1314 G_UART4,
1315 G_USART3,
1316 G_UART5,
1317 G_USART1,
1318 G_USART6,
1319 G_UART7,
1320 G_UART8,
1321 G_LPTIM1,
1322 G_LPTIM2,
1323 G_LPTIM3,
1324 G_LPTIM4,
1325 G_LPTIM5,
1326 G_LTDC,
1327 G_DSI,
1328 G_QSPI,
1329 G_FMC,
1330 G_SDMMC1,
1331 G_SDMMC2,
1332 G_SDMMC3,
1333 G_USBO,
1334 G_USBPHY,
1335 G_RNG1,
1336 G_RNG2,
1337 G_FDCAN,
1338 G_DAC12,
1339 G_CEC,
1340 G_ADC12,
1341 G_GPU,
1342 G_STGEN,
1343 G_DFSDM,
1344 G_ADFSDM,
1345 G_TIM2,
1346 G_TIM3,
1347 G_TIM4,
1348 G_TIM5,
1349 G_TIM6,
1350 G_TIM7,
1351 G_TIM12,
1352 G_TIM13,
1353 G_TIM14,
1354 G_MDIO,
1355 G_TIM1,
1356 G_TIM8,
1357 G_TIM15,
1358 G_TIM16,
1359 G_TIM17,
1360 G_SYSCFG,
1361 G_VREF,
1362 G_TMPSENS,
1363 G_PMBCTRL,
1364 G_HDP,
1365 G_IWDG2,
1366 G_STGENRO,
1367 G_DMA1,
1368 G_DMA2,
1369 G_DMAMUX,
1370 G_DCMI,
1371 G_CRYP2,
1372 G_HASH2,
1373 G_CRC2,
1374 G_HSEM,
1375 G_IPCC,
1376 G_GPIOA,
1377 G_GPIOB,
1378 G_GPIOC,
1379 G_GPIOD,
1380 G_GPIOE,
1381 G_GPIOF,
1382 G_GPIOG,
1383 G_GPIOH,
1384 G_GPIOI,
1385 G_GPIOJ,
1386 G_GPIOK,
1387 G_MDMA,
1388 G_ETHCK,
1389 G_ETHTX,
1390 G_ETHRX,
1391 G_ETHMAC,
1392 G_CRC1,
1393 G_USBH,
1394 G_ETHSTP,
1395 G_RTCAPB,
1396 G_TZC1,
1397 G_TZC2,
1398 G_TZPC,
1399 G_IWDG1,
1400 G_BSEC,
1401 G_GPIOZ,
1402 G_CRYP1,
1403 G_HASH1,
1404 G_BKPSRAM,
1405 G_DDRPERFM,
1406
1407 G_LAST
1408 };
1409
1410 static struct stm32_mgate mp1_mgate[G_LAST];
1411
1412 #define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1413 _mgate, _ops)\
1414 [_id] = {\
1415 &(struct gate_cfg) {\
1416 .reg_off = _gate_offset,\
1417 .bit_idx = _gate_bit_idx,\
1418 .gate_flags = _gate_flags,\
1419 },\
1420 .mgate = _mgate,\
1421 .ops = _ops,\
1422 }
1423
1424 #define K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1425 _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1426 NULL, &mp1_gate_clk_ops)
1427
1428 #define K_MGATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1429 _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1430 &mp1_mgate[_id], &mp1_mgate_clk_ops)
1431
1432 /* Peripheral gates */
1433 static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
1434 /* Multi gates */
1435 K_GATE(G_MDIO, RCC_APB1ENSETR, 31, 0),
1436 K_MGATE(G_DAC12, RCC_APB1ENSETR, 29, 0),
1437 K_MGATE(G_CEC, RCC_APB1ENSETR, 27, 0),
1438 K_MGATE(G_SPDIF, RCC_APB1ENSETR, 26, 0),
1439 K_MGATE(G_I2C5, RCC_APB1ENSETR, 24, 0),
1440 K_MGATE(G_I2C3, RCC_APB1ENSETR, 23, 0),
1441 K_MGATE(G_I2C2, RCC_APB1ENSETR, 22, 0),
1442 K_MGATE(G_I2C1, RCC_APB1ENSETR, 21, 0),
1443 K_MGATE(G_UART8, RCC_APB1ENSETR, 19, 0),
1444 K_MGATE(G_UART7, RCC_APB1ENSETR, 18, 0),
1445 K_MGATE(G_UART5, RCC_APB1ENSETR, 17, 0),
1446 K_MGATE(G_UART4, RCC_APB1ENSETR, 16, 0),
1447 K_MGATE(G_USART3, RCC_APB1ENSETR, 15, 0),
1448 K_MGATE(G_USART2, RCC_APB1ENSETR, 14, 0),
1449 K_MGATE(G_SPI3, RCC_APB1ENSETR, 12, 0),
1450 K_MGATE(G_SPI2, RCC_APB1ENSETR, 11, 0),
1451 K_MGATE(G_LPTIM1, RCC_APB1ENSETR, 9, 0),
1452 K_GATE(G_TIM14, RCC_APB1ENSETR, 8, 0),
1453 K_GATE(G_TIM13, RCC_APB1ENSETR, 7, 0),
1454 K_GATE(G_TIM12, RCC_APB1ENSETR, 6, 0),
1455 K_GATE(G_TIM7, RCC_APB1ENSETR, 5, 0),
1456 K_GATE(G_TIM6, RCC_APB1ENSETR, 4, 0),
1457 K_GATE(G_TIM5, RCC_APB1ENSETR, 3, 0),
1458 K_GATE(G_TIM4, RCC_APB1ENSETR, 2, 0),
1459 K_GATE(G_TIM3, RCC_APB1ENSETR, 1, 0),
1460 K_GATE(G_TIM2, RCC_APB1ENSETR, 0, 0),
1461
1462 K_MGATE(G_FDCAN, RCC_APB2ENSETR, 24, 0),
1463 K_GATE(G_ADFSDM, RCC_APB2ENSETR, 21, 0),
1464 K_GATE(G_DFSDM, RCC_APB2ENSETR, 20, 0),
1465 K_MGATE(G_SAI3, RCC_APB2ENSETR, 18, 0),
1466 K_MGATE(G_SAI2, RCC_APB2ENSETR, 17, 0),
1467 K_MGATE(G_SAI1, RCC_APB2ENSETR, 16, 0),
1468 K_MGATE(G_USART6, RCC_APB2ENSETR, 13, 0),
1469 K_MGATE(G_SPI5, RCC_APB2ENSETR, 10, 0),
1470 K_MGATE(G_SPI4, RCC_APB2ENSETR, 9, 0),
1471 K_MGATE(G_SPI1, RCC_APB2ENSETR, 8, 0),
1472 K_GATE(G_TIM17, RCC_APB2ENSETR, 4, 0),
1473 K_GATE(G_TIM16, RCC_APB2ENSETR, 3, 0),
1474 K_GATE(G_TIM15, RCC_APB2ENSETR, 2, 0),
1475 K_GATE(G_TIM8, RCC_APB2ENSETR, 1, 0),
1476 K_GATE(G_TIM1, RCC_APB2ENSETR, 0, 0),
1477
1478 K_GATE(G_HDP, RCC_APB3ENSETR, 20, 0),
1479 K_GATE(G_PMBCTRL, RCC_APB3ENSETR, 17, 0),
1480 K_GATE(G_TMPSENS, RCC_APB3ENSETR, 16, 0),
1481 K_GATE(G_VREF, RCC_APB3ENSETR, 13, 0),
1482 K_GATE(G_SYSCFG, RCC_APB3ENSETR, 11, 0),
1483 K_MGATE(G_SAI4, RCC_APB3ENSETR, 8, 0),
1484 K_MGATE(G_LPTIM5, RCC_APB3ENSETR, 3, 0),
1485 K_MGATE(G_LPTIM4, RCC_APB3ENSETR, 2, 0),
1486 K_MGATE(G_LPTIM3, RCC_APB3ENSETR, 1, 0),
1487 K_MGATE(G_LPTIM2, RCC_APB3ENSETR, 0, 0),
1488
1489 K_GATE(G_STGENRO, RCC_APB4ENSETR, 20, 0),
1490 K_MGATE(G_USBPHY, RCC_APB4ENSETR, 16, 0),
1491 K_GATE(G_IWDG2, RCC_APB4ENSETR, 15, 0),
1492 K_GATE(G_DDRPERFM, RCC_APB4ENSETR, 8, 0),
1493 K_MGATE(G_DSI, RCC_APB4ENSETR, 4, 0),
1494 K_MGATE(G_LTDC, RCC_APB4ENSETR, 0, 0),
1495
1496 K_GATE(G_STGEN, RCC_APB5ENSETR, 20, 0),
1497 K_GATE(G_BSEC, RCC_APB5ENSETR, 16, 0),
1498 K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
1499 K_GATE(G_TZPC, RCC_APB5ENSETR, 13, 0),
1500 K_GATE(G_TZC2, RCC_APB5ENSETR, 12, 0),
1501 K_GATE(G_TZC1, RCC_APB5ENSETR, 11, 0),
1502 K_GATE(G_RTCAPB, RCC_APB5ENSETR, 8, 0),
1503 K_MGATE(G_USART1, RCC_APB5ENSETR, 4, 0),
1504 K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
1505 K_MGATE(G_I2C4, RCC_APB5ENSETR, 2, 0),
1506 K_MGATE(G_SPI6, RCC_APB5ENSETR, 0, 0),
1507
1508 K_MGATE(G_SDMMC3, RCC_AHB2ENSETR, 16, 0),
1509 K_MGATE(G_USBO, RCC_AHB2ENSETR, 8, 0),
1510 K_MGATE(G_ADC12, RCC_AHB2ENSETR, 5, 0),
1511 K_GATE(G_DMAMUX, RCC_AHB2ENSETR, 2, 0),
1512 K_GATE(G_DMA2, RCC_AHB2ENSETR, 1, 0),
1513 K_GATE(G_DMA1, RCC_AHB2ENSETR, 0, 0),
1514
1515 K_GATE(G_IPCC, RCC_AHB3ENSETR, 12, 0),
1516 K_GATE(G_HSEM, RCC_AHB3ENSETR, 11, 0),
1517 K_GATE(G_CRC2, RCC_AHB3ENSETR, 7, 0),
1518 K_MGATE(G_RNG2, RCC_AHB3ENSETR, 6, 0),
1519 K_GATE(G_HASH2, RCC_AHB3ENSETR, 5, 0),
1520 K_GATE(G_CRYP2, RCC_AHB3ENSETR, 4, 0),
1521 K_GATE(G_DCMI, RCC_AHB3ENSETR, 0, 0),
1522
1523 K_GATE(G_GPIOK, RCC_AHB4ENSETR, 10, 0),
1524 K_GATE(G_GPIOJ, RCC_AHB4ENSETR, 9, 0),
1525 K_GATE(G_GPIOI, RCC_AHB4ENSETR, 8, 0),
1526 K_GATE(G_GPIOH, RCC_AHB4ENSETR, 7, 0),
1527 K_GATE(G_GPIOG, RCC_AHB4ENSETR, 6, 0),
1528 K_GATE(G_GPIOF, RCC_AHB4ENSETR, 5, 0),
1529 K_GATE(G_GPIOE, RCC_AHB4ENSETR, 4, 0),
1530 K_GATE(G_GPIOD, RCC_AHB4ENSETR, 3, 0),
1531 K_GATE(G_GPIOC, RCC_AHB4ENSETR, 2, 0),
1532 K_GATE(G_GPIOB, RCC_AHB4ENSETR, 1, 0),
1533 K_GATE(G_GPIOA, RCC_AHB4ENSETR, 0, 0),
1534
1535 K_GATE(G_BKPSRAM, RCC_AHB5ENSETR, 8, 0),
1536 K_MGATE(G_RNG1, RCC_AHB5ENSETR, 6, 0),
1537 K_GATE(G_HASH1, RCC_AHB5ENSETR, 5, 0),
1538 K_GATE(G_CRYP1, RCC_AHB5ENSETR, 4, 0),
1539 K_GATE(G_GPIOZ, RCC_AHB5ENSETR, 0, 0),
1540
1541 K_GATE(G_USBH, RCC_AHB6ENSETR, 24, 0),
1542 K_GATE(G_CRC1, RCC_AHB6ENSETR, 20, 0),
1543 K_MGATE(G_SDMMC2, RCC_AHB6ENSETR, 17, 0),
1544 K_MGATE(G_SDMMC1, RCC_AHB6ENSETR, 16, 0),
1545 K_MGATE(G_QSPI, RCC_AHB6ENSETR, 14, 0),
1546 K_MGATE(G_FMC, RCC_AHB6ENSETR, 12, 0),
1547 K_GATE(G_ETHMAC, RCC_AHB6ENSETR, 10, 0),
1548 K_GATE(G_ETHRX, RCC_AHB6ENSETR, 9, 0),
1549 K_GATE(G_ETHTX, RCC_AHB6ENSETR, 8, 0),
1550 K_GATE(G_ETHCK, RCC_AHB6ENSETR, 7, 0),
1551 K_MGATE(G_GPU, RCC_AHB6ENSETR, 5, 0),
1552 K_GATE(G_MDMA, RCC_AHB6ENSETR, 0, 0),
1553 K_GATE(G_ETHSTP, RCC_AHB6LPENSETR, 11, 0),
1554 };
1555
1556 enum {
1557 M_SDMMC12,
1558 M_SDMMC3,
1559 M_FMC,
1560 M_QSPI,
1561 M_RNG1,
1562 M_RNG2,
1563 M_USBPHY,
1564 M_USBO,
1565 M_STGEN,
1566 M_SPDIF,
1567 M_SPI1,
1568 M_SPI23,
1569 M_SPI45,
1570 M_SPI6,
1571 M_CEC,
1572 M_I2C12,
1573 M_I2C35,
1574 M_I2C46,
1575 M_LPTIM1,
1576 M_LPTIM23,
1577 M_LPTIM45,
1578 M_USART1,
1579 M_UART24,
1580 M_UART35,
1581 M_USART6,
1582 M_UART78,
1583 M_SAI1,
1584 M_SAI2,
1585 M_SAI3,
1586 M_SAI4,
1587 M_DSI,
1588 M_FDCAN,
1589 M_ADC12,
1590 M_ETHCK,
1591 M_CKPER,
1592 M_LAST
1593 };
1594
1595 static struct stm32_mmux ker_mux[M_LAST];
1596
1597 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
1598 [_id] = {\
1599 &(struct mux_cfg) {\
1600 .reg_off = _offset,\
1601 .shift = _shift,\
1602 .width = _width,\
1603 .mux_flags = _mux_flags,\
1604 .table = NULL,\
1605 },\
1606 .mmux = _mmux,\
1607 .ops = _ops,\
1608 }
1609
1610 #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\
1611 _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1612 NULL, NULL)
1613
1614 #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\
1615 _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1616 &ker_mux[_id], &clk_mmux_ops)
1617
1618 static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
1619 /* Kernel multi mux */
1620 K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
1621 K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
1622 K_MMUX(M_SPI45, RCC_SPI2S45CKSELR, 0, 3, 0),
1623 K_MMUX(M_I2C12, RCC_I2C12CKSELR, 0, 3, 0),
1624 K_MMUX(M_I2C35, RCC_I2C35CKSELR, 0, 3, 0),
1625 K_MMUX(M_LPTIM23, RCC_LPTIM23CKSELR, 0, 3, 0),
1626 K_MMUX(M_LPTIM45, RCC_LPTIM45CKSELR, 0, 3, 0),
1627 K_MMUX(M_UART24, RCC_UART24CKSELR, 0, 3, 0),
1628 K_MMUX(M_UART35, RCC_UART35CKSELR, 0, 3, 0),
1629 K_MMUX(M_UART78, RCC_UART78CKSELR, 0, 3, 0),
1630 K_MMUX(M_SAI1, RCC_SAI1CKSELR, 0, 3, 0),
1631 K_MMUX(M_ETHCK, RCC_ETHCKSELR, 0, 2, 0),
1632 K_MMUX(M_I2C46, RCC_I2C46CKSELR, 0, 3, 0),
1633
1634 /* Kernel simple mux */
1635 K_MUX(M_RNG2, RCC_RNG2CKSELR, 0, 2, 0),
1636 K_MUX(M_SDMMC3, RCC_SDMMC3CKSELR, 0, 3, 0),
1637 K_MUX(M_FMC, RCC_FMCCKSELR, 0, 2, 0),
1638 K_MUX(M_QSPI, RCC_QSPICKSELR, 0, 2, 0),
1639 K_MUX(M_USBPHY, RCC_USBCKSELR, 0, 2, 0),
1640 K_MUX(M_USBO, RCC_USBCKSELR, 4, 1, 0),
1641 K_MUX(M_SPDIF, RCC_SPDIFCKSELR, 0, 2, 0),
1642 K_MUX(M_SPI1, RCC_SPI2S1CKSELR, 0, 3, 0),
1643 K_MUX(M_CEC, RCC_CECCKSELR, 0, 2, 0),
1644 K_MUX(M_LPTIM1, RCC_LPTIM1CKSELR, 0, 3, 0),
1645 K_MUX(M_USART6, RCC_UART6CKSELR, 0, 3, 0),
1646 K_MUX(M_FDCAN, RCC_FDCANCKSELR, 0, 2, 0),
1647 K_MUX(M_SAI2, RCC_SAI2CKSELR, 0, 3, 0),
1648 K_MUX(M_SAI3, RCC_SAI3CKSELR, 0, 3, 0),
1649 K_MUX(M_SAI4, RCC_SAI4CKSELR, 0, 3, 0),
1650 K_MUX(M_ADC12, RCC_ADCCKSELR, 0, 2, 0),
1651 K_MUX(M_DSI, RCC_DSICKSELR, 0, 1, 0),
1652 K_MUX(M_CKPER, RCC_CPERCKSELR, 0, 2, 0),
1653 K_MUX(M_RNG1, RCC_RNG1CKSELR, 0, 2, 0),
1654 K_MUX(M_STGEN, RCC_STGENCKSELR, 0, 2, 0),
1655 K_MUX(M_USART1, RCC_UART1CKSELR, 0, 3, 0),
1656 K_MUX(M_SPI6, RCC_SPI6CKSELR, 0, 3, 0),
1657 };
1658
1659 static const struct clock_config stm32mp1_clock_cfg[] = {
1660 /* Oscillator divider */
1661 DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
1662 RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
1663
1664 /* External / Internal Oscillators */
1665 GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1666 /* ck_csi is used by IO compensation and should be critical */
1667 GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
1668 RCC_OCENSETR, 4, 0),
1669 GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
1670 GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1671 GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1672
1673 FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
1674
1675 /* ref clock pll */
1676 MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
1677 0, 2, CLK_MUX_READ_ONLY),
1678
1679 MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
1680 0, 2, CLK_MUX_READ_ONLY),
1681
1682 MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
1683 0, 2, CLK_MUX_READ_ONLY),
1684
1685 /* PLLs */
1686 PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
1687 PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
1688 PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),
1689 PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),
1690
1691 /* ODF */
1692 COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
1693 _GATE(RCC_PLL1CR, 4, 0),
1694 _NO_MUX,
1695 _DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
1696
1697 COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
1698 _GATE(RCC_PLL2CR, 4, 0),
1699 _NO_MUX,
1700 _DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
1701
1702 COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
1703 _GATE(RCC_PLL2CR, 5, 0),
1704 _NO_MUX,
1705 _DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),
1706
1707 COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,
1708 _GATE(RCC_PLL2CR, 6, 0),
1709 _NO_MUX,
1710 _DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
1711
1712 COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
1713 _GATE(RCC_PLL3CR, 4, 0),
1714 _NO_MUX,
1715 _DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
1716
1717 COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
1718 _GATE(RCC_PLL3CR, 5, 0),
1719 _NO_MUX,
1720 _DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),
1721
1722 COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
1723 _GATE(RCC_PLL3CR, 6, 0),
1724 _NO_MUX,
1725 _DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),
1726
1727 COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
1728 _GATE(RCC_PLL4CR, 4, 0),
1729 _NO_MUX,
1730 _DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),
1731
1732 COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
1733 _GATE(RCC_PLL4CR, 5, 0),
1734 _NO_MUX,
1735 _DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),
1736
1737 COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
1738 _GATE(RCC_PLL4CR, 6, 0),
1739 _NO_MUX,
1740 _DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
1741
1742 /* MUX system clocks */
1743 MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
1744 RCC_CPERCKSELR, 0, 2, 0),
1745
1746 MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
1747 CLK_IS_CRITICAL, RCC_MPCKSELR, 0, 2, 0),
1748
1749 COMPOSITE(CK_AXI, "ck_axi", axi_src, CLK_IS_CRITICAL |
1750 CLK_OPS_PARENT_ENABLE,
1751 _NO_GATE,
1752 _MUX(RCC_ASSCKSELR, 0, 2, 0),
1753 _DIV(RCC_AXIDIVR, 0, 3, 0, axi_div_table)),
1754
1755 COMPOSITE(CK_MCU, "ck_mcu", mcu_src, CLK_IS_CRITICAL |
1756 CLK_OPS_PARENT_ENABLE,
1757 _NO_GATE,
1758 _MUX(RCC_MSSCKSELR, 0, 2, 0),
1759 _DIV(RCC_MCUDIVR, 0, 4, 0, mcu_div_table)),
1760
1761 DIV_TABLE(NO_ID, "pclk1", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB1DIVR, 0,
1762 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1763
1764 DIV_TABLE(NO_ID, "pclk2", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB2DIVR, 0,
1765 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1766
1767 DIV_TABLE(NO_ID, "pclk3", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB3DIVR, 0,
1768 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1769
1770 DIV_TABLE(NO_ID, "pclk4", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB4DIVR, 0,
1771 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1772
1773 DIV_TABLE(NO_ID, "pclk5", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB5DIVR, 0,
1774 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1775
1776 /* Kernel Timers */
1777 STM32_CKTIM("ck1_tim", "pclk1", 0, RCC_APB1DIVR, RCC_TIMG1PRER),
1778 STM32_CKTIM("ck2_tim", "pclk2", 0, RCC_APB2DIVR, RCC_TIMG2PRER),
1779
1780 STM32_TIM(TIM2_K, "tim2_k", "ck1_tim", RCC_APB1ENSETR, 0),
1781 STM32_TIM(TIM3_K, "tim3_k", "ck1_tim", RCC_APB1ENSETR, 1),
1782 STM32_TIM(TIM4_K, "tim4_k", "ck1_tim", RCC_APB1ENSETR, 2),
1783 STM32_TIM(TIM5_K, "tim5_k", "ck1_tim", RCC_APB1ENSETR, 3),
1784 STM32_TIM(TIM6_K, "tim6_k", "ck1_tim", RCC_APB1ENSETR, 4),
1785 STM32_TIM(TIM7_K, "tim7_k", "ck1_tim", RCC_APB1ENSETR, 5),
1786 STM32_TIM(TIM12_K, "tim12_k", "ck1_tim", RCC_APB1ENSETR, 6),
1787 STM32_TIM(TIM13_K, "tim13_k", "ck1_tim", RCC_APB1ENSETR, 7),
1788 STM32_TIM(TIM14_K, "tim14_k", "ck1_tim", RCC_APB1ENSETR, 8),
1789 STM32_TIM(TIM1_K, "tim1_k", "ck2_tim", RCC_APB2ENSETR, 0),
1790 STM32_TIM(TIM8_K, "tim8_k", "ck2_tim", RCC_APB2ENSETR, 1),
1791 STM32_TIM(TIM15_K, "tim15_k", "ck2_tim", RCC_APB2ENSETR, 2),
1792 STM32_TIM(TIM16_K, "tim16_k", "ck2_tim", RCC_APB2ENSETR, 3),
1793 STM32_TIM(TIM17_K, "tim17_k", "ck2_tim", RCC_APB2ENSETR, 4),
1794
1795 /* Peripheral clocks */
1796 PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1797 PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1798 PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1799 PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1800 PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1801 PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1802 PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1803 PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1804 PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
1805 PCLK(LPTIM1, "lptim1", "pclk1", 0, G_LPTIM1),
1806 PCLK(SPI2, "spi2", "pclk1", 0, G_SPI2),
1807 PCLK(SPI3, "spi3", "pclk1", 0, G_SPI3),
1808 PCLK(USART2, "usart2", "pclk1", 0, G_USART2),
1809 PCLK(USART3, "usart3", "pclk1", 0, G_USART3),
1810 PCLK(UART4, "uart4", "pclk1", 0, G_UART4),
1811 PCLK(UART5, "uart5", "pclk1", 0, G_UART5),
1812 PCLK(UART7, "uart7", "pclk1", 0, G_UART7),
1813 PCLK(UART8, "uart8", "pclk1", 0, G_UART8),
1814 PCLK(I2C1, "i2c1", "pclk1", 0, G_I2C1),
1815 PCLK(I2C2, "i2c2", "pclk1", 0, G_I2C2),
1816 PCLK(I2C3, "i2c3", "pclk1", 0, G_I2C3),
1817 PCLK(I2C5, "i2c5", "pclk1", 0, G_I2C5),
1818 PCLK(SPDIF, "spdif", "pclk1", 0, G_SPDIF),
1819 PCLK(CEC, "cec", "pclk1", 0, G_CEC),
1820 PCLK(DAC12, "dac12", "pclk1", 0, G_DAC12),
1821 PCLK(MDIO, "mdio", "pclk1", 0, G_MDIO),
1822 PCLK(TIM1, "tim1", "pclk2", CLK_IGNORE_UNUSED, G_TIM1),
1823 PCLK(TIM8, "tim8", "pclk2", CLK_IGNORE_UNUSED, G_TIM8),
1824 PCLK(TIM15, "tim15", "pclk2", CLK_IGNORE_UNUSED, G_TIM15),
1825 PCLK(TIM16, "tim16", "pclk2", CLK_IGNORE_UNUSED, G_TIM16),
1826 PCLK(TIM17, "tim17", "pclk2", CLK_IGNORE_UNUSED, G_TIM17),
1827 PCLK(SPI1, "spi1", "pclk2", 0, G_SPI1),
1828 PCLK(SPI4, "spi4", "pclk2", 0, G_SPI4),
1829 PCLK(SPI5, "spi5", "pclk2", 0, G_SPI5),
1830 PCLK(USART6, "usart6", "pclk2", 0, G_USART6),
1831 PCLK(SAI1, "sai1", "pclk2", 0, G_SAI1),
1832 PCLK(SAI2, "sai2", "pclk2", 0, G_SAI2),
1833 PCLK(SAI3, "sai3", "pclk2", 0, G_SAI3),
1834 PCLK(DFSDM, "dfsdm", "pclk2", 0, G_DFSDM),
1835 PCLK(FDCAN, "fdcan", "pclk2", 0, G_FDCAN),
1836 PCLK(LPTIM2, "lptim2", "pclk3", 0, G_LPTIM2),
1837 PCLK(LPTIM3, "lptim3", "pclk3", 0, G_LPTIM3),
1838 PCLK(LPTIM4, "lptim4", "pclk3", 0, G_LPTIM4),
1839 PCLK(LPTIM5, "lptim5", "pclk3", 0, G_LPTIM5),
1840 PCLK(SAI4, "sai4", "pclk3", 0, G_SAI4),
1841 PCLK(SYSCFG, "syscfg", "pclk3", 0, G_SYSCFG),
1842 PCLK(VREF, "vref", "pclk3", 13, G_VREF),
1843 PCLK(TMPSENS, "tmpsens", "pclk3", 0, G_TMPSENS),
1844 PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, G_PMBCTRL),
1845 PCLK(HDP, "hdp", "pclk3", 0, G_HDP),
1846 PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
1847 PCLK(DSI, "dsi", "pclk4", 0, G_DSI),
1848 PCLK(IWDG2, "iwdg2", "pclk4", 0, G_IWDG2),
1849 PCLK(USBPHY, "usbphy", "pclk4", 0, G_USBPHY),
1850 PCLK(STGENRO, "stgenro", "pclk4", 0, G_STGENRO),
1851 PCLK(SPI6, "spi6", "pclk5", 0, G_SPI6),
1852 PCLK(I2C4, "i2c4", "pclk5", 0, G_I2C4),
1853 PCLK(I2C6, "i2c6", "pclk5", 0, G_I2C6),
1854 PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
1855 PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
1856 CLK_IS_CRITICAL, G_RTCAPB),
1857 PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
1858 PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
1859 PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
1860 PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
1861 PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
1862 PCLK(STGEN, "stgen", "pclk5", CLK_IGNORE_UNUSED, G_STGEN),
1863 PCLK(DMA1, "dma1", "ck_mcu", 0, G_DMA1),
1864 PCLK(DMA2, "dma2", "ck_mcu", 0, G_DMA2),
1865 PCLK(DMAMUX, "dmamux", "ck_mcu", 0, G_DMAMUX),
1866 PCLK(ADC12, "adc12", "ck_mcu", 0, G_ADC12),
1867 PCLK(USBO, "usbo", "ck_mcu", 0, G_USBO),
1868 PCLK(SDMMC3, "sdmmc3", "ck_mcu", 0, G_SDMMC3),
1869 PCLK(DCMI, "dcmi", "ck_mcu", 0, G_DCMI),
1870 PCLK(CRYP2, "cryp2", "ck_mcu", 0, G_CRYP2),
1871 PCLK(HASH2, "hash2", "ck_mcu", 0, G_HASH2),
1872 PCLK(RNG2, "rng2", "ck_mcu", 0, G_RNG2),
1873 PCLK(CRC2, "crc2", "ck_mcu", 0, G_CRC2),
1874 PCLK(HSEM, "hsem", "ck_mcu", 0, G_HSEM),
1875 PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
1876 PCLK(GPIOA, "gpioa", "ck_mcu", 0, G_GPIOA),
1877 PCLK(GPIOB, "gpiob", "ck_mcu", 0, G_GPIOB),
1878 PCLK(GPIOC, "gpioc", "ck_mcu", 0, G_GPIOC),
1879 PCLK(GPIOD, "gpiod", "ck_mcu", 0, G_GPIOD),
1880 PCLK(GPIOE, "gpioe", "ck_mcu", 0, G_GPIOE),
1881 PCLK(GPIOF, "gpiof", "ck_mcu", 0, G_GPIOF),
1882 PCLK(GPIOG, "gpiog", "ck_mcu", 0, G_GPIOG),
1883 PCLK(GPIOH, "gpioh", "ck_mcu", 0, G_GPIOH),
1884 PCLK(GPIOI, "gpioi", "ck_mcu", 0, G_GPIOI),
1885 PCLK(GPIOJ, "gpioj", "ck_mcu", 0, G_GPIOJ),
1886 PCLK(GPIOK, "gpiok", "ck_mcu", 0, G_GPIOK),
1887 PCLK(GPIOZ, "gpioz", "ck_axi", CLK_IGNORE_UNUSED, G_GPIOZ),
1888 PCLK(CRYP1, "cryp1", "ck_axi", CLK_IGNORE_UNUSED, G_CRYP1),
1889 PCLK(HASH1, "hash1", "ck_axi", CLK_IGNORE_UNUSED, G_HASH1),
1890 PCLK(RNG1, "rng1", "ck_axi", 0, G_RNG1),
1891 PCLK(BKPSRAM, "bkpsram", "ck_axi", CLK_IGNORE_UNUSED, G_BKPSRAM),
1892 PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA),
1893 PCLK(GPU, "gpu", "ck_axi", 0, G_GPU),
1894 PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX),
1895 PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
1896 PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC),
1897 PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC),
1898 PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI),
1899 PCLK(SDMMC1, "sdmmc1", "ck_axi", 0, G_SDMMC1),
1900 PCLK(SDMMC2, "sdmmc2", "ck_axi", 0, G_SDMMC2),
1901 PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
1902 PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
1903 PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
1904 PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM),
1905
1906 /* Kernel clocks */
1907 KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
1908 KCLK(SDMMC2_K, "sdmmc2_k", sdmmc12_src, 0, G_SDMMC2, M_SDMMC12),
1909 KCLK(SDMMC3_K, "sdmmc3_k", sdmmc3_src, 0, G_SDMMC3, M_SDMMC3),
1910 KCLK(FMC_K, "fmc_k", fmc_src, 0, G_FMC, M_FMC),
1911 KCLK(QSPI_K, "qspi_k", qspi_src, 0, G_QSPI, M_QSPI),
1912 KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
1913 KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
1914 KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
1915 KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
1916 KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
1917 KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
1918 KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
1919 KCLK(SPI3_K, "spi3_k", spi123_src, 0, G_SPI3, M_SPI23),
1920 KCLK(SPI4_K, "spi4_k", spi45_src, 0, G_SPI4, M_SPI45),
1921 KCLK(SPI5_K, "spi5_k", spi45_src, 0, G_SPI5, M_SPI45),
1922 KCLK(SPI6_K, "spi6_k", spi6_src, 0, G_SPI6, M_SPI6),
1923 KCLK(CEC_K, "cec_k", cec_src, 0, G_CEC, M_CEC),
1924 KCLK(I2C1_K, "i2c1_k", i2c12_src, 0, G_I2C1, M_I2C12),
1925 KCLK(I2C2_K, "i2c2_k", i2c12_src, 0, G_I2C2, M_I2C12),
1926 KCLK(I2C3_K, "i2c3_k", i2c35_src, 0, G_I2C3, M_I2C35),
1927 KCLK(I2C5_K, "i2c5_k", i2c35_src, 0, G_I2C5, M_I2C35),
1928 KCLK(I2C4_K, "i2c4_k", i2c46_src, 0, G_I2C4, M_I2C46),
1929 KCLK(I2C6_K, "i2c6_k", i2c46_src, 0, G_I2C6, M_I2C46),
1930 KCLK(LPTIM1_K, "lptim1_k", lptim1_src, 0, G_LPTIM1, M_LPTIM1),
1931 KCLK(LPTIM2_K, "lptim2_k", lptim23_src, 0, G_LPTIM2, M_LPTIM23),
1932 KCLK(LPTIM3_K, "lptim3_k", lptim23_src, 0, G_LPTIM3, M_LPTIM23),
1933 KCLK(LPTIM4_K, "lptim4_k", lptim45_src, 0, G_LPTIM4, M_LPTIM45),
1934 KCLK(LPTIM5_K, "lptim5_k", lptim45_src, 0, G_LPTIM5, M_LPTIM45),
1935 KCLK(USART1_K, "usart1_k", usart1_src, 0, G_USART1, M_USART1),
1936 KCLK(USART2_K, "usart2_k", usart234578_src, 0, G_USART2, M_UART24),
1937 KCLK(USART3_K, "usart3_k", usart234578_src, 0, G_USART3, M_UART35),
1938 KCLK(UART4_K, "uart4_k", usart234578_src, 0, G_UART4, M_UART24),
1939 KCLK(UART5_K, "uart5_k", usart234578_src, 0, G_UART5, M_UART35),
1940 KCLK(USART6_K, "uart6_k", usart6_src, 0, G_USART6, M_USART6),
1941 KCLK(UART7_K, "uart7_k", usart234578_src, 0, G_UART7, M_UART78),
1942 KCLK(UART8_K, "uart8_k", usart234578_src, 0, G_UART8, M_UART78),
1943 KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
1944 KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
1945 KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
1946 KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
1947 KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
1948 KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
1949 KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
1950 KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
1951 KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO),
1952 KCLK(ETHCK_K, "ethck_k", eth_src, 0, G_ETHCK, M_ETHCK),
1953
1954 /* Particulary Kernel Clocks (no mux or no gate) */
1955 MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM),
1956 MGATE_MP1(DSI_PX, "dsi_px", "pll4_q", CLK_SET_RATE_PARENT, G_DSI),
1957 MGATE_MP1(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT, G_LTDC),
1958 MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
1959 MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
1960
1961 COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
1962 CLK_SET_RATE_NO_REPARENT,
1963 _NO_GATE,
1964 _MMUX(M_ETHCK),
1965 _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
1966
1967 /* RTC clock */
1968 DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
1969
1970 COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
1971 CLK_SET_RATE_PARENT,
1972 _GATE(RCC_BDCR, 20, 0),
1973 _MUX(RCC_BDCR, 16, 2, 0),
1974 _NO_DIV),
1975
1976 /* MCO clocks */
1977 COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
1978 CLK_SET_RATE_NO_REPARENT,
1979 _GATE(RCC_MCO1CFGR, 12, 0),
1980 _MUX(RCC_MCO1CFGR, 0, 3, 0),
1981 _DIV(RCC_MCO1CFGR, 4, 4, 0, NULL)),
1982
1983 COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
1984 CLK_SET_RATE_NO_REPARENT,
1985 _GATE(RCC_MCO2CFGR, 12, 0),
1986 _MUX(RCC_MCO2CFGR, 0, 3, 0),
1987 _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
1988
1989 /* Debug clocks */
1990 GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
1991 RCC_DBGCFGR, 8, 0),
1992
1993 COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
1994 _GATE(RCC_DBGCFGR, 9, 0),
1995 _NO_MUX,
1996 _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
1997 };
1998
1999 struct stm32_clock_match_data {
2000 const struct clock_config *cfg;
2001 unsigned int num;
2002 unsigned int maxbinding;
2003 };
2004
2005 static struct stm32_clock_match_data stm32mp1_data = {
2006 .cfg = stm32mp1_clock_cfg,
2007 .num = ARRAY_SIZE(stm32mp1_clock_cfg),
2008 .maxbinding = STM32MP1_LAST_CLK,
2009 };
2010
2011 static const struct of_device_id stm32mp1_match_data[] = {
2012 {
2013 .compatible = "st,stm32mp1-rcc",
2014 .data = &stm32mp1_data,
2015 },
2016 { }
2017 };
2018
stm32_register_hw_clk(struct device * dev,struct clk_hw_onecell_data * clk_data,void __iomem * base,spinlock_t * lock,const struct clock_config * cfg)2019 static int stm32_register_hw_clk(struct device *dev,
2020 struct clk_hw_onecell_data *clk_data,
2021 void __iomem *base, spinlock_t *lock,
2022 const struct clock_config *cfg)
2023 {
2024 struct clk_hw **hws;
2025 struct clk_hw *hw = ERR_PTR(-ENOENT);
2026
2027 hws = clk_data->hws;
2028
2029 if (cfg->func)
2030 hw = (*cfg->func)(dev, clk_data, base, lock, cfg);
2031
2032 if (IS_ERR(hw)) {
2033 pr_err("Unable to register %s\n", cfg->name);
2034 return PTR_ERR(hw);
2035 }
2036
2037 if (cfg->id != NO_ID)
2038 hws[cfg->id] = hw;
2039
2040 return 0;
2041 }
2042
stm32_rcc_init(struct device_node * np,void __iomem * base,const struct of_device_id * match_data)2043 static int stm32_rcc_init(struct device_node *np,
2044 void __iomem *base,
2045 const struct of_device_id *match_data)
2046 {
2047 struct clk_hw_onecell_data *clk_data;
2048 struct clk_hw **hws;
2049 const struct of_device_id *match;
2050 const struct stm32_clock_match_data *data;
2051 int err, n, max_binding;
2052
2053 match = of_match_node(match_data, np);
2054 if (!match) {
2055 pr_err("%s: match data not found\n", __func__);
2056 return -ENODEV;
2057 }
2058
2059 data = match->data;
2060
2061 max_binding = data->maxbinding;
2062
2063 clk_data = kzalloc(struct_size(clk_data, hws, max_binding),
2064 GFP_KERNEL);
2065 if (!clk_data)
2066 return -ENOMEM;
2067
2068 clk_data->num = max_binding;
2069
2070 hws = clk_data->hws;
2071
2072 for (n = 0; n < max_binding; n++)
2073 hws[n] = ERR_PTR(-ENOENT);
2074
2075 for (n = 0; n < data->num; n++) {
2076 err = stm32_register_hw_clk(NULL, clk_data, base, &rlock,
2077 &data->cfg[n]);
2078 if (err) {
2079 pr_err("%s: can't register %s\n", __func__,
2080 data->cfg[n].name);
2081
2082 kfree(clk_data);
2083
2084 return err;
2085 }
2086 }
2087
2088 return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
2089 }
2090
stm32mp1_rcc_init(struct device_node * np)2091 static void stm32mp1_rcc_init(struct device_node *np)
2092 {
2093 void __iomem *base;
2094
2095 base = of_iomap(np, 0);
2096 if (!base) {
2097 pr_err("%pOFn: unable to map resource", np);
2098 of_node_put(np);
2099 return;
2100 }
2101
2102 if (stm32_rcc_init(np, base, stm32mp1_match_data)) {
2103 iounmap(base);
2104 of_node_put(np);
2105 }
2106 }
2107
2108 CLK_OF_DECLARE_DRIVER(stm32mp1_rcc, "st,stm32mp1-rcc", stm32mp1_rcc_init);
2109
