1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <linux/msi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32 #include <linux/libata.h>
33 #include <linux/ahci-remap.h>
34 #include <linux/io-64-nonatomic-lo-hi.h>
35 #include "ahci.h"
36
37 #define DRV_NAME "ahci"
38 #define DRV_VERSION "3.0"
39
40 enum {
41 AHCI_PCI_BAR_STA2X11 = 0,
42 AHCI_PCI_BAR_CAVIUM = 0,
43 AHCI_PCI_BAR_LOONGSON = 0,
44 AHCI_PCI_BAR_ENMOTUS = 2,
45 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
46 AHCI_PCI_BAR_STANDARD = 5,
47 };
48
49 enum board_ids {
50 /* board IDs by feature in alphabetical order */
51 board_ahci,
52 board_ahci_ign_iferr,
53 board_ahci_mobile,
54 board_ahci_nomsi,
55 board_ahci_noncq,
56 board_ahci_nosntf,
57 board_ahci_yes_fbs,
58
59 /* board IDs for specific chipsets in alphabetical order */
60 board_ahci_al,
61 board_ahci_avn,
62 board_ahci_mcp65,
63 board_ahci_mcp77,
64 board_ahci_mcp89,
65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700, /* for SB700 and SB800 */
68 board_ahci_vt8251,
69
70 /*
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
73 */
74 board_ahci_pcs7,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81 };
82
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static void ahci_remove_one(struct pci_dev *dev);
85 static void ahci_shutdown_one(struct pci_dev *dev);
86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91 static bool is_mcp89_apple(struct pci_dev *pdev);
92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94 #ifdef CONFIG_PM
95 static int ahci_pci_device_runtime_suspend(struct device *dev);
96 static int ahci_pci_device_runtime_resume(struct device *dev);
97 #ifdef CONFIG_PM_SLEEP
98 static int ahci_pci_device_suspend(struct device *dev);
99 static int ahci_pci_device_resume(struct device *dev);
100 #endif
101 #endif /* CONFIG_PM */
102
103 static struct scsi_host_template ahci_sht = {
104 AHCI_SHT("ahci"),
105 };
106
107 static struct ata_port_operations ahci_vt8251_ops = {
108 .inherits = &ahci_ops,
109 .hardreset = ahci_vt8251_hardreset,
110 };
111
112 static struct ata_port_operations ahci_p5wdh_ops = {
113 .inherits = &ahci_ops,
114 .hardreset = ahci_p5wdh_hardreset,
115 };
116
117 static struct ata_port_operations ahci_avn_ops = {
118 .inherits = &ahci_ops,
119 .hardreset = ahci_avn_hardreset,
120 };
121
122 static const struct ata_port_info ahci_port_info[] = {
123 /* by features */
124 [board_ahci] = {
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
129 },
130 [board_ahci_ign_iferr] = {
131 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
137 [board_ahci_mobile] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 [board_ahci_nomsi] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_noncq] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_nosntf] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_yes_fbs] = {
166 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
172 /* by chipsets */
173 [board_ahci_al] = {
174 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
186 [board_ahci_mcp65] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
194 [board_ahci_mcp77] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
201 [board_ahci_mcp89] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_mv] = {
209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
216 [board_ahci_sb600] = {
217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
224 },
225 [board_ahci_sb700] = { /* for SB700 and SB800 */
226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_pmp_retry_srst_ops,
231 },
232 [board_ahci_vt8251] = {
233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &ahci_vt8251_ops,
238 },
239 [board_ahci_pcs7] = {
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_ops,
244 },
245 };
246
247 static const struct pci_device_id ahci_pci_tbl[] = {
248 /* Intel */
249 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
250 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
251 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
252 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
253 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
254 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
255 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
256 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
257 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
258 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
259 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
260 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
261 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
262 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
263 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
264 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
265 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
266 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
267 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
268 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
269 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
270 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
271 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
272 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
273 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
274 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
275 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
276 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
277 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
278 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
279 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
280 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
281 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
282 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
283 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
284 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
285 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
286 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
287 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
288 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
289 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
290 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
311 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
312 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
313 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
314 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
315 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
316 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
317 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
318 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
319 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
320 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
321 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
322 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
323 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
324 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
325 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
326 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
327 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
328 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
329 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
330 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
331 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
332 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
333 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
334 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
335 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
336 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
337 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
339 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
343 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
344 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
345 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
346 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
347 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
348 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
349 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
350 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
351 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
352 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
353 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
355 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
362 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
363 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
364 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
365 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
366 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
367 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
368 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
369 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
372 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
373 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
374 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
375 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
376 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
377 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
378 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
379 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
380 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
381 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
382 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
383 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
384 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
385 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
386 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
387 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
388 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
389 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
390 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
391 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
392 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
393 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
394 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
395 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
396 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
397 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
398 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
399 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
400 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
401 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
402 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
403 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
405 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
406 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
407 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
410 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
411 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
412 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
413 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
414 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
415 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
416 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
417 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */
418 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */
419
420 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
421 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
422 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
423 /* JMicron 362B and 362C have an AHCI function with IDE class code */
424 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
425 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
426 /* May need to update quirk_jmicron_async_suspend() for additions */
427
428 /* ATI */
429 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
430 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
435 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
436
437 /* Amazon's Annapurna Labs support */
438 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
439 .class = PCI_CLASS_STORAGE_SATA_AHCI,
440 .class_mask = 0xffffff,
441 board_ahci_al },
442 /* AMD */
443 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
444 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
445 /* AMD is using RAID class only for ahci controllers */
446 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
447 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
448
449 /* VIA */
450 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
451 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
452
453 /* NVIDIA */
454 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
456 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
457 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
458 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
459 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
460 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
461 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
462 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
472 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
475 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
476 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
483 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
484 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
485 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
486 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
487 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
488 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
489 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
490 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
491 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
498 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
499 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
500 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
503 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
510 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
511 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
512 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
515 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
522 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
523 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
524 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
527 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
528 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
529 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
530 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
531 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
532 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
533 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
534 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
535 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
536 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
537 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
538
539 /* SiS */
540 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
541 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
542 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
543
544 /* ST Microelectronics */
545 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
546
547 /* Marvell */
548 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
549 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
550 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
551 .class = PCI_CLASS_STORAGE_SATA_AHCI,
552 .class_mask = 0xffffff,
553 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
554 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
555 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
556 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
557 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
558 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
560 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
562 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
564 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
566 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
568 .driver_data = board_ahci_yes_fbs },
569 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
570 .driver_data = board_ahci_yes_fbs },
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
572 .driver_data = board_ahci_yes_fbs },
573 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
574 .driver_data = board_ahci_yes_fbs },
575 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
576 .driver_data = board_ahci_yes_fbs },
577 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
578 .driver_data = board_ahci_yes_fbs },
579
580 /* Promise */
581 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
582 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
583
584 /* Asmedia */
585 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
586 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
587 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
588 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
589 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
590 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
591
592 /*
593 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
594 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
595 */
596 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
597 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
598
599 /* Enmotus */
600 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
601
602 /* Loongson */
603 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
604
605 /* Generic, PCI class code for AHCI */
606 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
607 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
608
609 { } /* terminate list */
610 };
611
612 static const struct dev_pm_ops ahci_pci_pm_ops = {
613 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
614 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
615 ahci_pci_device_runtime_resume, NULL)
616 };
617
618 static struct pci_driver ahci_pci_driver = {
619 .name = DRV_NAME,
620 .id_table = ahci_pci_tbl,
621 .probe = ahci_init_one,
622 .remove = ahci_remove_one,
623 .shutdown = ahci_shutdown_one,
624 .driver = {
625 .pm = &ahci_pci_pm_ops,
626 },
627 };
628
629 #if IS_ENABLED(CONFIG_PATA_MARVELL)
630 static int marvell_enable;
631 #else
632 static int marvell_enable = 1;
633 #endif
634 module_param(marvell_enable, int, 0644);
635 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
636
637 static int mobile_lpm_policy = -1;
638 module_param(mobile_lpm_policy, int, 0644);
639 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
640
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)641 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
642 struct ahci_host_priv *hpriv)
643 {
644 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
645 dev_info(&pdev->dev, "JMB361 has only one port\n");
646 hpriv->force_port_map = 1;
647 }
648
649 /*
650 * Temporary Marvell 6145 hack: PATA port presence
651 * is asserted through the standard AHCI port
652 * presence register, as bit 4 (counting from 0)
653 */
654 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
655 if (pdev->device == 0x6121)
656 hpriv->mask_port_map = 0x3;
657 else
658 hpriv->mask_port_map = 0xf;
659 dev_info(&pdev->dev,
660 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
661 }
662
663 ahci_save_initial_config(&pdev->dev, hpriv);
664 }
665
ahci_pci_init_controller(struct ata_host * host)666 static void ahci_pci_init_controller(struct ata_host *host)
667 {
668 struct ahci_host_priv *hpriv = host->private_data;
669 struct pci_dev *pdev = to_pci_dev(host->dev);
670 void __iomem *port_mmio;
671 u32 tmp;
672 int mv;
673
674 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
675 if (pdev->device == 0x6121)
676 mv = 2;
677 else
678 mv = 4;
679 port_mmio = __ahci_port_base(host, mv);
680
681 writel(0, port_mmio + PORT_IRQ_MASK);
682
683 /* clear port IRQ */
684 tmp = readl(port_mmio + PORT_IRQ_STAT);
685 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
686 if (tmp)
687 writel(tmp, port_mmio + PORT_IRQ_STAT);
688 }
689
690 ahci_init_controller(host);
691 }
692
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)693 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
694 unsigned long deadline)
695 {
696 struct ata_port *ap = link->ap;
697 struct ahci_host_priv *hpriv = ap->host->private_data;
698 bool online;
699 int rc;
700
701 DPRINTK("ENTER\n");
702
703 hpriv->stop_engine(ap);
704
705 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
706 deadline, &online, NULL);
707
708 hpriv->start_engine(ap);
709
710 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
711
712 /* vt8251 doesn't clear BSY on signature FIS reception,
713 * request follow-up softreset.
714 */
715 return online ? -EAGAIN : rc;
716 }
717
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)718 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
719 unsigned long deadline)
720 {
721 struct ata_port *ap = link->ap;
722 struct ahci_port_priv *pp = ap->private_data;
723 struct ahci_host_priv *hpriv = ap->host->private_data;
724 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
725 struct ata_taskfile tf;
726 bool online;
727 int rc;
728
729 hpriv->stop_engine(ap);
730
731 /* clear D2H reception area to properly wait for D2H FIS */
732 ata_tf_init(link->device, &tf);
733 tf.command = ATA_BUSY;
734 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
735
736 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
737 deadline, &online, NULL);
738
739 hpriv->start_engine(ap);
740
741 /* The pseudo configuration device on SIMG4726 attached to
742 * ASUS P5W-DH Deluxe doesn't send signature FIS after
743 * hardreset if no device is attached to the first downstream
744 * port && the pseudo device locks up on SRST w/ PMP==0. To
745 * work around this, wait for !BSY only briefly. If BSY isn't
746 * cleared, perform CLO and proceed to IDENTIFY (achieved by
747 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
748 *
749 * Wait for two seconds. Devices attached to downstream port
750 * which can't process the following IDENTIFY after this will
751 * have to be reset again. For most cases, this should
752 * suffice while making probing snappish enough.
753 */
754 if (online) {
755 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
756 ahci_check_ready);
757 if (rc)
758 ahci_kick_engine(ap);
759 }
760 return rc;
761 }
762
763 /*
764 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
765 *
766 * It has been observed with some SSDs that the timing of events in the
767 * link synchronization phase can leave the port in a state that can not
768 * be recovered by a SATA-hard-reset alone. The failing signature is
769 * SStatus.DET stuck at 1 ("Device presence detected but Phy
770 * communication not established"). It was found that unloading and
771 * reloading the driver when this problem occurs allows the drive
772 * connection to be recovered (DET advanced to 0x3). The critical
773 * component of reloading the driver is that the port state machines are
774 * reset by bouncing "port enable" in the AHCI PCS configuration
775 * register. So, reproduce that effect by bouncing a port whenever we
776 * see DET==1 after a reset.
777 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)778 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
779 unsigned long deadline)
780 {
781 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
782 struct ata_port *ap = link->ap;
783 struct ahci_port_priv *pp = ap->private_data;
784 struct ahci_host_priv *hpriv = ap->host->private_data;
785 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
786 unsigned long tmo = deadline - jiffies;
787 struct ata_taskfile tf;
788 bool online;
789 int rc, i;
790
791 DPRINTK("ENTER\n");
792
793 hpriv->stop_engine(ap);
794
795 for (i = 0; i < 2; i++) {
796 u16 val;
797 u32 sstatus;
798 int port = ap->port_no;
799 struct ata_host *host = ap->host;
800 struct pci_dev *pdev = to_pci_dev(host->dev);
801
802 /* clear D2H reception area to properly wait for D2H FIS */
803 ata_tf_init(link->device, &tf);
804 tf.command = ATA_BUSY;
805 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
806
807 rc = sata_link_hardreset(link, timing, deadline, &online,
808 ahci_check_ready);
809
810 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
811 (sstatus & 0xf) != 1)
812 break;
813
814 ata_link_info(link, "avn bounce port%d\n", port);
815
816 pci_read_config_word(pdev, 0x92, &val);
817 val &= ~(1 << port);
818 pci_write_config_word(pdev, 0x92, val);
819 ata_msleep(ap, 1000);
820 val |= 1 << port;
821 pci_write_config_word(pdev, 0x92, val);
822 deadline += tmo;
823 }
824
825 hpriv->start_engine(ap);
826
827 if (online)
828 *class = ahci_dev_classify(ap);
829
830 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
831 return rc;
832 }
833
834
835 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)836 static void ahci_pci_disable_interrupts(struct ata_host *host)
837 {
838 struct ahci_host_priv *hpriv = host->private_data;
839 void __iomem *mmio = hpriv->mmio;
840 u32 ctl;
841
842 /* AHCI spec rev1.1 section 8.3.3:
843 * Software must disable interrupts prior to requesting a
844 * transition of the HBA to D3 state.
845 */
846 ctl = readl(mmio + HOST_CTL);
847 ctl &= ~HOST_IRQ_EN;
848 writel(ctl, mmio + HOST_CTL);
849 readl(mmio + HOST_CTL); /* flush */
850 }
851
ahci_pci_device_runtime_suspend(struct device * dev)852 static int ahci_pci_device_runtime_suspend(struct device *dev)
853 {
854 struct pci_dev *pdev = to_pci_dev(dev);
855 struct ata_host *host = pci_get_drvdata(pdev);
856
857 ahci_pci_disable_interrupts(host);
858 return 0;
859 }
860
ahci_pci_device_runtime_resume(struct device * dev)861 static int ahci_pci_device_runtime_resume(struct device *dev)
862 {
863 struct pci_dev *pdev = to_pci_dev(dev);
864 struct ata_host *host = pci_get_drvdata(pdev);
865 int rc;
866
867 rc = ahci_reset_controller(host);
868 if (rc)
869 return rc;
870 ahci_pci_init_controller(host);
871 return 0;
872 }
873
874 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)875 static int ahci_pci_device_suspend(struct device *dev)
876 {
877 struct pci_dev *pdev = to_pci_dev(dev);
878 struct ata_host *host = pci_get_drvdata(pdev);
879 struct ahci_host_priv *hpriv = host->private_data;
880
881 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
882 dev_err(&pdev->dev,
883 "BIOS update required for suspend/resume\n");
884 return -EIO;
885 }
886
887 ahci_pci_disable_interrupts(host);
888 return ata_host_suspend(host, PMSG_SUSPEND);
889 }
890
ahci_pci_device_resume(struct device * dev)891 static int ahci_pci_device_resume(struct device *dev)
892 {
893 struct pci_dev *pdev = to_pci_dev(dev);
894 struct ata_host *host = pci_get_drvdata(pdev);
895 int rc;
896
897 /* Apple BIOS helpfully mangles the registers on resume */
898 if (is_mcp89_apple(pdev))
899 ahci_mcp89_apple_enable(pdev);
900
901 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
902 rc = ahci_reset_controller(host);
903 if (rc)
904 return rc;
905
906 ahci_pci_init_controller(host);
907 }
908
909 ata_host_resume(host);
910
911 return 0;
912 }
913 #endif
914
915 #endif /* CONFIG_PM */
916
ahci_configure_dma_masks(struct pci_dev * pdev,int using_dac)917 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
918 {
919 const int dma_bits = using_dac ? 64 : 32;
920 int rc;
921
922 /*
923 * If the device fixup already set the dma_mask to some non-standard
924 * value, don't extend it here. This happens on STA2X11, for example.
925 *
926 * XXX: manipulating the DMA mask from platform code is completely
927 * bogus, platform code should use dev->bus_dma_limit instead..
928 */
929 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
930 return 0;
931
932 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
933 if (rc)
934 dev_err(&pdev->dev, "DMA enable failed\n");
935 return rc;
936 }
937
ahci_pci_print_info(struct ata_host * host)938 static void ahci_pci_print_info(struct ata_host *host)
939 {
940 struct pci_dev *pdev = to_pci_dev(host->dev);
941 u16 cc;
942 const char *scc_s;
943
944 pci_read_config_word(pdev, 0x0a, &cc);
945 if (cc == PCI_CLASS_STORAGE_IDE)
946 scc_s = "IDE";
947 else if (cc == PCI_CLASS_STORAGE_SATA)
948 scc_s = "SATA";
949 else if (cc == PCI_CLASS_STORAGE_RAID)
950 scc_s = "RAID";
951 else
952 scc_s = "unknown";
953
954 ahci_print_info(host, scc_s);
955 }
956
957 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
958 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
959 * support PMP and the 4726 either directly exports the device
960 * attached to the first downstream port or acts as a hardware storage
961 * controller and emulate a single ATA device (can be RAID 0/1 or some
962 * other configuration).
963 *
964 * When there's no device attached to the first downstream port of the
965 * 4726, "Config Disk" appears, which is a pseudo ATA device to
966 * configure the 4726. However, ATA emulation of the device is very
967 * lame. It doesn't send signature D2H Reg FIS after the initial
968 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
969 *
970 * The following function works around the problem by always using
971 * hardreset on the port and not depending on receiving signature FIS
972 * afterward. If signature FIS isn't received soon, ATA class is
973 * assumed without follow-up softreset.
974 */
ahci_p5wdh_workaround(struct ata_host * host)975 static void ahci_p5wdh_workaround(struct ata_host *host)
976 {
977 static const struct dmi_system_id sysids[] = {
978 {
979 .ident = "P5W DH Deluxe",
980 .matches = {
981 DMI_MATCH(DMI_SYS_VENDOR,
982 "ASUSTEK COMPUTER INC"),
983 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
984 },
985 },
986 { }
987 };
988 struct pci_dev *pdev = to_pci_dev(host->dev);
989
990 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
991 dmi_check_system(sysids)) {
992 struct ata_port *ap = host->ports[1];
993
994 dev_info(&pdev->dev,
995 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
996
997 ap->ops = &ahci_p5wdh_ops;
998 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
999 }
1000 }
1001
1002 /*
1003 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1004 * booting in BIOS compatibility mode. We restore the registers but not ID.
1005 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)1006 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1007 {
1008 u32 val;
1009
1010 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1011
1012 pci_read_config_dword(pdev, 0xf8, &val);
1013 val |= 1 << 0x1b;
1014 /* the following changes the device ID, but appears not to affect function */
1015 /* val = (val & ~0xf0000000) | 0x80000000; */
1016 pci_write_config_dword(pdev, 0xf8, val);
1017
1018 pci_read_config_dword(pdev, 0x54c, &val);
1019 val |= 1 << 0xc;
1020 pci_write_config_dword(pdev, 0x54c, val);
1021
1022 pci_read_config_dword(pdev, 0x4a4, &val);
1023 val &= 0xff;
1024 val |= 0x01060100;
1025 pci_write_config_dword(pdev, 0x4a4, val);
1026
1027 pci_read_config_dword(pdev, 0x54c, &val);
1028 val &= ~(1 << 0xc);
1029 pci_write_config_dword(pdev, 0x54c, val);
1030
1031 pci_read_config_dword(pdev, 0xf8, &val);
1032 val &= ~(1 << 0x1b);
1033 pci_write_config_dword(pdev, 0xf8, val);
1034 }
1035
is_mcp89_apple(struct pci_dev * pdev)1036 static bool is_mcp89_apple(struct pci_dev *pdev)
1037 {
1038 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1039 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1040 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1041 pdev->subsystem_device == 0xcb89;
1042 }
1043
1044 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1045 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1046 {
1047 static const struct dmi_system_id sysids[] = {
1048 /*
1049 * The oldest version known to be broken is 0901 and
1050 * working is 1501 which was released on 2007-10-26.
1051 * Enable 64bit DMA on 1501 and anything newer.
1052 *
1053 * Please read bko#9412 for more info.
1054 */
1055 {
1056 .ident = "ASUS M2A-VM",
1057 .matches = {
1058 DMI_MATCH(DMI_BOARD_VENDOR,
1059 "ASUSTeK Computer INC."),
1060 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1061 },
1062 .driver_data = "20071026", /* yyyymmdd */
1063 },
1064 /*
1065 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1066 * support 64bit DMA.
1067 *
1068 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1069 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1070 * This spelling mistake was fixed in BIOS version 1.5, so
1071 * 1.5 and later have the Manufacturer as
1072 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1073 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1074 *
1075 * BIOS versions earlier than 1.9 had a Board Product Name
1076 * DMI field of "MS-7376". This was changed to be
1077 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1078 * match on DMI_BOARD_NAME of "MS-7376".
1079 */
1080 {
1081 .ident = "MSI K9A2 Platinum",
1082 .matches = {
1083 DMI_MATCH(DMI_BOARD_VENDOR,
1084 "MICRO-STAR INTER"),
1085 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1086 },
1087 },
1088 /*
1089 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1090 * 64bit DMA.
1091 *
1092 * This board also had the typo mentioned above in the
1093 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1094 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1095 */
1096 {
1097 .ident = "MSI K9AGM2",
1098 .matches = {
1099 DMI_MATCH(DMI_BOARD_VENDOR,
1100 "MICRO-STAR INTER"),
1101 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1102 },
1103 },
1104 /*
1105 * All BIOS versions for the Asus M3A support 64bit DMA.
1106 * (all release versions from 0301 to 1206 were tested)
1107 */
1108 {
1109 .ident = "ASUS M3A",
1110 .matches = {
1111 DMI_MATCH(DMI_BOARD_VENDOR,
1112 "ASUSTeK Computer INC."),
1113 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1114 },
1115 },
1116 { }
1117 };
1118 const struct dmi_system_id *match;
1119 int year, month, date;
1120 char buf[9];
1121
1122 match = dmi_first_match(sysids);
1123 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1124 !match)
1125 return false;
1126
1127 if (!match->driver_data)
1128 goto enable_64bit;
1129
1130 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1131 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1132
1133 if (strcmp(buf, match->driver_data) >= 0)
1134 goto enable_64bit;
1135 else {
1136 dev_warn(&pdev->dev,
1137 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1138 match->ident);
1139 return false;
1140 }
1141
1142 enable_64bit:
1143 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1144 return true;
1145 }
1146
ahci_broken_system_poweroff(struct pci_dev * pdev)1147 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1148 {
1149 static const struct dmi_system_id broken_systems[] = {
1150 {
1151 .ident = "HP Compaq nx6310",
1152 .matches = {
1153 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1154 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1155 },
1156 /* PCI slot number of the controller */
1157 .driver_data = (void *)0x1FUL,
1158 },
1159 {
1160 .ident = "HP Compaq 6720s",
1161 .matches = {
1162 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1163 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1164 },
1165 /* PCI slot number of the controller */
1166 .driver_data = (void *)0x1FUL,
1167 },
1168
1169 { } /* terminate list */
1170 };
1171 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1172
1173 if (dmi) {
1174 unsigned long slot = (unsigned long)dmi->driver_data;
1175 /* apply the quirk only to on-board controllers */
1176 return slot == PCI_SLOT(pdev->devfn);
1177 }
1178
1179 return false;
1180 }
1181
ahci_broken_suspend(struct pci_dev * pdev)1182 static bool ahci_broken_suspend(struct pci_dev *pdev)
1183 {
1184 static const struct dmi_system_id sysids[] = {
1185 /*
1186 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1187 * to the harddisk doesn't become online after
1188 * resuming from STR. Warn and fail suspend.
1189 *
1190 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1191 *
1192 * Use dates instead of versions to match as HP is
1193 * apparently recycling both product and version
1194 * strings.
1195 *
1196 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1197 */
1198 {
1199 .ident = "dv4",
1200 .matches = {
1201 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1202 DMI_MATCH(DMI_PRODUCT_NAME,
1203 "HP Pavilion dv4 Notebook PC"),
1204 },
1205 .driver_data = "20090105", /* F.30 */
1206 },
1207 {
1208 .ident = "dv5",
1209 .matches = {
1210 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1211 DMI_MATCH(DMI_PRODUCT_NAME,
1212 "HP Pavilion dv5 Notebook PC"),
1213 },
1214 .driver_data = "20090506", /* F.16 */
1215 },
1216 {
1217 .ident = "dv6",
1218 .matches = {
1219 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1220 DMI_MATCH(DMI_PRODUCT_NAME,
1221 "HP Pavilion dv6 Notebook PC"),
1222 },
1223 .driver_data = "20090423", /* F.21 */
1224 },
1225 {
1226 .ident = "HDX18",
1227 .matches = {
1228 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1229 DMI_MATCH(DMI_PRODUCT_NAME,
1230 "HP HDX18 Notebook PC"),
1231 },
1232 .driver_data = "20090430", /* F.23 */
1233 },
1234 /*
1235 * Acer eMachines G725 has the same problem. BIOS
1236 * V1.03 is known to be broken. V3.04 is known to
1237 * work. Between, there are V1.06, V2.06 and V3.03
1238 * that we don't have much idea about. For now,
1239 * blacklist anything older than V3.04.
1240 *
1241 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1242 */
1243 {
1244 .ident = "G725",
1245 .matches = {
1246 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1247 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1248 },
1249 .driver_data = "20091216", /* V3.04 */
1250 },
1251 { } /* terminate list */
1252 };
1253 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1254 int year, month, date;
1255 char buf[9];
1256
1257 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1258 return false;
1259
1260 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1261 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1262
1263 return strcmp(buf, dmi->driver_data) < 0;
1264 }
1265
ahci_broken_lpm(struct pci_dev * pdev)1266 static bool ahci_broken_lpm(struct pci_dev *pdev)
1267 {
1268 static const struct dmi_system_id sysids[] = {
1269 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1270 {
1271 .matches = {
1272 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1273 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1274 },
1275 .driver_data = "20180406", /* 1.31 */
1276 },
1277 {
1278 .matches = {
1279 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1280 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1281 },
1282 .driver_data = "20180420", /* 1.28 */
1283 },
1284 {
1285 .matches = {
1286 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1287 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1288 },
1289 .driver_data = "20180315", /* 1.33 */
1290 },
1291 {
1292 .matches = {
1293 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1294 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1295 },
1296 /*
1297 * Note date based on release notes, 2.35 has been
1298 * reported to be good, but I've been unable to get
1299 * a hold of the reporter to get the DMI BIOS date.
1300 * TODO: fix this.
1301 */
1302 .driver_data = "20180310", /* 2.35 */
1303 },
1304 { } /* terminate list */
1305 };
1306 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1307 int year, month, date;
1308 char buf[9];
1309
1310 if (!dmi)
1311 return false;
1312
1313 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1314 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1315
1316 return strcmp(buf, dmi->driver_data) < 0;
1317 }
1318
ahci_broken_online(struct pci_dev * pdev)1319 static bool ahci_broken_online(struct pci_dev *pdev)
1320 {
1321 #define ENCODE_BUSDEVFN(bus, slot, func) \
1322 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1323 static const struct dmi_system_id sysids[] = {
1324 /*
1325 * There are several gigabyte boards which use
1326 * SIMG5723s configured as hardware RAID. Certain
1327 * 5723 firmware revisions shipped there keep the link
1328 * online but fail to answer properly to SRST or
1329 * IDENTIFY when no device is attached downstream
1330 * causing libata to retry quite a few times leading
1331 * to excessive detection delay.
1332 *
1333 * As these firmwares respond to the second reset try
1334 * with invalid device signature, considering unknown
1335 * sig as offline works around the problem acceptably.
1336 */
1337 {
1338 .ident = "EP45-DQ6",
1339 .matches = {
1340 DMI_MATCH(DMI_BOARD_VENDOR,
1341 "Gigabyte Technology Co., Ltd."),
1342 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1343 },
1344 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1345 },
1346 {
1347 .ident = "EP45-DS5",
1348 .matches = {
1349 DMI_MATCH(DMI_BOARD_VENDOR,
1350 "Gigabyte Technology Co., Ltd."),
1351 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1352 },
1353 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1354 },
1355 { } /* terminate list */
1356 };
1357 #undef ENCODE_BUSDEVFN
1358 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1359 unsigned int val;
1360
1361 if (!dmi)
1362 return false;
1363
1364 val = (unsigned long)dmi->driver_data;
1365
1366 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1367 }
1368
ahci_broken_devslp(struct pci_dev * pdev)1369 static bool ahci_broken_devslp(struct pci_dev *pdev)
1370 {
1371 /* device with broken DEVSLP but still showing SDS capability */
1372 static const struct pci_device_id ids[] = {
1373 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1374 {}
1375 };
1376
1377 return pci_match_id(ids, pdev);
1378 }
1379
1380 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1381 static void ahci_gtf_filter_workaround(struct ata_host *host)
1382 {
1383 static const struct dmi_system_id sysids[] = {
1384 /*
1385 * Aspire 3810T issues a bunch of SATA enable commands
1386 * via _GTF including an invalid one and one which is
1387 * rejected by the device. Among the successful ones
1388 * is FPDMA non-zero offset enable which when enabled
1389 * only on the drive side leads to NCQ command
1390 * failures. Filter it out.
1391 */
1392 {
1393 .ident = "Aspire 3810T",
1394 .matches = {
1395 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1396 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1397 },
1398 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1399 },
1400 { }
1401 };
1402 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1403 unsigned int filter;
1404 int i;
1405
1406 if (!dmi)
1407 return;
1408
1409 filter = (unsigned long)dmi->driver_data;
1410 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1411 filter, dmi->ident);
1412
1413 for (i = 0; i < host->n_ports; i++) {
1414 struct ata_port *ap = host->ports[i];
1415 struct ata_link *link;
1416 struct ata_device *dev;
1417
1418 ata_for_each_link(link, ap, EDGE)
1419 ata_for_each_dev(dev, link, ALL)
1420 dev->gtf_filter |= filter;
1421 }
1422 }
1423 #else
ahci_gtf_filter_workaround(struct ata_host * host)1424 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1425 {}
1426 #endif
1427
1428 /*
1429 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1430 * as DUMMY, or detected but eventually get a "link down" and never get up
1431 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1432 * port_map may hold a value of 0x00.
1433 *
1434 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1435 * and can significantly reduce the occurrence of the problem.
1436 *
1437 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1438 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)1439 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1440 struct pci_dev *pdev)
1441 {
1442 static const struct dmi_system_id sysids[] = {
1443 {
1444 .ident = "Acer Switch Alpha 12",
1445 .matches = {
1446 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1447 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1448 },
1449 },
1450 { }
1451 };
1452
1453 if (dmi_check_system(sysids)) {
1454 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1455 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1456 hpriv->port_map = 0x7;
1457 hpriv->cap = 0xC734FF02;
1458 }
1459 }
1460 }
1461
1462 #ifdef CONFIG_ARM64
1463 /*
1464 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1465 * Workaround is to make sure all pending IRQs are served before leaving
1466 * handler.
1467 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)1468 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1469 {
1470 struct ata_host *host = dev_instance;
1471 struct ahci_host_priv *hpriv;
1472 unsigned int rc = 0;
1473 void __iomem *mmio;
1474 u32 irq_stat, irq_masked;
1475 unsigned int handled = 1;
1476
1477 VPRINTK("ENTER\n");
1478 hpriv = host->private_data;
1479 mmio = hpriv->mmio;
1480 irq_stat = readl(mmio + HOST_IRQ_STAT);
1481 if (!irq_stat)
1482 return IRQ_NONE;
1483
1484 do {
1485 irq_masked = irq_stat & hpriv->port_map;
1486 spin_lock(&host->lock);
1487 rc = ahci_handle_port_intr(host, irq_masked);
1488 if (!rc)
1489 handled = 0;
1490 writel(irq_stat, mmio + HOST_IRQ_STAT);
1491 irq_stat = readl(mmio + HOST_IRQ_STAT);
1492 spin_unlock(&host->lock);
1493 } while (irq_stat);
1494 VPRINTK("EXIT\n");
1495
1496 return IRQ_RETVAL(handled);
1497 }
1498 #endif
1499
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)1500 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1501 struct ahci_host_priv *hpriv)
1502 {
1503 int i;
1504 u32 cap;
1505
1506 /*
1507 * Check if this device might have remapped nvme devices.
1508 */
1509 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1510 pci_resource_len(pdev, bar) < SZ_512K ||
1511 bar != AHCI_PCI_BAR_STANDARD ||
1512 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1513 return;
1514
1515 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1516 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1517 if ((cap & (1 << i)) == 0)
1518 continue;
1519 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1520 != PCI_CLASS_STORAGE_EXPRESS)
1521 continue;
1522
1523 /* We've found a remapped device */
1524 hpriv->remapped_nvme++;
1525 }
1526
1527 if (!hpriv->remapped_nvme)
1528 return;
1529
1530 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1531 hpriv->remapped_nvme);
1532 dev_warn(&pdev->dev,
1533 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1534
1535 /*
1536 * Don't rely on the msi-x capability in the remap case,
1537 * share the legacy interrupt across ahci and remapped devices.
1538 */
1539 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1540 }
1541
ahci_get_irq_vector(struct ata_host * host,int port)1542 static int ahci_get_irq_vector(struct ata_host *host, int port)
1543 {
1544 return pci_irq_vector(to_pci_dev(host->dev), port);
1545 }
1546
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1547 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1548 struct ahci_host_priv *hpriv)
1549 {
1550 int nvec;
1551
1552 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1553 return -ENODEV;
1554
1555 /*
1556 * If number of MSIs is less than number of ports then Sharing Last
1557 * Message mode could be enforced. In this case assume that advantage
1558 * of multipe MSIs is negated and use single MSI mode instead.
1559 */
1560 if (n_ports > 1) {
1561 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1562 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1563 if (nvec > 0) {
1564 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1565 hpriv->get_irq_vector = ahci_get_irq_vector;
1566 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1567 return nvec;
1568 }
1569
1570 /*
1571 * Fallback to single MSI mode if the controller
1572 * enforced MRSM mode.
1573 */
1574 printk(KERN_INFO
1575 "ahci: MRSM is on, fallback to single MSI\n");
1576 pci_free_irq_vectors(pdev);
1577 }
1578 }
1579
1580 /*
1581 * If the host is not capable of supporting per-port vectors, fall
1582 * back to single MSI before finally attempting single MSI-X.
1583 */
1584 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1585 if (nvec == 1)
1586 return nvec;
1587 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1588 }
1589
ahci_update_initial_lpm_policy(struct ata_port * ap,struct ahci_host_priv * hpriv)1590 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1591 struct ahci_host_priv *hpriv)
1592 {
1593 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1594
1595
1596 /* Ignore processing for non mobile platforms */
1597 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1598 return;
1599
1600 /* user modified policy via module param */
1601 if (mobile_lpm_policy != -1) {
1602 policy = mobile_lpm_policy;
1603 goto update_policy;
1604 }
1605
1606 #ifdef CONFIG_ACPI
1607 if (policy > ATA_LPM_MED_POWER &&
1608 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1609 if (hpriv->cap & HOST_CAP_PART)
1610 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1611 else if (hpriv->cap & HOST_CAP_SSC)
1612 policy = ATA_LPM_MIN_POWER;
1613 }
1614 #endif
1615
1616 update_policy:
1617 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1618 ap->target_lpm_policy = policy;
1619 }
1620
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1621 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1622 {
1623 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1624 u16 tmp16;
1625
1626 /*
1627 * Only apply the 6-port PCS quirk for known legacy platforms.
1628 */
1629 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1630 return;
1631
1632 /* Skip applying the quirk on Denverton and beyond */
1633 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1634 return;
1635
1636 /*
1637 * port_map is determined from PORTS_IMPL PCI register which is
1638 * implemented as write or write-once register. If the register
1639 * isn't programmed, ahci automatically generates it from number
1640 * of ports, which is good enough for PCS programming. It is
1641 * otherwise expected that platform firmware enables the ports
1642 * before the OS boots.
1643 */
1644 pci_read_config_word(pdev, PCS_6, &tmp16);
1645 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1646 tmp16 |= hpriv->port_map;
1647 pci_write_config_word(pdev, PCS_6, tmp16);
1648 }
1649 }
1650
remapped_nvme_show(struct device * dev,struct device_attribute * attr,char * buf)1651 static ssize_t remapped_nvme_show(struct device *dev,
1652 struct device_attribute *attr,
1653 char *buf)
1654 {
1655 struct ata_host *host = dev_get_drvdata(dev);
1656 struct ahci_host_priv *hpriv = host->private_data;
1657
1658 return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1659 }
1660
1661 static DEVICE_ATTR_RO(remapped_nvme);
1662
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1663 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1664 {
1665 unsigned int board_id = ent->driver_data;
1666 struct ata_port_info pi = ahci_port_info[board_id];
1667 const struct ata_port_info *ppi[] = { &pi, NULL };
1668 struct device *dev = &pdev->dev;
1669 struct ahci_host_priv *hpriv;
1670 struct ata_host *host;
1671 int n_ports, i, rc;
1672 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1673
1674 VPRINTK("ENTER\n");
1675
1676 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1677
1678 ata_print_version_once(&pdev->dev, DRV_VERSION);
1679
1680 /* The AHCI driver can only drive the SATA ports, the PATA driver
1681 can drive them all so if both drivers are selected make sure
1682 AHCI stays out of the way */
1683 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1684 return -ENODEV;
1685
1686 /* Apple BIOS on MCP89 prevents us using AHCI */
1687 if (is_mcp89_apple(pdev))
1688 ahci_mcp89_apple_enable(pdev);
1689
1690 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1691 * At the moment, we can only use the AHCI mode. Let the users know
1692 * that for SAS drives they're out of luck.
1693 */
1694 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1695 dev_info(&pdev->dev,
1696 "PDC42819 can only drive SATA devices with this driver\n");
1697
1698 /* Some devices use non-standard BARs */
1699 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1700 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1701 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1702 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1703 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1704 if (pdev->device == 0xa01c)
1705 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1706 if (pdev->device == 0xa084)
1707 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1708 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1709 if (pdev->device == 0x7a08)
1710 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1711 }
1712
1713 /* acquire resources */
1714 rc = pcim_enable_device(pdev);
1715 if (rc)
1716 return rc;
1717
1718 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1719 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1720 u8 map;
1721
1722 /* ICH6s share the same PCI ID for both piix and ahci
1723 * modes. Enabling ahci mode while MAP indicates
1724 * combined mode is a bad idea. Yield to ata_piix.
1725 */
1726 pci_read_config_byte(pdev, ICH_MAP, &map);
1727 if (map & 0x3) {
1728 dev_info(&pdev->dev,
1729 "controller is in combined mode, can't enable AHCI mode\n");
1730 return -ENODEV;
1731 }
1732 }
1733
1734 /* AHCI controllers often implement SFF compatible interface.
1735 * Grab all PCI BARs just in case.
1736 */
1737 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1738 if (rc == -EBUSY)
1739 pcim_pin_device(pdev);
1740 if (rc)
1741 return rc;
1742
1743 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1744 if (!hpriv)
1745 return -ENOMEM;
1746 hpriv->flags |= (unsigned long)pi.private_data;
1747
1748 /* MCP65 revision A1 and A2 can't do MSI */
1749 if (board_id == board_ahci_mcp65 &&
1750 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1751 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1752
1753 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1754 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1755 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1756
1757 /* only some SB600s can do 64bit DMA */
1758 if (ahci_sb600_enable_64bit(pdev))
1759 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1760
1761 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1762
1763 /* detect remapped nvme devices */
1764 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1765
1766 sysfs_add_file_to_group(&pdev->dev.kobj,
1767 &dev_attr_remapped_nvme.attr,
1768 NULL);
1769
1770 /* must set flag prior to save config in order to take effect */
1771 if (ahci_broken_devslp(pdev))
1772 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1773
1774 #ifdef CONFIG_ARM64
1775 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1776 hpriv->irq_handler = ahci_thunderx_irq_handler;
1777 #endif
1778
1779 /* save initial config */
1780 ahci_pci_save_initial_config(pdev, hpriv);
1781
1782 /*
1783 * If platform firmware failed to enable ports, try to enable
1784 * them here.
1785 */
1786 ahci_intel_pcs_quirk(pdev, hpriv);
1787
1788 /* prepare host */
1789 if (hpriv->cap & HOST_CAP_NCQ) {
1790 pi.flags |= ATA_FLAG_NCQ;
1791 /*
1792 * Auto-activate optimization is supposed to be
1793 * supported on all AHCI controllers indicating NCQ
1794 * capability, but it seems to be broken on some
1795 * chipsets including NVIDIAs.
1796 */
1797 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1798 pi.flags |= ATA_FLAG_FPDMA_AA;
1799
1800 /*
1801 * All AHCI controllers should be forward-compatible
1802 * with the new auxiliary field. This code should be
1803 * conditionalized if any buggy AHCI controllers are
1804 * encountered.
1805 */
1806 pi.flags |= ATA_FLAG_FPDMA_AUX;
1807 }
1808
1809 if (hpriv->cap & HOST_CAP_PMP)
1810 pi.flags |= ATA_FLAG_PMP;
1811
1812 ahci_set_em_messages(hpriv, &pi);
1813
1814 if (ahci_broken_system_poweroff(pdev)) {
1815 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1816 dev_info(&pdev->dev,
1817 "quirky BIOS, skipping spindown on poweroff\n");
1818 }
1819
1820 if (ahci_broken_lpm(pdev)) {
1821 pi.flags |= ATA_FLAG_NO_LPM;
1822 dev_warn(&pdev->dev,
1823 "BIOS update required for Link Power Management support\n");
1824 }
1825
1826 if (ahci_broken_suspend(pdev)) {
1827 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1828 dev_warn(&pdev->dev,
1829 "BIOS update required for suspend/resume\n");
1830 }
1831
1832 if (ahci_broken_online(pdev)) {
1833 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1834 dev_info(&pdev->dev,
1835 "online status unreliable, applying workaround\n");
1836 }
1837
1838
1839 /* Acer SA5-271 workaround modifies private_data */
1840 acer_sa5_271_workaround(hpriv, pdev);
1841
1842 /* CAP.NP sometimes indicate the index of the last enabled
1843 * port, at other times, that of the last possible port, so
1844 * determining the maximum port number requires looking at
1845 * both CAP.NP and port_map.
1846 */
1847 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1848
1849 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1850 if (!host)
1851 return -ENOMEM;
1852 host->private_data = hpriv;
1853
1854 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1855 /* legacy intx interrupts */
1856 pci_intx(pdev, 1);
1857 }
1858 hpriv->irq = pci_irq_vector(pdev, 0);
1859
1860 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1861 host->flags |= ATA_HOST_PARALLEL_SCAN;
1862 else
1863 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1864
1865 if (pi.flags & ATA_FLAG_EM)
1866 ahci_reset_em(host);
1867
1868 for (i = 0; i < host->n_ports; i++) {
1869 struct ata_port *ap = host->ports[i];
1870
1871 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1872 ata_port_pbar_desc(ap, ahci_pci_bar,
1873 0x100 + ap->port_no * 0x80, "port");
1874
1875 /* set enclosure management message type */
1876 if (ap->flags & ATA_FLAG_EM)
1877 ap->em_message_type = hpriv->em_msg_type;
1878
1879 ahci_update_initial_lpm_policy(ap, hpriv);
1880
1881 /* disabled/not-implemented port */
1882 if (!(hpriv->port_map & (1 << i)))
1883 ap->ops = &ata_dummy_port_ops;
1884 }
1885
1886 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1887 ahci_p5wdh_workaround(host);
1888
1889 /* apply gtf filter quirk */
1890 ahci_gtf_filter_workaround(host);
1891
1892 /* initialize adapter */
1893 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1894 if (rc)
1895 return rc;
1896
1897 rc = ahci_reset_controller(host);
1898 if (rc)
1899 return rc;
1900
1901 ahci_pci_init_controller(host);
1902 ahci_pci_print_info(host);
1903
1904 pci_set_master(pdev);
1905
1906 rc = ahci_host_activate(host, &ahci_sht);
1907 if (rc)
1908 return rc;
1909
1910 pm_runtime_put_noidle(&pdev->dev);
1911 return 0;
1912 }
1913
ahci_shutdown_one(struct pci_dev * pdev)1914 static void ahci_shutdown_one(struct pci_dev *pdev)
1915 {
1916 ata_pci_shutdown_one(pdev);
1917 }
1918
ahci_remove_one(struct pci_dev * pdev)1919 static void ahci_remove_one(struct pci_dev *pdev)
1920 {
1921 sysfs_remove_file_from_group(&pdev->dev.kobj,
1922 &dev_attr_remapped_nvme.attr,
1923 NULL);
1924 pm_runtime_get_noresume(&pdev->dev);
1925 ata_pci_remove_one(pdev);
1926 }
1927
1928 module_pci_driver(ahci_pci_driver);
1929
1930 MODULE_AUTHOR("Jeff Garzik");
1931 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1932 MODULE_LICENSE("GPL");
1933 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1934 MODULE_VERSION(DRV_VERSION);
1935
