1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * include/asm-sh/cpu-sh2/cache.h 4 * 5 * Copyright (C) 2003 Paul Mundt 6 */ 7 #ifndef __ASM_CPU_SH2_CACHE_H 8 #define __ASM_CPU_SH2_CACHE_H 9 10 #define L1_CACHE_SHIFT 4 11 12 #define SH_CACHE_VALID 1 13 #define SH_CACHE_UPDATED 2 14 #define SH_CACHE_COMBINED 4 15 #define SH_CACHE_ASSOC 8 16 17 #if defined(CONFIG_CPU_SUBTYPE_SH7619) 18 #define SH_CCR 0xffffffec 19 20 #define CCR_CACHE_CE 0x01 /* Cache enable */ 21 #define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */ 22 /* 0x00000000-0x7fffffff: Write-through */ 23 /* 0x80000000-0x9fffffff: Write-back */ 24 /* 0xc0000000-0xdfffffff: Write-through */ 25 #define CCR_CACHE_CB 0x04 /* CCR[bit1=0,bit2=0] */ 26 /* 0x00000000-0x7fffffff: Write-back */ 27 /* 0x80000000-0x9fffffff: Write-through */ 28 /* 0xc0000000-0xdfffffff: Write-back */ 29 #define CCR_CACHE_CF 0x08 /* Cache invalidate */ 30 31 #define CACHE_OC_ADDRESS_ARRAY 0xf0000000 32 #define CACHE_OC_DATA_ARRAY 0xf1000000 33 34 #define CCR_CACHE_ENABLE CCR_CACHE_CE 35 #define CCR_CACHE_INVALIDATE CCR_CACHE_CF 36 #define CACHE_PHYSADDR_MASK 0x1ffffc00 37 38 #endif 39 40 #endif /* __ASM_CPU_SH2_CACHE_H */ 41
