1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Performance event support - hardware-specific disambiguation
4  *
5  * For now this is a compile-time decision, but eventually it should be
6  * runtime.  This would allow multiplatform perf event support for e300 (fsl
7  * embedded perf counters) plus server/classic, and would accommodate
8  * devices other than the core which provide their own performance counters.
9  *
10  * Copyright 2010 Freescale Semiconductor, Inc.
11  */
12 
13 #ifdef CONFIG_PPC_PERF_CTRS
14 #include <asm/perf_event_server.h>
15 #else
is_sier_available(void)16 static inline bool is_sier_available(void) { return false; }
17 #endif
18 
19 #ifdef CONFIG_FSL_EMB_PERF_EVENT
20 #include <asm/perf_event_fsl_emb.h>
21 #endif
22 
23 #ifdef CONFIG_PERF_EVENTS
24 #include <asm/ptrace.h>
25 #include <asm/reg.h>
26 
27 #define perf_arch_bpf_user_pt_regs(regs) &regs->user_regs
28 
29 /*
30  * Overload regs->result to specify whether we should use the MSR (result
31  * is zero) or the SIAR (result is non zero).
32  */
33 #define perf_arch_fetch_caller_regs(regs, __ip)			\
34 	do {							\
35 		(regs)->result = 0;				\
36 		(regs)->nip = __ip;				\
37 		(regs)->gpr[1] = current_stack_frame();		\
38 		asm volatile("mfmsr %0" : "=r" ((regs)->msr));	\
39 	} while (0)
40 
41 /* To support perf_regs sier update */
42 extern bool is_sier_available(void);
43 /* To define perf extended regs mask value */
44 extern u64 PERF_REG_EXTENDED_MASK;
45 #define PERF_REG_EXTENDED_MASK	PERF_REG_EXTENDED_MASK
46 #endif
47