1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/types.h>
3 #include <linux/i8253.h>
4 #include <linux/interrupt.h>
5 #include <linux/irq.h>
6 #include <linux/smp.h>
7 #include <linux/time.h>
8 #include <linux/clockchips.h>
9 
10 #include <asm/sni.h>
11 #include <asm/time.h>
12 
13 #define SNI_CLOCK_TICK_RATE	3686400
14 #define SNI_COUNTER2_DIV	64
15 #define SNI_COUNTER0_DIV	((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
16 
a20r_set_periodic(struct clock_event_device * evt)17 static int a20r_set_periodic(struct clock_event_device *evt)
18 {
19 	*(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34;
20 	wmb();
21 	*(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV;
22 	wmb();
23 	*(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV >> 8;
24 	wmb();
25 
26 	*(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4;
27 	wmb();
28 	*(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV;
29 	wmb();
30 	*(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV >> 8;
31 	wmb();
32 	return 0;
33 }
34 
35 static struct clock_event_device a20r_clockevent_device = {
36 	.name			= "a20r-timer",
37 	.features		= CLOCK_EVT_FEAT_PERIODIC,
38 
39 	/* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
40 
41 	.rating			= 300,
42 	.irq			= SNI_A20R_IRQ_TIMER,
43 	.set_state_periodic	= a20r_set_periodic,
44 };
45 
a20r_interrupt(int irq,void * dev_id)46 static irqreturn_t a20r_interrupt(int irq, void *dev_id)
47 {
48 	struct clock_event_device *cd = dev_id;
49 
50 	*(volatile u8 *)A20R_PT_TIM0_ACK = 0;
51 	wmb();
52 
53 	cd->event_handler(cd);
54 
55 	return IRQ_HANDLED;
56 }
57 
58 /*
59  * a20r platform uses 2 counters to divide the input frequency.
60  * Counter 2 output is connected to Counter 0 & 1 input.
61  */
sni_a20r_timer_setup(void)62 static void __init sni_a20r_timer_setup(void)
63 {
64 	struct clock_event_device *cd = &a20r_clockevent_device;
65 	unsigned int cpu = smp_processor_id();
66 
67 	cd->cpumask		= cpumask_of(cpu);
68 	clockevents_register_device(cd);
69 	if (request_irq(SNI_A20R_IRQ_TIMER, a20r_interrupt,
70 			IRQF_PERCPU | IRQF_TIMER, "a20r-timer", cd))
71 		pr_err("Failed to register a20r-timer interrupt\n");
72 }
73 
74 #define SNI_8254_TICK_RATE	  1193182UL
75 
76 #define SNI_8254_TCSAMP_COUNTER	  ((SNI_8254_TICK_RATE / HZ) + 255)
77 
dosample(void)78 static __init unsigned long dosample(void)
79 {
80 	u32 ct0, ct1;
81 	volatile u8 msb;
82 
83 	/* Start the counter. */
84 	outb_p(0x34, 0x43);
85 	outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
86 	outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
87 
88 	/* Get initial counter invariant */
89 	ct0 = read_c0_count();
90 
91 	/* Latch and spin until top byte of counter0 is zero */
92 	do {
93 		outb(0x00, 0x43);
94 		(void) inb(0x40);
95 		msb = inb(0x40);
96 		ct1 = read_c0_count();
97 	} while (msb);
98 
99 	/* Stop the counter. */
100 	outb(0x38, 0x43);
101 	/*
102 	 * Return the difference, this is how far the r4k counter increments
103 	 * for every 1/HZ seconds. We round off the nearest 1 MHz of master
104 	 * clock (= 1000000 / HZ / 2).
105 	 */
106 	/*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
107 	return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
108 }
109 
110 /*
111  * Here we need to calibrate the cycle counter to at least be close.
112  */
plat_time_init(void)113 void __init plat_time_init(void)
114 {
115 	unsigned long r4k_ticks[3];
116 	unsigned long r4k_tick;
117 
118 	/*
119 	 * Figure out the r4k offset, the algorithm is very simple and works in
120 	 * _all_ cases as long as the 8254 counter register itself works ok (as
121 	 * an interrupt driving timer it does not because of bug, this is why
122 	 * we are using the onchip r4k counter/compare register to serve this
123 	 * purpose, but for r4k_offset calculation it will work ok for us).
124 	 * There are other very complicated ways of performing this calculation
125 	 * but this one works just fine so I am not going to futz around. ;-)
126 	 */
127 	printk(KERN_INFO "Calibrating system timer... ");
128 	dosample();	/* Prime cache. */
129 	dosample();	/* Prime cache. */
130 	/* Zero is NOT an option. */
131 	do {
132 		r4k_ticks[0] = dosample();
133 	} while (!r4k_ticks[0]);
134 	do {
135 		r4k_ticks[1] = dosample();
136 	} while (!r4k_ticks[1]);
137 
138 	if (r4k_ticks[0] != r4k_ticks[1]) {
139 		printk("warning: timer counts differ, retrying... ");
140 		r4k_ticks[2] = dosample();
141 		if (r4k_ticks[2] == r4k_ticks[0]
142 		    || r4k_ticks[2] == r4k_ticks[1])
143 			r4k_tick = r4k_ticks[2];
144 		else {
145 			printk("disagreement, using average... ");
146 			r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
147 				   + r4k_ticks[2]) / 3;
148 		}
149 	} else
150 		r4k_tick = r4k_ticks[0];
151 
152 	printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
153 		(int) (r4k_tick / (500000 / HZ)),
154 		(int) (r4k_tick % (500000 / HZ)));
155 
156 	mips_hpt_frequency = r4k_tick * HZ;
157 
158 	switch (sni_brd_type) {
159 	case SNI_BRD_10:
160 	case SNI_BRD_10NEW:
161 	case SNI_BRD_TOWER_OASIC:
162 	case SNI_BRD_MINITOWER:
163 		sni_a20r_timer_setup();
164 		break;
165 	}
166 	setup_pit_timer();
167 }
168