1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
4 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
6 */
7 #include <linux/kernel.h>
8 #include <linux/export.h>
9 #include <linux/pci.h>
10 #include <linux/smp.h>
11 #include <linux/dma-direct.h>
12 #include <linux/platform_device.h>
13 #include <linux/platform_data/xtalk-bridge.h>
14 #include <linux/nvmem-consumer.h>
15 #include <linux/crc16.h>
16
17 #include <asm/pci/bridge.h>
18 #include <asm/paccess.h>
19 #include <asm/sn/irq_alloc.h>
20 #include <asm/sn/ioc3.h>
21
22 #define CRC16_INIT 0
23 #define CRC16_VALID 0xb001
24
25 /*
26 * Common phys<->dma mapping for platforms using pci xtalk bridge
27 */
phys_to_dma(struct device * dev,phys_addr_t paddr)28 dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
29 {
30 struct pci_dev *pdev = to_pci_dev(dev);
31 struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
32
33 return bc->baddr + paddr;
34 }
35
dma_to_phys(struct device * dev,dma_addr_t dma_addr)36 phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
37 {
38 return dma_addr & ~(0xffUL << 56);
39 }
40
41 /*
42 * Most of the IOC3 PCI config register aren't present
43 * we emulate what is needed for a normal PCI enumeration
44 */
ioc3_cfg_rd(void * addr,int where,int size,u32 * value,u32 sid)45 static int ioc3_cfg_rd(void *addr, int where, int size, u32 *value, u32 sid)
46 {
47 u32 cf, shift, mask;
48
49 switch (where & ~3) {
50 case 0x00 ... 0x10:
51 case 0x40 ... 0x44:
52 if (get_dbe(cf, (u32 *)addr))
53 return PCIBIOS_DEVICE_NOT_FOUND;
54 break;
55 case 0x2c:
56 cf = sid;
57 break;
58 case 0x3c:
59 /* emulate sane interrupt pin value */
60 cf = 0x00000100;
61 break;
62 default:
63 cf = 0;
64 break;
65 }
66 shift = (where & 3) << 3;
67 mask = 0xffffffffU >> ((4 - size) << 3);
68 *value = (cf >> shift) & mask;
69
70 return PCIBIOS_SUCCESSFUL;
71 }
72
ioc3_cfg_wr(void * addr,int where,int size,u32 value)73 static int ioc3_cfg_wr(void *addr, int where, int size, u32 value)
74 {
75 u32 cf, shift, mask, smask;
76
77 if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
78 return PCIBIOS_SUCCESSFUL;
79
80 if (get_dbe(cf, (u32 *)addr))
81 return PCIBIOS_DEVICE_NOT_FOUND;
82
83 shift = ((where & 3) << 3);
84 mask = (0xffffffffU >> ((4 - size) << 3));
85 smask = mask << shift;
86
87 cf = (cf & ~smask) | ((value & mask) << shift);
88 if (put_dbe(cf, (u32 *)addr))
89 return PCIBIOS_DEVICE_NOT_FOUND;
90
91 return PCIBIOS_SUCCESSFUL;
92 }
93
bridge_disable_swapping(struct pci_dev * dev)94 static void bridge_disable_swapping(struct pci_dev *dev)
95 {
96 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
97 int slot = PCI_SLOT(dev->devfn);
98
99 /* Turn off byte swapping */
100 bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
101 bridge_read(bc, b_widget.w_tflush); /* Flush */
102 }
103
104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
105 bridge_disable_swapping);
106
107
108 /*
109 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
110 * not really documented, so right now I can't write code which uses it.
111 * Therefore we use type 0 accesses for now even though they won't work
112 * correctly for PCI-to-PCI bridges.
113 *
114 * The function is complicated by the ultimate brokenness of the IOC3 chip
115 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI
116 * accesses and does only decode parts of it's address space.
117 */
pci_conf0_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)118 static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
119 int where, int size, u32 *value)
120 {
121 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
122 struct bridge_regs *bridge = bc->base;
123 int slot = PCI_SLOT(devfn);
124 int fn = PCI_FUNC(devfn);
125 void *addr;
126 u32 cf;
127 int res;
128
129 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
130 if (get_dbe(cf, (u32 *)addr))
131 return PCIBIOS_DEVICE_NOT_FOUND;
132
133 /*
134 * IOC3 is broken beyond belief ... Don't even give the
135 * generic PCI code a chance to look at it for real ...
136 */
137 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
138 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
139 return ioc3_cfg_rd(addr, where, size, value,
140 bc->ioc3_sid[slot]);
141 }
142
143 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
144
145 if (size == 1)
146 res = get_dbe(*value, (u8 *)addr);
147 else if (size == 2)
148 res = get_dbe(*value, (u16 *)addr);
149 else
150 res = get_dbe(*value, (u32 *)addr);
151
152 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
153 }
154
pci_conf1_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)155 static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
156 int where, int size, u32 *value)
157 {
158 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
159 struct bridge_regs *bridge = bc->base;
160 int busno = bus->number;
161 int slot = PCI_SLOT(devfn);
162 int fn = PCI_FUNC(devfn);
163 void *addr;
164 u32 cf;
165 int res;
166
167 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
168 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
169 if (get_dbe(cf, (u32 *)addr))
170 return PCIBIOS_DEVICE_NOT_FOUND;
171
172 /*
173 * IOC3 is broken beyond belief ... Don't even give the
174 * generic PCI code a chance to look at it for real ...
175 */
176 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
177 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where & ~3)];
178 return ioc3_cfg_rd(addr, where, size, value,
179 bc->ioc3_sid[slot]);
180 }
181
182 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
183
184 if (size == 1)
185 res = get_dbe(*value, (u8 *)addr);
186 else if (size == 2)
187 res = get_dbe(*value, (u16 *)addr);
188 else
189 res = get_dbe(*value, (u32 *)addr);
190
191 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
192 }
193
pci_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)194 static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
195 int where, int size, u32 *value)
196 {
197 if (!pci_is_root_bus(bus))
198 return pci_conf1_read_config(bus, devfn, where, size, value);
199
200 return pci_conf0_read_config(bus, devfn, where, size, value);
201 }
202
pci_conf0_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)203 static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
204 int where, int size, u32 value)
205 {
206 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
207 struct bridge_regs *bridge = bc->base;
208 int slot = PCI_SLOT(devfn);
209 int fn = PCI_FUNC(devfn);
210 void *addr;
211 u32 cf;
212 int res;
213
214 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
215 if (get_dbe(cf, (u32 *)addr))
216 return PCIBIOS_DEVICE_NOT_FOUND;
217
218 /*
219 * IOC3 is broken beyond belief ... Don't even give the
220 * generic PCI code a chance to look at it for real ...
221 */
222 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
223 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
224 return ioc3_cfg_wr(addr, where, size, value);
225 }
226
227 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
228
229 if (size == 1)
230 res = put_dbe(value, (u8 *)addr);
231 else if (size == 2)
232 res = put_dbe(value, (u16 *)addr);
233 else
234 res = put_dbe(value, (u32 *)addr);
235
236 if (res)
237 return PCIBIOS_DEVICE_NOT_FOUND;
238
239 return PCIBIOS_SUCCESSFUL;
240 }
241
pci_conf1_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)242 static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
243 int where, int size, u32 value)
244 {
245 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
246 struct bridge_regs *bridge = bc->base;
247 int slot = PCI_SLOT(devfn);
248 int fn = PCI_FUNC(devfn);
249 int busno = bus->number;
250 void *addr;
251 u32 cf;
252 int res;
253
254 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
255 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
256 if (get_dbe(cf, (u32 *)addr))
257 return PCIBIOS_DEVICE_NOT_FOUND;
258
259 /*
260 * IOC3 is broken beyond belief ... Don't even give the
261 * generic PCI code a chance to look at it for real ...
262 */
263 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
264 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
265 return ioc3_cfg_wr(addr, where, size, value);
266 }
267
268 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
269
270 if (size == 1)
271 res = put_dbe(value, (u8 *)addr);
272 else if (size == 2)
273 res = put_dbe(value, (u16 *)addr);
274 else
275 res = put_dbe(value, (u32 *)addr);
276
277 if (res)
278 return PCIBIOS_DEVICE_NOT_FOUND;
279
280 return PCIBIOS_SUCCESSFUL;
281 }
282
pci_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)283 static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
284 int where, int size, u32 value)
285 {
286 if (!pci_is_root_bus(bus))
287 return pci_conf1_write_config(bus, devfn, where, size, value);
288
289 return pci_conf0_write_config(bus, devfn, where, size, value);
290 }
291
292 static struct pci_ops bridge_pci_ops = {
293 .read = pci_read_config,
294 .write = pci_write_config,
295 };
296
297 struct bridge_irq_chip_data {
298 struct bridge_controller *bc;
299 nasid_t nasid;
300 };
301
bridge_set_affinity(struct irq_data * d,const struct cpumask * mask,bool force)302 static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
303 bool force)
304 {
305 #ifdef CONFIG_NUMA
306 struct bridge_irq_chip_data *data = d->chip_data;
307 int bit = d->parent_data->hwirq;
308 int pin = d->hwirq;
309 int ret, cpu;
310
311 ret = irq_chip_set_affinity_parent(d, mask, force);
312 if (ret >= 0) {
313 cpu = cpumask_first_and(mask, cpu_online_mask);
314 data->nasid = cpu_to_node(cpu);
315 bridge_write(data->bc, b_int_addr[pin].addr,
316 (((data->bc->intr_addr >> 30) & 0x30000) |
317 bit | (data->nasid << 8)));
318 bridge_read(data->bc, b_wid_tflush);
319 }
320 return ret;
321 #else
322 return irq_chip_set_affinity_parent(d, mask, force);
323 #endif
324 }
325
326 struct irq_chip bridge_irq_chip = {
327 .name = "BRIDGE",
328 .irq_mask = irq_chip_mask_parent,
329 .irq_unmask = irq_chip_unmask_parent,
330 .irq_set_affinity = bridge_set_affinity
331 };
332
bridge_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)333 static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq,
334 unsigned int nr_irqs, void *arg)
335 {
336 struct bridge_irq_chip_data *data;
337 struct irq_alloc_info *info = arg;
338 int ret;
339
340 if (nr_irqs > 1 || !info)
341 return -EINVAL;
342
343 data = kzalloc(sizeof(*data), GFP_KERNEL);
344 if (!data)
345 return -ENOMEM;
346
347 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
348 if (ret >= 0) {
349 data->bc = info->ctrl;
350 data->nasid = info->nasid;
351 irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip,
352 data, handle_level_irq, NULL, NULL);
353 } else {
354 kfree(data);
355 }
356
357 return ret;
358 }
359
bridge_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)360 static void bridge_domain_free(struct irq_domain *domain, unsigned int virq,
361 unsigned int nr_irqs)
362 {
363 struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
364
365 if (nr_irqs)
366 return;
367
368 kfree(irqd->chip_data);
369 irq_domain_free_irqs_top(domain, virq, nr_irqs);
370 }
371
bridge_domain_activate(struct irq_domain * domain,struct irq_data * irqd,bool reserve)372 static int bridge_domain_activate(struct irq_domain *domain,
373 struct irq_data *irqd, bool reserve)
374 {
375 struct bridge_irq_chip_data *data = irqd->chip_data;
376 struct bridge_controller *bc = data->bc;
377 int bit = irqd->parent_data->hwirq;
378 int pin = irqd->hwirq;
379 u32 device;
380
381 bridge_write(bc, b_int_addr[pin].addr,
382 (((bc->intr_addr >> 30) & 0x30000) |
383 bit | (data->nasid << 8)));
384 bridge_set(bc, b_int_enable, (1 << pin));
385 bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
386
387 /*
388 * Enable sending of an interrupt clear packt to the hub on a high to
389 * low transition of the interrupt pin.
390 *
391 * IRIX sets additional bits in the address which are documented as
392 * reserved in the bridge docs.
393 */
394 bridge_set(bc, b_int_mode, (1UL << pin));
395
396 /*
397 * We assume the bridge to have a 1:1 mapping between devices
398 * (slots) and intr pins.
399 */
400 device = bridge_read(bc, b_int_device);
401 device &= ~(7 << (pin*3));
402 device |= (pin << (pin*3));
403 bridge_write(bc, b_int_device, device);
404
405 bridge_read(bc, b_wid_tflush);
406 return 0;
407 }
408
bridge_domain_deactivate(struct irq_domain * domain,struct irq_data * irqd)409 static void bridge_domain_deactivate(struct irq_domain *domain,
410 struct irq_data *irqd)
411 {
412 struct bridge_irq_chip_data *data = irqd->chip_data;
413
414 bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
415 bridge_read(data->bc, b_wid_tflush);
416 }
417
418 static const struct irq_domain_ops bridge_domain_ops = {
419 .alloc = bridge_domain_alloc,
420 .free = bridge_domain_free,
421 .activate = bridge_domain_activate,
422 .deactivate = bridge_domain_deactivate
423 };
424
425 /*
426 * All observed requests have pin == 1. We could have a global here, that
427 * gets incremented and returned every time - unfortunately, pci_map_irq
428 * may be called on the same device over and over, and need to return the
429 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
430 *
431 * A given PCI device, in general, should be able to intr any of the cpus
432 * on any one of the hubs connected to its xbow.
433 */
bridge_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)434 static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
435 {
436 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
437 struct irq_alloc_info info;
438 int irq;
439
440 switch (pin) {
441 case PCI_INTERRUPT_UNKNOWN:
442 case PCI_INTERRUPT_INTA:
443 case PCI_INTERRUPT_INTC:
444 pin = 0;
445 break;
446 case PCI_INTERRUPT_INTB:
447 case PCI_INTERRUPT_INTD:
448 pin = 1;
449 }
450
451 irq = bc->pci_int[slot][pin];
452 if (irq == -1) {
453 info.ctrl = bc;
454 info.nasid = bc->nasid;
455 info.pin = bc->int_mapping[slot][pin];
456
457 irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
458 if (irq < 0)
459 return irq;
460
461 bc->pci_int[slot][pin] = irq;
462 }
463 return irq;
464 }
465
466 #define IOC3_SID(sid) (PCI_VENDOR_ID_SGI | ((sid) << 16))
467
bridge_setup_ip27_baseio6g(struct bridge_controller * bc)468 static void bridge_setup_ip27_baseio6g(struct bridge_controller *bc)
469 {
470 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO6G);
471 bc->ioc3_sid[6] = IOC3_SID(IOC3_SUBSYS_IP27_MIO);
472 bc->int_mapping[2][1] = 4;
473 bc->int_mapping[6][1] = 6;
474 }
475
bridge_setup_ip27_baseio(struct bridge_controller * bc)476 static void bridge_setup_ip27_baseio(struct bridge_controller *bc)
477 {
478 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO);
479 bc->int_mapping[2][1] = 4;
480 }
481
bridge_setup_ip29_baseio(struct bridge_controller * bc)482 static void bridge_setup_ip29_baseio(struct bridge_controller *bc)
483 {
484 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP29_SYSBOARD);
485 bc->int_mapping[2][1] = 3;
486 }
487
bridge_setup_ip30_sysboard(struct bridge_controller * bc)488 static void bridge_setup_ip30_sysboard(struct bridge_controller *bc)
489 {
490 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP30_SYSBOARD);
491 bc->int_mapping[2][1] = 4;
492 }
493
bridge_setup_menet(struct bridge_controller * bc)494 static void bridge_setup_menet(struct bridge_controller *bc)
495 {
496 bc->ioc3_sid[0] = IOC3_SID(IOC3_SUBSYS_MENET);
497 bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_MENET);
498 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_MENET);
499 bc->ioc3_sid[3] = IOC3_SID(IOC3_SUBSYS_MENET4);
500 }
501
bridge_setup_io7(struct bridge_controller * bc)502 static void bridge_setup_io7(struct bridge_controller *bc)
503 {
504 bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO7);
505 }
506
bridge_setup_io8(struct bridge_controller * bc)507 static void bridge_setup_io8(struct bridge_controller *bc)
508 {
509 bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO8);
510 }
511
bridge_setup_io9(struct bridge_controller * bc)512 static void bridge_setup_io9(struct bridge_controller *bc)
513 {
514 bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_IO9);
515 }
516
bridge_setup_ip34_fuel_sysboard(struct bridge_controller * bc)517 static void bridge_setup_ip34_fuel_sysboard(struct bridge_controller *bc)
518 {
519 bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IP34_SYSBOARD);
520 }
521
522 #define BRIDGE_BOARD_SETUP(_partno, _setup) \
523 { .match = _partno, .setup = _setup }
524
525 static const struct {
526 char *match;
527 void (*setup)(struct bridge_controller *bc);
528 } bridge_ioc3_devid[] = {
529 BRIDGE_BOARD_SETUP("030-0734-", bridge_setup_ip27_baseio6g),
530 BRIDGE_BOARD_SETUP("030-0880-", bridge_setup_ip27_baseio6g),
531 BRIDGE_BOARD_SETUP("030-1023-", bridge_setup_ip27_baseio),
532 BRIDGE_BOARD_SETUP("030-1124-", bridge_setup_ip27_baseio),
533 BRIDGE_BOARD_SETUP("030-1025-", bridge_setup_ip29_baseio),
534 BRIDGE_BOARD_SETUP("030-1244-", bridge_setup_ip29_baseio),
535 BRIDGE_BOARD_SETUP("030-1389-", bridge_setup_ip29_baseio),
536 BRIDGE_BOARD_SETUP("030-0887-", bridge_setup_ip30_sysboard),
537 BRIDGE_BOARD_SETUP("030-1467-", bridge_setup_ip30_sysboard),
538 BRIDGE_BOARD_SETUP("030-0873-", bridge_setup_menet),
539 BRIDGE_BOARD_SETUP("030-1557-", bridge_setup_io7),
540 BRIDGE_BOARD_SETUP("030-1673-", bridge_setup_io8),
541 BRIDGE_BOARD_SETUP("030-1771-", bridge_setup_io9),
542 BRIDGE_BOARD_SETUP("030-1707-", bridge_setup_ip34_fuel_sysboard),
543 };
544
bridge_setup_board(struct bridge_controller * bc,char * partnum)545 static void bridge_setup_board(struct bridge_controller *bc, char *partnum)
546 {
547 int i;
548
549 for (i = 0; i < ARRAY_SIZE(bridge_ioc3_devid); i++)
550 if (!strncmp(partnum, bridge_ioc3_devid[i].match,
551 strlen(bridge_ioc3_devid[i].match))) {
552 bridge_ioc3_devid[i].setup(bc);
553 }
554 }
555
bridge_nvmem_match(struct device * dev,const void * data)556 static int bridge_nvmem_match(struct device *dev, const void *data)
557 {
558 const char *name = dev_name(dev);
559 const char *prefix = data;
560
561 if (strlen(name) < strlen(prefix))
562 return 0;
563
564 return memcmp(prefix, dev_name(dev), strlen(prefix)) == 0;
565 }
566
bridge_get_partnum(u64 baddr,char * partnum)567 static int bridge_get_partnum(u64 baddr, char *partnum)
568 {
569 struct nvmem_device *nvmem;
570 char prefix[24];
571 u8 prom[64];
572 int i, j;
573 int ret;
574
575 snprintf(prefix, sizeof(prefix), "bridge-%012llx-0b-", baddr);
576
577 nvmem = nvmem_device_find(prefix, bridge_nvmem_match);
578 if (IS_ERR(nvmem))
579 return PTR_ERR(nvmem);
580
581 ret = nvmem_device_read(nvmem, 0, 64, prom);
582 nvmem_device_put(nvmem);
583
584 if (ret != 64)
585 return ret;
586
587 if (crc16(CRC16_INIT, prom, 32) != CRC16_VALID ||
588 crc16(CRC16_INIT, prom + 32, 32) != CRC16_VALID)
589 return -EINVAL;
590
591 /* Assemble part number */
592 j = 0;
593 for (i = 0; i < 19; i++)
594 if (prom[i + 11] != ' ')
595 partnum[j++] = prom[i + 11];
596
597 for (i = 0; i < 6; i++)
598 if (prom[i + 32] != ' ')
599 partnum[j++] = prom[i + 32];
600
601 partnum[j] = 0;
602
603 return 0;
604 }
605
bridge_probe(struct platform_device * pdev)606 static int bridge_probe(struct platform_device *pdev)
607 {
608 struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev);
609 struct device *dev = &pdev->dev;
610 struct bridge_controller *bc;
611 struct pci_host_bridge *host;
612 struct irq_domain *domain, *parent;
613 struct fwnode_handle *fn;
614 char partnum[26];
615 int slot;
616 int err;
617
618 /* get part number from one wire prom */
619 if (bridge_get_partnum(virt_to_phys((void *)bd->bridge_addr), partnum))
620 return -EPROBE_DEFER; /* not available yet */
621
622 parent = irq_get_default_host();
623 if (!parent)
624 return -ENODEV;
625 fn = irq_domain_alloc_named_fwnode("BRIDGE");
626 if (!fn)
627 return -ENOMEM;
628 domain = irq_domain_create_hierarchy(parent, 0, 8, fn,
629 &bridge_domain_ops, NULL);
630 if (!domain) {
631 irq_domain_free_fwnode(fn);
632 return -ENOMEM;
633 }
634
635 pci_set_flags(PCI_PROBE_ONLY);
636
637 host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
638 if (!host) {
639 err = -ENOMEM;
640 goto err_remove_domain;
641 }
642
643 bc = pci_host_bridge_priv(host);
644
645 bc->busn.name = "Bridge PCI busn";
646 bc->busn.start = 0;
647 bc->busn.end = 0xff;
648 bc->busn.flags = IORESOURCE_BUS;
649
650 bc->domain = domain;
651
652 pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset);
653 pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset);
654 pci_add_resource(&host->windows, &bc->busn);
655
656 err = devm_request_pci_bus_resources(dev, &host->windows);
657 if (err < 0)
658 goto err_free_resource;
659
660 bc->nasid = bd->nasid;
661
662 bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
663 bc->base = (struct bridge_regs *)bd->bridge_addr;
664 bc->intr_addr = bd->intr_addr;
665
666 /*
667 * Clear all pending interrupts.
668 */
669 bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
670
671 /*
672 * Until otherwise set up, assume all interrupts are from slot 0
673 */
674 bridge_write(bc, b_int_device, 0x0);
675
676 /*
677 * disable swapping for big windows
678 */
679 bridge_clr(bc, b_wid_control,
680 BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP);
681 #ifdef CONFIG_PAGE_SIZE_4KB
682 bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
683 #else /* 16kB or larger */
684 bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
685 #endif
686
687 /*
688 * Hmm... IRIX sets additional bits in the address which
689 * are documented as reserved in the bridge docs.
690 */
691 bridge_write(bc, b_wid_int_upper,
692 ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
693 bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
694 bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */
695 bridge_write(bc, b_int_enable, 0);
696
697 for (slot = 0; slot < 8; slot++) {
698 bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
699 bc->pci_int[slot][0] = -1;
700 bc->pci_int[slot][1] = -1;
701 /* default interrupt pin mapping */
702 bc->int_mapping[slot][0] = slot;
703 bc->int_mapping[slot][1] = slot ^ 4;
704 }
705 bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
706
707 bridge_setup_board(bc, partnum);
708
709 host->dev.parent = dev;
710 host->sysdata = bc;
711 host->busnr = 0;
712 host->ops = &bridge_pci_ops;
713 host->map_irq = bridge_map_irq;
714 host->swizzle_irq = pci_common_swizzle;
715
716 err = pci_scan_root_bus_bridge(host);
717 if (err < 0)
718 goto err_free_resource;
719
720 pci_bus_claim_resources(host->bus);
721 pci_bus_add_devices(host->bus);
722
723 platform_set_drvdata(pdev, host->bus);
724
725 return 0;
726
727 err_free_resource:
728 pci_free_resource_list(&host->windows);
729 err_remove_domain:
730 irq_domain_remove(domain);
731 irq_domain_free_fwnode(fn);
732 return err;
733 }
734
bridge_remove(struct platform_device * pdev)735 static int bridge_remove(struct platform_device *pdev)
736 {
737 struct pci_bus *bus = platform_get_drvdata(pdev);
738 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
739 struct fwnode_handle *fn = bc->domain->fwnode;
740
741 irq_domain_remove(bc->domain);
742 irq_domain_free_fwnode(fn);
743 pci_lock_rescan_remove();
744 pci_stop_root_bus(bus);
745 pci_remove_root_bus(bus);
746 pci_unlock_rescan_remove();
747
748 return 0;
749 }
750
751 static struct platform_driver bridge_driver = {
752 .probe = bridge_probe,
753 .remove = bridge_remove,
754 .driver = {
755 .name = "xtalk-bridge",
756 }
757 };
758
759 builtin_platform_driver(bridge_driver);
760
