1 /*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #ifndef _NLM_HAL_PIC_H
36 #define _NLM_HAL_PIC_H
37
38 /* PIC Specific registers */
39 #define PIC_CTRL 0x00
40
41 /* PIC control register defines */
42 #define PIC_CTRL_ITV 32 /* interrupt timeout value */
43 #define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
44 #define PIC_CTRL_ITE 18 /* interrupt timeout enable */
45 #define PIC_CTRL_STE 10 /* system timer interrupt enable */
46 #define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
47 #define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
48 #define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
49 #define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
50 #define PIC_CTRL_WTE 0 /* watchdog timer enable */
51
52 /* PIC Status register defines */
53 #define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
54 #define PIC_ITE_STATUS 32 /* interrupt timeout status */
55 #define PIC_STS_STATUS 4 /* System timer interrupt status */
56 #define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
57 #define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
58
59 /* PIC IPI control register offsets */
60 #define PIC_IPICTRL_NMI 32
61 #define PIC_IPICTRL_RIV 20 /* received interrupt vector */
62 #define PIC_IPICTRL_IDB 16 /* interrupt destination base */
63 #define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
64
65 /* PIC IRT register offsets */
66 #define PIC_IRT_ENABLE 31
67 #define PIC_IRT_NMI 29
68 #define PIC_IRT_SCH 28 /* Scheduling scheme */
69 #define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
70 #define PIC_IRT_DT 19 /* Destination type */
71 #define PIC_IRT_DB 16 /* Destination base */
72 #define PIC_IRT_DTE 0 /* Destination thread enables */
73
74 #define PIC_BYTESWAP 0x02
75 #define PIC_STATUS 0x04
76 #define PIC_INTR_TIMEOUT 0x06
77 #define PIC_ICI0_INTR_TIMEOUT 0x08
78 #define PIC_ICI1_INTR_TIMEOUT 0x0a
79 #define PIC_ICI2_INTR_TIMEOUT 0x0c
80 #define PIC_IPI_CTL 0x0e
81 #define PIC_INT_ACK 0x10
82 #define PIC_INT_PENDING0 0x12
83 #define PIC_INT_PENDING1 0x14
84 #define PIC_INT_PENDING2 0x16
85
86 #define PIC_WDOG0_MAXVAL 0x18
87 #define PIC_WDOG0_COUNT 0x1a
88 #define PIC_WDOG0_ENABLE0 0x1c
89 #define PIC_WDOG0_ENABLE1 0x1e
90 #define PIC_WDOG0_BEATCMD 0x20
91 #define PIC_WDOG0_BEAT0 0x22
92 #define PIC_WDOG0_BEAT1 0x24
93
94 #define PIC_WDOG1_MAXVAL 0x26
95 #define PIC_WDOG1_COUNT 0x28
96 #define PIC_WDOG1_ENABLE0 0x2a
97 #define PIC_WDOG1_ENABLE1 0x2c
98 #define PIC_WDOG1_BEATCMD 0x2e
99 #define PIC_WDOG1_BEAT0 0x30
100 #define PIC_WDOG1_BEAT1 0x32
101
102 #define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
103 #define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
104 #define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
105 #define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
106 #define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
107 #define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
108 #define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
109
110 #define PIC_TIMER0_MAXVAL 0x34
111 #define PIC_TIMER1_MAXVAL 0x36
112 #define PIC_TIMER2_MAXVAL 0x38
113 #define PIC_TIMER3_MAXVAL 0x3a
114 #define PIC_TIMER4_MAXVAL 0x3c
115 #define PIC_TIMER5_MAXVAL 0x3e
116 #define PIC_TIMER6_MAXVAL 0x40
117 #define PIC_TIMER7_MAXVAL 0x42
118 #define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
119
120 #define PIC_TIMER0_COUNT 0x44
121 #define PIC_TIMER1_COUNT 0x46
122 #define PIC_TIMER2_COUNT 0x48
123 #define PIC_TIMER3_COUNT 0x4a
124 #define PIC_TIMER4_COUNT 0x4c
125 #define PIC_TIMER5_COUNT 0x4e
126 #define PIC_TIMER6_COUNT 0x50
127 #define PIC_TIMER7_COUNT 0x52
128 #define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
129
130 #define PIC_ITE0_N0_N1 0x54
131 #define PIC_ITE1_N0_N1 0x58
132 #define PIC_ITE2_N0_N1 0x5c
133 #define PIC_ITE3_N0_N1 0x60
134 #define PIC_ITE4_N0_N1 0x64
135 #define PIC_ITE5_N0_N1 0x68
136 #define PIC_ITE6_N0_N1 0x6c
137 #define PIC_ITE7_N0_N1 0x70
138 #define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
139
140 #define PIC_ITE0_N2_N3 0x56
141 #define PIC_ITE1_N2_N3 0x5a
142 #define PIC_ITE2_N2_N3 0x5e
143 #define PIC_ITE3_N2_N3 0x62
144 #define PIC_ITE4_N2_N3 0x66
145 #define PIC_ITE5_N2_N3 0x6a
146 #define PIC_ITE6_N2_N3 0x6e
147 #define PIC_ITE7_N2_N3 0x72
148 #define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
149
150 #define PIC_IRT0 0x74
151 #define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
152
153 #define PIC_9XX_PENDING_0 0x6
154 #define PIC_9XX_PENDING_1 0x8
155 #define PIC_9XX_PENDING_2 0xa
156 #define PIC_9XX_PENDING_3 0xc
157
158 #define PIC_9XX_IRT0 0x1c0
159 #define PIC_9XX_IRT(i) (PIC_9XX_IRT0 + ((i) * 2))
160
161 /*
162 * IRT Map
163 */
164 #define PIC_NUM_IRTS 160
165 #define PIC_9XX_NUM_IRTS 256
166
167 #define PIC_IRT_WD_0_INDEX 0
168 #define PIC_IRT_WD_1_INDEX 1
169 #define PIC_IRT_WD_NMI_0_INDEX 2
170 #define PIC_IRT_WD_NMI_1_INDEX 3
171 #define PIC_IRT_TIMER_0_INDEX 4
172 #define PIC_IRT_TIMER_1_INDEX 5
173 #define PIC_IRT_TIMER_2_INDEX 6
174 #define PIC_IRT_TIMER_3_INDEX 7
175 #define PIC_IRT_TIMER_4_INDEX 8
176 #define PIC_IRT_TIMER_5_INDEX 9
177 #define PIC_IRT_TIMER_6_INDEX 10
178 #define PIC_IRT_TIMER_7_INDEX 11
179 #define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
180 #define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
181
182
183 /* 11 and 12 */
184 #define PIC_NUM_MSG_Q_IRTS 32
185 #define PIC_IRT_MSG_Q0_INDEX 12
186 #define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX)
187 /* 12 to 43 */
188 #define PIC_IRT_MSG_0_INDEX 44
189 #define PIC_IRT_MSG_1_INDEX 45
190 /* 44 and 45 */
191 #define PIC_NUM_PCIE_MSIX_IRTS 32
192 #define PIC_IRT_PCIE_MSIX_0_INDEX 46
193 #define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
194 /* 46 to 77 */
195 #define PIC_NUM_PCIE_LINK_IRTS 4
196 #define PIC_IRT_PCIE_LINK_0_INDEX 78
197 #define PIC_IRT_PCIE_LINK_1_INDEX 79
198 #define PIC_IRT_PCIE_LINK_2_INDEX 80
199 #define PIC_IRT_PCIE_LINK_3_INDEX 81
200 #define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
201
202 #define PIC_9XX_IRT_PCIE_LINK_0_INDEX 191
203 #define PIC_9XX_IRT_PCIE_LINK_INDEX(num) \
204 ((num) + PIC_9XX_IRT_PCIE_LINK_0_INDEX)
205
206 #define PIC_CLOCK_TIMER 7
207
208 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
209
210 /*
211 * Misc
212 */
213 #define PIC_IRT_VALID 1
214 #define PIC_LOCAL_SCHEDULING 1
215 #define PIC_GLOBAL_SCHEDULING 0
216
217 #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
218 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
219 #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
220 XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))
221 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
222
223 /* We use PIC on node 0 as a timer */
224 #define pic_timer_freq() nlm_get_pic_frequency(0)
225
226 /* IRT and h/w interrupt routines */
227 static inline void
nlm_9xx_pic_write_irt(uint64_t base,int irt_num,int en,int nmi,int sch,int vec,int dt,int db,int cpu)228 nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
229 int sch, int vec, int dt, int db, int cpu)
230 {
231 uint64_t val;
232
233 val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |
234 ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |
235 ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |
236 (cpu & 0x3ff);
237
238 nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);
239 }
240
241 static inline void
nlm_pic_write_irt(uint64_t base,int irt_num,int en,int nmi,int sch,int vec,int dt,int db,int dte)242 nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
243 int sch, int vec, int dt, int db, int dte)
244 {
245 uint64_t val;
246
247 val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
248 ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
249 ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
250 (dte & 0xffff);
251
252 nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
253 }
254
255 static inline void
nlm_pic_write_irt_direct(uint64_t base,int irt_num,int en,int nmi,int sch,int vec,int cpu)256 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
257 int sch, int vec, int cpu)
258 {
259 if (cpu_is_xlp9xx())
260 nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,
261 1, 0, cpu);
262 else
263 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
264 (cpu >> 4), /* thread group */
265 1 << (cpu & 0xf)); /* thread mask */
266 }
267
268 static inline uint64_t
nlm_pic_read_timer(uint64_t base,int timer)269 nlm_pic_read_timer(uint64_t base, int timer)
270 {
271 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
272 }
273
274 static inline uint32_t
nlm_pic_read_timer32(uint64_t base,int timer)275 nlm_pic_read_timer32(uint64_t base, int timer)
276 {
277 return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
278 }
279
280 static inline void
nlm_pic_write_timer(uint64_t base,int timer,uint64_t value)281 nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
282 {
283 nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
284 }
285
286 static inline void
nlm_pic_set_timer(uint64_t base,int timer,uint64_t value,int irq,int cpu)287 nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
288 {
289 uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
290 int en;
291
292 en = (irq > 0);
293 nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
294 nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
295 en, 0, 0, irq, cpu);
296
297 /* enable the timer */
298 pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
299 nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
300 }
301
302 static inline void
nlm_pic_enable_irt(uint64_t base,int irt)303 nlm_pic_enable_irt(uint64_t base, int irt)
304 {
305 uint64_t reg;
306
307 if (cpu_is_xlp9xx()) {
308 reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
309 nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));
310 } else {
311 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
312 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
313 }
314 }
315
316 static inline void
nlm_pic_disable_irt(uint64_t base,int irt)317 nlm_pic_disable_irt(uint64_t base, int irt)
318 {
319 uint64_t reg;
320
321 if (cpu_is_xlp9xx()) {
322 reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
323 reg &= ~((uint64_t)1 << 22);
324 nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);
325 } else {
326 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
327 reg &= ~((uint64_t)1 << 31);
328 nlm_write_pic_reg(base, PIC_IRT(irt), reg);
329 }
330 }
331
332 static inline void
nlm_pic_send_ipi(uint64_t base,int hwt,int irq,int nmi)333 nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
334 {
335 uint64_t ipi;
336
337 if (cpu_is_xlp9xx())
338 ipi = (nmi << 23) | (irq << 24) |
339 (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;
340 else
341 ipi = ((uint64_t)nmi << 31) | (irq << 20) |
342 ((hwt >> 4) << 16) | (1 << (hwt & 0xf));
343
344 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
345 }
346
347 static inline void
nlm_pic_ack(uint64_t base,int irt_num)348 nlm_pic_ack(uint64_t base, int irt_num)
349 {
350 nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
351
352 /* Ack the Status register for Watchdog & System timers */
353 if (irt_num < 12)
354 nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
355 }
356
357 static inline void
nlm_pic_init_irt(uint64_t base,int irt,int irq,int hwt,int en)358 nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
359 {
360 nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt);
361 }
362
363 int nlm_irq_to_irt(int irq);
364
365 #endif /* __ASSEMBLY__ */
366 #endif /* _NLM_HAL_PIC_H */
367
