1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
10 * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
11 */
12
13 /*
14 * Platform devices for Atheros AR2315 SoCs
15 */
16
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/bitops.h>
20 #include <linux/irqdomain.h>
21 #include <linux/interrupt.h>
22 #include <linux/memblock.h>
23 #include <linux/platform_device.h>
24 #include <linux/reboot.h>
25 #include <asm/bootinfo.h>
26 #include <asm/reboot.h>
27 #include <asm/time.h>
28
29 #include <ath25_platform.h>
30
31 #include "devices.h"
32 #include "ar2315.h"
33 #include "ar2315_regs.h"
34
35 static void __iomem *ar2315_rst_base;
36 static struct irq_domain *ar2315_misc_irq_domain;
37
ar2315_rst_reg_read(u32 reg)38 static inline u32 ar2315_rst_reg_read(u32 reg)
39 {
40 return __raw_readl(ar2315_rst_base + reg);
41 }
42
ar2315_rst_reg_write(u32 reg,u32 val)43 static inline void ar2315_rst_reg_write(u32 reg, u32 val)
44 {
45 __raw_writel(val, ar2315_rst_base + reg);
46 }
47
ar2315_rst_reg_mask(u32 reg,u32 mask,u32 val)48 static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
49 {
50 u32 ret = ar2315_rst_reg_read(reg);
51
52 ret &= ~mask;
53 ret |= val;
54 ar2315_rst_reg_write(reg, ret);
55 }
56
ar2315_ahb_err_handler(int cpl,void * dev_id)57 static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
58 {
59 ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
60 ar2315_rst_reg_read(AR2315_AHB_ERR1);
61
62 pr_emerg("AHB fatal error\n");
63 machine_restart("AHB error"); /* Catastrophic failure */
64
65 return IRQ_HANDLED;
66 }
67
ar2315_misc_irq_handler(struct irq_desc * desc)68 static void ar2315_misc_irq_handler(struct irq_desc *desc)
69 {
70 u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
71 ar2315_rst_reg_read(AR2315_IMR);
72 unsigned nr, misc_irq = 0;
73
74 if (pending) {
75 struct irq_domain *domain = irq_desc_get_handler_data(desc);
76
77 nr = __ffs(pending);
78 misc_irq = irq_find_mapping(domain, nr);
79 }
80
81 if (misc_irq) {
82 if (nr == AR2315_MISC_IRQ_GPIO)
83 ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
84 else if (nr == AR2315_MISC_IRQ_WATCHDOG)
85 ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
86 generic_handle_irq(misc_irq);
87 } else {
88 spurious_interrupt();
89 }
90 }
91
ar2315_misc_irq_unmask(struct irq_data * d)92 static void ar2315_misc_irq_unmask(struct irq_data *d)
93 {
94 ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
95 }
96
ar2315_misc_irq_mask(struct irq_data * d)97 static void ar2315_misc_irq_mask(struct irq_data *d)
98 {
99 ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
100 }
101
102 static struct irq_chip ar2315_misc_irq_chip = {
103 .name = "ar2315-misc",
104 .irq_unmask = ar2315_misc_irq_unmask,
105 .irq_mask = ar2315_misc_irq_mask,
106 };
107
ar2315_misc_irq_map(struct irq_domain * d,unsigned irq,irq_hw_number_t hw)108 static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
109 irq_hw_number_t hw)
110 {
111 irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
112 return 0;
113 }
114
115 static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
116 .map = ar2315_misc_irq_map,
117 };
118
119 /*
120 * Called when an interrupt is received, this function
121 * determines exactly which interrupt it was, and it
122 * invokes the appropriate handler.
123 *
124 * Implicitly, we also define interrupt priority by
125 * choosing which to dispatch first.
126 */
ar2315_irq_dispatch(void)127 static void ar2315_irq_dispatch(void)
128 {
129 u32 pending = read_c0_status() & read_c0_cause();
130
131 if (pending & CAUSEF_IP3)
132 do_IRQ(AR2315_IRQ_WLAN0);
133 #ifdef CONFIG_PCI_AR2315
134 else if (pending & CAUSEF_IP5)
135 do_IRQ(AR2315_IRQ_LCBUS_PCI);
136 #endif
137 else if (pending & CAUSEF_IP2)
138 do_IRQ(AR2315_IRQ_MISC);
139 else if (pending & CAUSEF_IP7)
140 do_IRQ(ATH25_IRQ_CPU_CLOCK);
141 else
142 spurious_interrupt();
143 }
144
ar2315_arch_init_irq(void)145 void __init ar2315_arch_init_irq(void)
146 {
147 struct irq_domain *domain;
148 unsigned irq;
149
150 ath25_irq_dispatch = ar2315_irq_dispatch;
151
152 domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
153 &ar2315_misc_irq_domain_ops, NULL);
154 if (!domain)
155 panic("Failed to add IRQ domain");
156
157 irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
158 if (request_irq(irq, ar2315_ahb_err_handler, 0, "ar2315-ahb-error",
159 NULL))
160 pr_err("Failed to register ar2315-ahb-error interrupt\n");
161
162 irq_set_chained_handler_and_data(AR2315_IRQ_MISC,
163 ar2315_misc_irq_handler, domain);
164
165 ar2315_misc_irq_domain = domain;
166 }
167
ar2315_init_devices(void)168 void __init ar2315_init_devices(void)
169 {
170 /* Find board configuration */
171 ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
172
173 ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
174 }
175
ar2315_restart(char * command)176 static void ar2315_restart(char *command)
177 {
178 void (*mips_reset_vec)(void) = (void *)0xbfc00000;
179
180 local_irq_disable();
181
182 /* try reset the system via reset control */
183 ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
184
185 /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
186 * a workaround. Give it some time to attempt a gpio based hardware
187 * reset (atheros reference design workaround) */
188
189 /* TODO: implement the GPIO reset workaround */
190
191 /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
192 * workaround. Attempt to jump to the mips reset location -
193 * the boot loader itself might be able to recover the system */
194 mips_reset_vec();
195 }
196
197 /*
198 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
199 * to determine the predevisor value.
200 */
201 static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
202 static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
203
ar2315_sys_clk(u32 clock_ctl)204 static unsigned __init ar2315_sys_clk(u32 clock_ctl)
205 {
206 unsigned int pllc_ctrl, cpu_div;
207 unsigned int pllc_out, refdiv, fdiv, divby2;
208 unsigned int clk_div;
209
210 pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
211 refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
212 refdiv = clockctl1_predivide_table[refdiv];
213 fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
214 divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
215 pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
216
217 /* clkm input selected */
218 switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
219 case 0:
220 case 1:
221 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
222 clk_div = pllc_divide_table[clk_div];
223 break;
224 case 2:
225 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
226 clk_div = pllc_divide_table[clk_div];
227 break;
228 default:
229 pllc_out = 40000000;
230 clk_div = 1;
231 break;
232 }
233
234 cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
235 cpu_div = cpu_div * 2 ?: 1;
236
237 return pllc_out / (clk_div * cpu_div);
238 }
239
ar2315_cpu_frequency(void)240 static inline unsigned ar2315_cpu_frequency(void)
241 {
242 return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
243 }
244
ar2315_apb_frequency(void)245 static inline unsigned ar2315_apb_frequency(void)
246 {
247 return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
248 }
249
ar2315_plat_time_init(void)250 void __init ar2315_plat_time_init(void)
251 {
252 mips_hpt_frequency = ar2315_cpu_frequency() / 2;
253 }
254
ar2315_plat_mem_setup(void)255 void __init ar2315_plat_mem_setup(void)
256 {
257 void __iomem *sdram_base;
258 u32 memsize, memcfg;
259 u32 devid;
260 u32 config;
261
262 /* Detect memory size */
263 sdram_base = ioremap(AR2315_SDRAMCTL_BASE,
264 AR2315_SDRAMCTL_SIZE);
265 memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
266 memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
267 memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
268 memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
269 memsize <<= 3;
270 memblock_add(0, memsize);
271 iounmap(sdram_base);
272
273 ar2315_rst_base = ioremap(AR2315_RST_BASE, AR2315_RST_SIZE);
274
275 /* Detect the hardware based on the device ID */
276 devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
277 switch (devid) {
278 case 0x91: /* Need to check */
279 ath25_soc = ATH25_SOC_AR2318;
280 break;
281 case 0x90:
282 ath25_soc = ATH25_SOC_AR2317;
283 break;
284 case 0x87:
285 ath25_soc = ATH25_SOC_AR2316;
286 break;
287 case 0x86:
288 default:
289 ath25_soc = ATH25_SOC_AR2315;
290 break;
291 }
292 ath25_board.devid = devid;
293
294 /* Clear any lingering AHB errors */
295 config = read_c0_config();
296 write_c0_config(config & ~0x3);
297 ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
298 ar2315_rst_reg_read(AR2315_AHB_ERR1);
299 ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
300
301 _machine_restart = ar2315_restart;
302 }
303
304 #ifdef CONFIG_PCI_AR2315
305 static struct resource ar2315_pci_res[] = {
306 {
307 .name = "ar2315-pci-ctrl",
308 .flags = IORESOURCE_MEM,
309 .start = AR2315_PCI_BASE,
310 .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
311 },
312 {
313 .name = "ar2315-pci-ext",
314 .flags = IORESOURCE_MEM,
315 .start = AR2315_PCI_EXT_BASE,
316 .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
317 },
318 {
319 .name = "ar2315-pci",
320 .flags = IORESOURCE_IRQ,
321 .start = AR2315_IRQ_LCBUS_PCI,
322 .end = AR2315_IRQ_LCBUS_PCI,
323 },
324 };
325 #endif
326
ar2315_arch_init(void)327 void __init ar2315_arch_init(void)
328 {
329 unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
330 AR2315_MISC_IRQ_UART0);
331
332 ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
333
334 #ifdef CONFIG_PCI_AR2315
335 if (ath25_soc == ATH25_SOC_AR2315) {
336 /* Reset PCI DMA logic */
337 ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
338 msleep(20);
339 ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
340 msleep(20);
341
342 /* Configure endians */
343 ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
344 AR2315_CONFIG_PCIAHB_BRIDGE);
345
346 /* Configure as PCI host with DMA */
347 ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
348 (AR2315_PCICLK_IN_FREQ_DIV_6 <<
349 AR2315_PCICLK_DIV_S));
350 ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
351 ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
352 AR2315_IF_MASK, AR2315_IF_PCI |
353 AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
354 (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
355 AR2315_IF_PCI_CLK_SHIFT));
356
357 platform_device_register_simple("ar2315-pci", -1,
358 ar2315_pci_res,
359 ARRAY_SIZE(ar2315_pci_res));
360 }
361 #endif
362 }
363
