1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Here is where the ball gets rolling as far as the kernel is concerned. 4 * When control is transferred to _start, the bootload has already 5 * loaded us to the correct address. All that's left to do here is 6 * to set up the kernel's global pointer and jump to the kernel 7 * entry point. 8 * 9 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co 10 * David Mosberger-Tang <davidm@hpl.hp.com> 11 * Stephane Eranian <eranian@hpl.hp.com> 12 * Copyright (C) 1999 VA Linux Systems 13 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 14 * Copyright (C) 1999 Intel Corp. 15 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com> 16 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com> 17 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com> 18 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2. 19 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com> 20 * Support for CPU Hotplug 21 */ 22 23 24#include <linux/pgtable.h> 25#include <asm/asmmacro.h> 26#include <asm/fpu.h> 27#include <asm/kregs.h> 28#include <asm/mmu_context.h> 29#include <asm/asm-offsets.h> 30#include <asm/pal.h> 31#include <asm/processor.h> 32#include <asm/ptrace.h> 33#include <asm/mca_asm.h> 34#include <linux/init.h> 35#include <linux/linkage.h> 36#include <linux/pgtable.h> 37#include <asm/export.h> 38 39#ifdef CONFIG_HOTPLUG_CPU 40#define SAL_PSR_BITS_TO_SET \ 41 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL) 42 43#define SAVE_FROM_REG(src, ptr, dest) \ 44 mov dest=src;; \ 45 st8 [ptr]=dest,0x08 46 47#define RESTORE_REG(reg, ptr, _tmp) \ 48 ld8 _tmp=[ptr],0x08;; \ 49 mov reg=_tmp 50 51#define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\ 52 mov ar.lc=IA64_NUM_DBG_REGS-1;; \ 53 mov _idx=0;; \ 541: \ 55 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \ 56 add _idx=1,_idx;; \ 57 br.cloop.sptk.many 1b 58 59#define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\ 60 mov ar.lc=IA64_NUM_DBG_REGS-1;; \ 61 mov _idx=0;; \ 62_lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \ 63 add _idx=1, _idx;; \ 64 br.cloop.sptk.many _lbl 65 66#define SAVE_ONE_RR(num, _reg, _tmp) \ 67 movl _tmp=(num<<61);; \ 68 mov _reg=rr[_tmp] 69 70#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \ 71 SAVE_ONE_RR(0,_r0, _tmp);; \ 72 SAVE_ONE_RR(1,_r1, _tmp);; \ 73 SAVE_ONE_RR(2,_r2, _tmp);; \ 74 SAVE_ONE_RR(3,_r3, _tmp);; \ 75 SAVE_ONE_RR(4,_r4, _tmp);; \ 76 SAVE_ONE_RR(5,_r5, _tmp);; \ 77 SAVE_ONE_RR(6,_r6, _tmp);; \ 78 SAVE_ONE_RR(7,_r7, _tmp);; 79 80#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \ 81 st8 [ptr]=_r0, 8;; \ 82 st8 [ptr]=_r1, 8;; \ 83 st8 [ptr]=_r2, 8;; \ 84 st8 [ptr]=_r3, 8;; \ 85 st8 [ptr]=_r4, 8;; \ 86 st8 [ptr]=_r5, 8;; \ 87 st8 [ptr]=_r6, 8;; \ 88 st8 [ptr]=_r7, 8;; 89 90#define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \ 91 mov ar.lc=0x08-1;; \ 92 movl _idx1=0x00;; \ 93RestRR: \ 94 dep.z _idx2=_idx1,61,3;; \ 95 ld8 _tmp=[ptr],8;; \ 96 mov rr[_idx2]=_tmp;; \ 97 srlz.d;; \ 98 add _idx1=1,_idx1;; \ 99 br.cloop.sptk.few RestRR 100 101#define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \ 102 movl reg1=sal_state_for_booting_cpu;; \ 103 ld8 reg2=[reg1];; 104 105/* 106 * Adjust region registers saved before starting to save 107 * break regs and rest of the states that need to be preserved. 108 */ 109#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \ 110 SAVE_FROM_REG(b0,_reg1,_reg2);; \ 111 SAVE_FROM_REG(b1,_reg1,_reg2);; \ 112 SAVE_FROM_REG(b2,_reg1,_reg2);; \ 113 SAVE_FROM_REG(b3,_reg1,_reg2);; \ 114 SAVE_FROM_REG(b4,_reg1,_reg2);; \ 115 SAVE_FROM_REG(b5,_reg1,_reg2);; \ 116 st8 [_reg1]=r1,0x08;; \ 117 st8 [_reg1]=r12,0x08;; \ 118 st8 [_reg1]=r13,0x08;; \ 119 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \ 120 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \ 121 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \ 122 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \ 123 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \ 124 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \ 125 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \ 126 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \ 127 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \ 128 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \ 129 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \ 130 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \ 131 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \ 132 st8 [_reg1]=r4,0x08;; \ 133 st8 [_reg1]=r5,0x08;; \ 134 st8 [_reg1]=r6,0x08;; \ 135 st8 [_reg1]=r7,0x08;; \ 136 st8 [_reg1]=_pred,0x08;; \ 137 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \ 138 stf.spill.nta [_reg1]=f2,16;; \ 139 stf.spill.nta [_reg1]=f3,16;; \ 140 stf.spill.nta [_reg1]=f4,16;; \ 141 stf.spill.nta [_reg1]=f5,16;; \ 142 stf.spill.nta [_reg1]=f16,16;; \ 143 stf.spill.nta [_reg1]=f17,16;; \ 144 stf.spill.nta [_reg1]=f18,16;; \ 145 stf.spill.nta [_reg1]=f19,16;; \ 146 stf.spill.nta [_reg1]=f20,16;; \ 147 stf.spill.nta [_reg1]=f21,16;; \ 148 stf.spill.nta [_reg1]=f22,16;; \ 149 stf.spill.nta [_reg1]=f23,16;; \ 150 stf.spill.nta [_reg1]=f24,16;; \ 151 stf.spill.nta [_reg1]=f25,16;; \ 152 stf.spill.nta [_reg1]=f26,16;; \ 153 stf.spill.nta [_reg1]=f27,16;; \ 154 stf.spill.nta [_reg1]=f28,16;; \ 155 stf.spill.nta [_reg1]=f29,16;; \ 156 stf.spill.nta [_reg1]=f30,16;; \ 157 stf.spill.nta [_reg1]=f31,16;; 158 159#else 160#define SET_AREA_FOR_BOOTING_CPU(a1, a2) 161#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3) 162#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) 163#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) 164#endif 165 166#define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \ 167 movl _tmp1=(num << 61);; \ 168 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \ 169 mov rr[_tmp1]=_tmp2 170 171 __PAGE_ALIGNED_DATA 172 173 .global empty_zero_page 174EXPORT_DATA_SYMBOL_GPL(empty_zero_page) 175empty_zero_page: 176 .skip PAGE_SIZE 177 178 .global swapper_pg_dir 179swapper_pg_dir: 180 .skip PAGE_SIZE 181 182 .rodata 183halt_msg: 184 stringz "Halting kernel\n" 185 186 __REF 187 188 .global start_ap 189 190 /* 191 * Start the kernel. When the bootloader passes control to _start(), r28 192 * points to the address of the boot parameter area. Execution reaches 193 * here in physical mode. 194 */ 195GLOBAL_ENTRY(_start) 196start_ap: 197 .prologue 198 .save rp, r0 // terminate unwind chain with a NULL rp 199 .body 200 201 rsm psr.i | psr.ic 202 ;; 203 srlz.i 204 ;; 205 { 206 flushrs // must be first insn in group 207 srlz.i 208 } 209 ;; 210 /* 211 * Save the region registers, predicate before they get clobbered 212 */ 213 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15); 214 mov r25=pr;; 215 216 /* 217 * Initialize kernel region registers: 218 * rr[0]: VHPT enabled, page size = PAGE_SHIFT 219 * rr[1]: VHPT enabled, page size = PAGE_SHIFT 220 * rr[2]: VHPT enabled, page size = PAGE_SHIFT 221 * rr[3]: VHPT enabled, page size = PAGE_SHIFT 222 * rr[4]: VHPT enabled, page size = PAGE_SHIFT 223 * rr[5]: VHPT enabled, page size = PAGE_SHIFT 224 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT 225 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT 226 * We initialize all of them to prevent inadvertently assuming 227 * something about the state of address translation early in boot. 228 */ 229 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);; 230 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);; 231 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);; 232 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);; 233 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);; 234 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);; 235 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);; 236 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);; 237 /* 238 * Now pin mappings into the TLB for kernel text and data 239 */ 240 mov r18=KERNEL_TR_PAGE_SHIFT<<2 241 movl r17=KERNEL_START 242 ;; 243 mov cr.itir=r18 244 mov cr.ifa=r17 245 mov r16=IA64_TR_KERNEL 246 mov r3=ip 247 movl r18=PAGE_KERNEL 248 ;; 249 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT 250 ;; 251 or r18=r2,r18 252 ;; 253 srlz.i 254 ;; 255 itr.i itr[r16]=r18 256 ;; 257 itr.d dtr[r16]=r18 258 ;; 259 srlz.i 260 261 /* 262 * Switch into virtual mode: 263 */ 264 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \ 265 |IA64_PSR_DI) 266 ;; 267 mov cr.ipsr=r16 268 movl r17=1f 269 ;; 270 mov cr.iip=r17 271 mov cr.ifs=r0 272 ;; 273 rfi 274 ;; 2751: // now we are in virtual mode 276 277 SET_AREA_FOR_BOOTING_CPU(r2, r16); 278 279 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15); 280 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25) 281 ;; 282 283 // set IVT entry point---can't access I/O ports without it 284 movl r3=ia64_ivt 285 ;; 286 mov cr.iva=r3 287 movl r2=FPSR_DEFAULT 288 ;; 289 srlz.i 290 movl gp=__gp 291 292 mov ar.fpsr=r2 293 ;; 294 295#define isAP p2 // are we an Application Processor? 296#define isBP p3 // are we the Bootstrap Processor? 297 298#ifdef CONFIG_SMP 299 /* 300 * Find the init_task for the currently booting CPU. At poweron, and in 301 * UP mode, task_for_booting_cpu is NULL. 302 */ 303 movl r3=task_for_booting_cpu 304 ;; 305 ld8 r3=[r3] 306 movl r2=init_task 307 ;; 308 cmp.eq isBP,isAP=r3,r0 309 ;; 310(isAP) mov r2=r3 311#else 312 movl r2=init_task 313 cmp.eq isBP,isAP=r0,r0 314#endif 315 ;; 316 tpa r3=r2 // r3 == phys addr of task struct 317 mov r16=-1 318(isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it 319 320 // load mapping for stack (virtaddr in r2, physaddr in r3) 321 rsm psr.ic 322 movl r17=PAGE_KERNEL 323 ;; 324 srlz.d 325 dep r18=0,r3,0,12 326 ;; 327 or r18=r17,r18 328 dep r2=-1,r3,61,3 // IMVA of task 329 ;; 330 mov r17=rr[r2] 331 shr.u r16=r3,IA64_GRANULE_SHIFT 332 ;; 333 dep r17=0,r17,8,24 334 ;; 335 mov cr.itir=r17 336 mov cr.ifa=r2 337 338 mov r19=IA64_TR_CURRENT_STACK 339 ;; 340 itr.d dtr[r19]=r18 341 ;; 342 ssm psr.ic 343 srlz.d 344 ;; 345 346.load_current: 347 // load the "current" pointer (r13) and ar.k6 with the current task 348 mov IA64_KR(CURRENT)=r2 // virtual address 349 mov IA64_KR(CURRENT_STACK)=r16 350 mov r13=r2 351 /* 352 * Reserve space at the top of the stack for "struct pt_regs". Kernel 353 * threads don't store interesting values in that structure, but the space 354 * still needs to be there because time-critical stuff such as the context 355 * switching can be implemented more efficiently (for example, __switch_to() 356 * always sets the psr.dfh bit of the task it is switching to). 357 */ 358 359 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2 360 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE 361 mov ar.rsc=0 // place RSE in enforced lazy mode 362 ;; 363 loadrs // clear the dirty partition 364 movl r19=__phys_per_cpu_start 365 mov r18=PERCPU_PAGE_SIZE 366 ;; 367#ifndef CONFIG_SMP 368 add r19=r19,r18 369 ;; 370#else 371(isAP) br.few 2f 372 movl r20=__cpu0_per_cpu 373 ;; 374 shr.u r18=r18,3 3751: 376 ld8 r21=[r19],8;; 377 st8[r20]=r21,8 378 adds r18=-1,r18;; 379 cmp4.lt p7,p6=0,r18 380(p7) br.cond.dptk.few 1b 381 mov r19=r20 382 ;; 3832: 384#endif 385 tpa r19=r19 386 ;; 387 .pred.rel.mutex isBP,isAP 388(isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0 389(isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base 390 ;; 391 mov ar.bspstore=r2 // establish the new RSE stack 392 ;; 393 mov ar.rsc=0x3 // place RSE in eager mode 394 395(isBP) dep r28=-1,r28,61,3 // make address virtual 396(isBP) movl r2=ia64_boot_param 397 ;; 398(isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader 399 400#ifdef CONFIG_SMP 401(isAP) br.call.sptk.many rp=start_secondary 402.ret0: 403(isAP) br.cond.sptk self 404#endif 405 406 // This is executed by the bootstrap processor (bsp) only: 407 408#ifdef CONFIG_IA64_FW_EMU 409 // initialize PAL & SAL emulator: 410 br.call.sptk.many rp=sys_fw_init 411.ret1: 412#endif 413 br.call.sptk.many rp=start_kernel 414.ret2: addl r3=@ltoff(halt_msg),gp 415 ;; 416 alloc r2=ar.pfs,8,0,2,0 417 ;; 418 ld8 out0=[r3] 419 br.call.sptk.many b0=console_print 420 421self: hint @pause 422 br.sptk.many self // endless loop 423END(_start) 424 425 .text 426 427GLOBAL_ENTRY(ia64_save_debug_regs) 428 alloc r16=ar.pfs,1,0,0,0 429 mov r20=ar.lc // preserve ar.lc 430 mov ar.lc=IA64_NUM_DBG_REGS-1 431 mov r18=0 432 add r19=IA64_NUM_DBG_REGS*8,in0 433 ;; 4341: mov r16=dbr[r18] 435#ifdef CONFIG_ITANIUM 436 ;; 437 srlz.d 438#endif 439 mov r17=ibr[r18] 440 add r18=1,r18 441 ;; 442 st8.nta [in0]=r16,8 443 st8.nta [r19]=r17,8 444 br.cloop.sptk.many 1b 445 ;; 446 mov ar.lc=r20 // restore ar.lc 447 br.ret.sptk.many rp 448END(ia64_save_debug_regs) 449 450GLOBAL_ENTRY(ia64_load_debug_regs) 451 alloc r16=ar.pfs,1,0,0,0 452 lfetch.nta [in0] 453 mov r20=ar.lc // preserve ar.lc 454 add r19=IA64_NUM_DBG_REGS*8,in0 455 mov ar.lc=IA64_NUM_DBG_REGS-1 456 mov r18=-1 457 ;; 4581: ld8.nta r16=[in0],8 459 ld8.nta r17=[r19],8 460 add r18=1,r18 461 ;; 462 mov dbr[r18]=r16 463#ifdef CONFIG_ITANIUM 464 ;; 465 srlz.d // Errata 132 (NoFix status) 466#endif 467 mov ibr[r18]=r17 468 br.cloop.sptk.many 1b 469 ;; 470 mov ar.lc=r20 // restore ar.lc 471 br.ret.sptk.many rp 472END(ia64_load_debug_regs) 473 474GLOBAL_ENTRY(__ia64_save_fpu) 475 alloc r2=ar.pfs,1,4,0,0 476 adds loc0=96*16-16,in0 477 adds loc1=96*16-16-128,in0 478 ;; 479 stf.spill.nta [loc0]=f127,-256 480 stf.spill.nta [loc1]=f119,-256 481 ;; 482 stf.spill.nta [loc0]=f111,-256 483 stf.spill.nta [loc1]=f103,-256 484 ;; 485 stf.spill.nta [loc0]=f95,-256 486 stf.spill.nta [loc1]=f87,-256 487 ;; 488 stf.spill.nta [loc0]=f79,-256 489 stf.spill.nta [loc1]=f71,-256 490 ;; 491 stf.spill.nta [loc0]=f63,-256 492 stf.spill.nta [loc1]=f55,-256 493 adds loc2=96*16-32,in0 494 ;; 495 stf.spill.nta [loc0]=f47,-256 496 stf.spill.nta [loc1]=f39,-256 497 adds loc3=96*16-32-128,in0 498 ;; 499 stf.spill.nta [loc2]=f126,-256 500 stf.spill.nta [loc3]=f118,-256 501 ;; 502 stf.spill.nta [loc2]=f110,-256 503 stf.spill.nta [loc3]=f102,-256 504 ;; 505 stf.spill.nta [loc2]=f94,-256 506 stf.spill.nta [loc3]=f86,-256 507 ;; 508 stf.spill.nta [loc2]=f78,-256 509 stf.spill.nta [loc3]=f70,-256 510 ;; 511 stf.spill.nta [loc2]=f62,-256 512 stf.spill.nta [loc3]=f54,-256 513 adds loc0=96*16-48,in0 514 ;; 515 stf.spill.nta [loc2]=f46,-256 516 stf.spill.nta [loc3]=f38,-256 517 adds loc1=96*16-48-128,in0 518 ;; 519 stf.spill.nta [loc0]=f125,-256 520 stf.spill.nta [loc1]=f117,-256 521 ;; 522 stf.spill.nta [loc0]=f109,-256 523 stf.spill.nta [loc1]=f101,-256 524 ;; 525 stf.spill.nta [loc0]=f93,-256 526 stf.spill.nta [loc1]=f85,-256 527 ;; 528 stf.spill.nta [loc0]=f77,-256 529 stf.spill.nta [loc1]=f69,-256 530 ;; 531 stf.spill.nta [loc0]=f61,-256 532 stf.spill.nta [loc1]=f53,-256 533 adds loc2=96*16-64,in0 534 ;; 535 stf.spill.nta [loc0]=f45,-256 536 stf.spill.nta [loc1]=f37,-256 537 adds loc3=96*16-64-128,in0 538 ;; 539 stf.spill.nta [loc2]=f124,-256 540 stf.spill.nta [loc3]=f116,-256 541 ;; 542 stf.spill.nta [loc2]=f108,-256 543 stf.spill.nta [loc3]=f100,-256 544 ;; 545 stf.spill.nta [loc2]=f92,-256 546 stf.spill.nta [loc3]=f84,-256 547 ;; 548 stf.spill.nta [loc2]=f76,-256 549 stf.spill.nta [loc3]=f68,-256 550 ;; 551 stf.spill.nta [loc2]=f60,-256 552 stf.spill.nta [loc3]=f52,-256 553 adds loc0=96*16-80,in0 554 ;; 555 stf.spill.nta [loc2]=f44,-256 556 stf.spill.nta [loc3]=f36,-256 557 adds loc1=96*16-80-128,in0 558 ;; 559 stf.spill.nta [loc0]=f123,-256 560 stf.spill.nta [loc1]=f115,-256 561 ;; 562 stf.spill.nta [loc0]=f107,-256 563 stf.spill.nta [loc1]=f99,-256 564 ;; 565 stf.spill.nta [loc0]=f91,-256 566 stf.spill.nta [loc1]=f83,-256 567 ;; 568 stf.spill.nta [loc0]=f75,-256 569 stf.spill.nta [loc1]=f67,-256 570 ;; 571 stf.spill.nta [loc0]=f59,-256 572 stf.spill.nta [loc1]=f51,-256 573 adds loc2=96*16-96,in0 574 ;; 575 stf.spill.nta [loc0]=f43,-256 576 stf.spill.nta [loc1]=f35,-256 577 adds loc3=96*16-96-128,in0 578 ;; 579 stf.spill.nta [loc2]=f122,-256 580 stf.spill.nta [loc3]=f114,-256 581 ;; 582 stf.spill.nta [loc2]=f106,-256 583 stf.spill.nta [loc3]=f98,-256 584 ;; 585 stf.spill.nta [loc2]=f90,-256 586 stf.spill.nta [loc3]=f82,-256 587 ;; 588 stf.spill.nta [loc2]=f74,-256 589 stf.spill.nta [loc3]=f66,-256 590 ;; 591 stf.spill.nta [loc2]=f58,-256 592 stf.spill.nta [loc3]=f50,-256 593 adds loc0=96*16-112,in0 594 ;; 595 stf.spill.nta [loc2]=f42,-256 596 stf.spill.nta [loc3]=f34,-256 597 adds loc1=96*16-112-128,in0 598 ;; 599 stf.spill.nta [loc0]=f121,-256 600 stf.spill.nta [loc1]=f113,-256 601 ;; 602 stf.spill.nta [loc0]=f105,-256 603 stf.spill.nta [loc1]=f97,-256 604 ;; 605 stf.spill.nta [loc0]=f89,-256 606 stf.spill.nta [loc1]=f81,-256 607 ;; 608 stf.spill.nta [loc0]=f73,-256 609 stf.spill.nta [loc1]=f65,-256 610 ;; 611 stf.spill.nta [loc0]=f57,-256 612 stf.spill.nta [loc1]=f49,-256 613 adds loc2=96*16-128,in0 614 ;; 615 stf.spill.nta [loc0]=f41,-256 616 stf.spill.nta [loc1]=f33,-256 617 adds loc3=96*16-128-128,in0 618 ;; 619 stf.spill.nta [loc2]=f120,-256 620 stf.spill.nta [loc3]=f112,-256 621 ;; 622 stf.spill.nta [loc2]=f104,-256 623 stf.spill.nta [loc3]=f96,-256 624 ;; 625 stf.spill.nta [loc2]=f88,-256 626 stf.spill.nta [loc3]=f80,-256 627 ;; 628 stf.spill.nta [loc2]=f72,-256 629 stf.spill.nta [loc3]=f64,-256 630 ;; 631 stf.spill.nta [loc2]=f56,-256 632 stf.spill.nta [loc3]=f48,-256 633 ;; 634 stf.spill.nta [loc2]=f40 635 stf.spill.nta [loc3]=f32 636 br.ret.sptk.many rp 637END(__ia64_save_fpu) 638 639GLOBAL_ENTRY(__ia64_load_fpu) 640 alloc r2=ar.pfs,1,2,0,0 641 adds r3=128,in0 642 adds r14=256,in0 643 adds r15=384,in0 644 mov loc0=512 645 mov loc1=-1024+16 646 ;; 647 ldf.fill.nta f32=[in0],loc0 648 ldf.fill.nta f40=[ r3],loc0 649 ldf.fill.nta f48=[r14],loc0 650 ldf.fill.nta f56=[r15],loc0 651 ;; 652 ldf.fill.nta f64=[in0],loc0 653 ldf.fill.nta f72=[ r3],loc0 654 ldf.fill.nta f80=[r14],loc0 655 ldf.fill.nta f88=[r15],loc0 656 ;; 657 ldf.fill.nta f96=[in0],loc1 658 ldf.fill.nta f104=[ r3],loc1 659 ldf.fill.nta f112=[r14],loc1 660 ldf.fill.nta f120=[r15],loc1 661 ;; 662 ldf.fill.nta f33=[in0],loc0 663 ldf.fill.nta f41=[ r3],loc0 664 ldf.fill.nta f49=[r14],loc0 665 ldf.fill.nta f57=[r15],loc0 666 ;; 667 ldf.fill.nta f65=[in0],loc0 668 ldf.fill.nta f73=[ r3],loc0 669 ldf.fill.nta f81=[r14],loc0 670 ldf.fill.nta f89=[r15],loc0 671 ;; 672 ldf.fill.nta f97=[in0],loc1 673 ldf.fill.nta f105=[ r3],loc1 674 ldf.fill.nta f113=[r14],loc1 675 ldf.fill.nta f121=[r15],loc1 676 ;; 677 ldf.fill.nta f34=[in0],loc0 678 ldf.fill.nta f42=[ r3],loc0 679 ldf.fill.nta f50=[r14],loc0 680 ldf.fill.nta f58=[r15],loc0 681 ;; 682 ldf.fill.nta f66=[in0],loc0 683 ldf.fill.nta f74=[ r3],loc0 684 ldf.fill.nta f82=[r14],loc0 685 ldf.fill.nta f90=[r15],loc0 686 ;; 687 ldf.fill.nta f98=[in0],loc1 688 ldf.fill.nta f106=[ r3],loc1 689 ldf.fill.nta f114=[r14],loc1 690 ldf.fill.nta f122=[r15],loc1 691 ;; 692 ldf.fill.nta f35=[in0],loc0 693 ldf.fill.nta f43=[ r3],loc0 694 ldf.fill.nta f51=[r14],loc0 695 ldf.fill.nta f59=[r15],loc0 696 ;; 697 ldf.fill.nta f67=[in0],loc0 698 ldf.fill.nta f75=[ r3],loc0 699 ldf.fill.nta f83=[r14],loc0 700 ldf.fill.nta f91=[r15],loc0 701 ;; 702 ldf.fill.nta f99=[in0],loc1 703 ldf.fill.nta f107=[ r3],loc1 704 ldf.fill.nta f115=[r14],loc1 705 ldf.fill.nta f123=[r15],loc1 706 ;; 707 ldf.fill.nta f36=[in0],loc0 708 ldf.fill.nta f44=[ r3],loc0 709 ldf.fill.nta f52=[r14],loc0 710 ldf.fill.nta f60=[r15],loc0 711 ;; 712 ldf.fill.nta f68=[in0],loc0 713 ldf.fill.nta f76=[ r3],loc0 714 ldf.fill.nta f84=[r14],loc0 715 ldf.fill.nta f92=[r15],loc0 716 ;; 717 ldf.fill.nta f100=[in0],loc1 718 ldf.fill.nta f108=[ r3],loc1 719 ldf.fill.nta f116=[r14],loc1 720 ldf.fill.nta f124=[r15],loc1 721 ;; 722 ldf.fill.nta f37=[in0],loc0 723 ldf.fill.nta f45=[ r3],loc0 724 ldf.fill.nta f53=[r14],loc0 725 ldf.fill.nta f61=[r15],loc0 726 ;; 727 ldf.fill.nta f69=[in0],loc0 728 ldf.fill.nta f77=[ r3],loc0 729 ldf.fill.nta f85=[r14],loc0 730 ldf.fill.nta f93=[r15],loc0 731 ;; 732 ldf.fill.nta f101=[in0],loc1 733 ldf.fill.nta f109=[ r3],loc1 734 ldf.fill.nta f117=[r14],loc1 735 ldf.fill.nta f125=[r15],loc1 736 ;; 737 ldf.fill.nta f38 =[in0],loc0 738 ldf.fill.nta f46 =[ r3],loc0 739 ldf.fill.nta f54 =[r14],loc0 740 ldf.fill.nta f62 =[r15],loc0 741 ;; 742 ldf.fill.nta f70 =[in0],loc0 743 ldf.fill.nta f78 =[ r3],loc0 744 ldf.fill.nta f86 =[r14],loc0 745 ldf.fill.nta f94 =[r15],loc0 746 ;; 747 ldf.fill.nta f102=[in0],loc1 748 ldf.fill.nta f110=[ r3],loc1 749 ldf.fill.nta f118=[r14],loc1 750 ldf.fill.nta f126=[r15],loc1 751 ;; 752 ldf.fill.nta f39 =[in0],loc0 753 ldf.fill.nta f47 =[ r3],loc0 754 ldf.fill.nta f55 =[r14],loc0 755 ldf.fill.nta f63 =[r15],loc0 756 ;; 757 ldf.fill.nta f71 =[in0],loc0 758 ldf.fill.nta f79 =[ r3],loc0 759 ldf.fill.nta f87 =[r14],loc0 760 ldf.fill.nta f95 =[r15],loc0 761 ;; 762 ldf.fill.nta f103=[in0] 763 ldf.fill.nta f111=[ r3] 764 ldf.fill.nta f119=[r14] 765 ldf.fill.nta f127=[r15] 766 br.ret.sptk.many rp 767END(__ia64_load_fpu) 768 769GLOBAL_ENTRY(__ia64_init_fpu) 770 stf.spill [sp]=f0 // M3 771 mov f32=f0 // F 772 nop.b 0 773 774 ldfps f33,f34=[sp] // M0 775 ldfps f35,f36=[sp] // M1 776 mov f37=f0 // F 777 ;; 778 779 setf.s f38=r0 // M2 780 setf.s f39=r0 // M3 781 mov f40=f0 // F 782 783 ldfps f41,f42=[sp] // M0 784 ldfps f43,f44=[sp] // M1 785 mov f45=f0 // F 786 787 setf.s f46=r0 // M2 788 setf.s f47=r0 // M3 789 mov f48=f0 // F 790 791 ldfps f49,f50=[sp] // M0 792 ldfps f51,f52=[sp] // M1 793 mov f53=f0 // F 794 795 setf.s f54=r0 // M2 796 setf.s f55=r0 // M3 797 mov f56=f0 // F 798 799 ldfps f57,f58=[sp] // M0 800 ldfps f59,f60=[sp] // M1 801 mov f61=f0 // F 802 803 setf.s f62=r0 // M2 804 setf.s f63=r0 // M3 805 mov f64=f0 // F 806 807 ldfps f65,f66=[sp] // M0 808 ldfps f67,f68=[sp] // M1 809 mov f69=f0 // F 810 811 setf.s f70=r0 // M2 812 setf.s f71=r0 // M3 813 mov f72=f0 // F 814 815 ldfps f73,f74=[sp] // M0 816 ldfps f75,f76=[sp] // M1 817 mov f77=f0 // F 818 819 setf.s f78=r0 // M2 820 setf.s f79=r0 // M3 821 mov f80=f0 // F 822 823 ldfps f81,f82=[sp] // M0 824 ldfps f83,f84=[sp] // M1 825 mov f85=f0 // F 826 827 setf.s f86=r0 // M2 828 setf.s f87=r0 // M3 829 mov f88=f0 // F 830 831 /* 832 * When the instructions are cached, it would be faster to initialize 833 * the remaining registers with simply mov instructions (F-unit). 834 * This gets the time down to ~29 cycles. However, this would use up 835 * 33 bundles, whereas continuing with the above pattern yields 836 * 10 bundles and ~30 cycles. 837 */ 838 839 ldfps f89,f90=[sp] // M0 840 ldfps f91,f92=[sp] // M1 841 mov f93=f0 // F 842 843 setf.s f94=r0 // M2 844 setf.s f95=r0 // M3 845 mov f96=f0 // F 846 847 ldfps f97,f98=[sp] // M0 848 ldfps f99,f100=[sp] // M1 849 mov f101=f0 // F 850 851 setf.s f102=r0 // M2 852 setf.s f103=r0 // M3 853 mov f104=f0 // F 854 855 ldfps f105,f106=[sp] // M0 856 ldfps f107,f108=[sp] // M1 857 mov f109=f0 // F 858 859 setf.s f110=r0 // M2 860 setf.s f111=r0 // M3 861 mov f112=f0 // F 862 863 ldfps f113,f114=[sp] // M0 864 ldfps f115,f116=[sp] // M1 865 mov f117=f0 // F 866 867 setf.s f118=r0 // M2 868 setf.s f119=r0 // M3 869 mov f120=f0 // F 870 871 ldfps f121,f122=[sp] // M0 872 ldfps f123,f124=[sp] // M1 873 mov f125=f0 // F 874 875 setf.s f126=r0 // M2 876 setf.s f127=r0 // M3 877 br.ret.sptk.many rp // F 878END(__ia64_init_fpu) 879 880/* 881 * Switch execution mode from virtual to physical 882 * 883 * Inputs: 884 * r16 = new psr to establish 885 * Output: 886 * r19 = old virtual address of ar.bsp 887 * r20 = old virtual address of sp 888 * 889 * Note: RSE must already be in enforced lazy mode 890 */ 891GLOBAL_ENTRY(ia64_switch_mode_phys) 892 { 893 rsm psr.i | psr.ic // disable interrupts and interrupt collection 894 mov r15=ip 895 } 896 ;; 897 { 898 flushrs // must be first insn in group 899 srlz.i 900 } 901 ;; 902 mov cr.ipsr=r16 // set new PSR 903 add r3=1f-ia64_switch_mode_phys,r15 904 905 mov r19=ar.bsp 906 mov r20=sp 907 mov r14=rp // get return address into a general register 908 ;; 909 910 // going to physical mode, use tpa to translate virt->phys 911 tpa r17=r19 912 tpa r3=r3 913 tpa sp=sp 914 tpa r14=r14 915 ;; 916 917 mov r18=ar.rnat // save ar.rnat 918 mov ar.bspstore=r17 // this steps on ar.rnat 919 mov cr.iip=r3 920 mov cr.ifs=r0 921 ;; 922 mov ar.rnat=r18 // restore ar.rnat 923 rfi // must be last insn in group 924 ;; 9251: mov rp=r14 926 br.ret.sptk.many rp 927END(ia64_switch_mode_phys) 928 929/* 930 * Switch execution mode from physical to virtual 931 * 932 * Inputs: 933 * r16 = new psr to establish 934 * r19 = new bspstore to establish 935 * r20 = new sp to establish 936 * 937 * Note: RSE must already be in enforced lazy mode 938 */ 939GLOBAL_ENTRY(ia64_switch_mode_virt) 940 { 941 rsm psr.i | psr.ic // disable interrupts and interrupt collection 942 mov r15=ip 943 } 944 ;; 945 { 946 flushrs // must be first insn in group 947 srlz.i 948 } 949 ;; 950 mov cr.ipsr=r16 // set new PSR 951 add r3=1f-ia64_switch_mode_virt,r15 952 953 mov r14=rp // get return address into a general register 954 ;; 955 956 // going to virtual 957 // - for code addresses, set upper bits of addr to KERNEL_START 958 // - for stack addresses, copy from input argument 959 movl r18=KERNEL_START 960 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT 961 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT 962 mov sp=r20 963 ;; 964 or r3=r3,r18 965 or r14=r14,r18 966 ;; 967 968 mov r18=ar.rnat // save ar.rnat 969 mov ar.bspstore=r19 // this steps on ar.rnat 970 mov cr.iip=r3 971 mov cr.ifs=r0 972 ;; 973 mov ar.rnat=r18 // restore ar.rnat 974 rfi // must be last insn in group 975 ;; 9761: mov rp=r14 977 br.ret.sptk.many rp 978END(ia64_switch_mode_virt) 979 980GLOBAL_ENTRY(ia64_delay_loop) 981 .prologue 982{ nop 0 // work around GAS unwind info generation bug... 983 .save ar.lc,r2 984 mov r2=ar.lc 985 .body 986 ;; 987 mov ar.lc=r32 988} 989 ;; 990 // force loop to be 32-byte aligned (GAS bug means we cannot use .align 991 // inside function body without corrupting unwind info). 992{ nop 0 } 9931: br.cloop.sptk.few 1b 994 ;; 995 mov ar.lc=r2 996 br.ret.sptk.many rp 997END(ia64_delay_loop) 998 999/* 1000 * Return a CPU-local timestamp in nano-seconds. This timestamp is 1001 * NOT synchronized across CPUs its return value must never be 1002 * compared against the values returned on another CPU. The usage in 1003 * kernel/sched/core.c ensures that. 1004 * 1005 * The return-value of sched_clock() is NOT supposed to wrap-around. 1006 * If it did, it would cause some scheduling hiccups (at the worst). 1007 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even 1008 * that would happen only once every 5+ years. 1009 * 1010 * The code below basically calculates: 1011 * 1012 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT 1013 * 1014 * except that the multiplication and the shift are done with 128-bit 1015 * intermediate precision so that we can produce a full 64-bit result. 1016 */ 1017GLOBAL_ENTRY(ia64_native_sched_clock) 1018 addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0 1019 mov.m r9=ar.itc // fetch cycle-counter (35 cyc) 1020 ;; 1021 ldf8 f8=[r8] 1022 ;; 1023 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8... 1024 ;; 1025 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc) 1026 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product 1027 ;; 1028 getf.sig r8=f10 // (5 cyc) 1029 getf.sig r9=f11 1030 ;; 1031 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT 1032 br.ret.sptk.many rp 1033END(ia64_native_sched_clock) 1034 1035#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 1036GLOBAL_ENTRY(cycle_to_nsec) 1037 alloc r16=ar.pfs,1,0,0,0 1038 addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0 1039 ;; 1040 ldf8 f8=[r8] 1041 ;; 1042 setf.sig f9=r32 1043 ;; 1044 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc) 1045 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product 1046 ;; 1047 getf.sig r8=f10 // (5 cyc) 1048 getf.sig r9=f11 1049 ;; 1050 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT 1051 br.ret.sptk.many rp 1052END(cycle_to_nsec) 1053#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 1054 1055#ifdef CONFIG_IA64_BRL_EMU 1056 1057/* 1058 * Assembly routines used by brl_emu.c to set preserved register state. 1059 */ 1060 1061#define SET_REG(reg) \ 1062 GLOBAL_ENTRY(ia64_set_##reg); \ 1063 alloc r16=ar.pfs,1,0,0,0; \ 1064 mov reg=r32; \ 1065 ;; \ 1066 br.ret.sptk.many rp; \ 1067 END(ia64_set_##reg) 1068 1069SET_REG(b1); 1070SET_REG(b2); 1071SET_REG(b3); 1072SET_REG(b4); 1073SET_REG(b5); 1074 1075#endif /* CONFIG_IA64_BRL_EMU */ 1076 1077#ifdef CONFIG_SMP 1078 1079#ifdef CONFIG_HOTPLUG_CPU 1080GLOBAL_ENTRY(ia64_jump_to_sal) 1081 alloc r16=ar.pfs,1,0,0,0;; 1082 rsm psr.i | psr.ic 1083{ 1084 flushrs 1085 srlz.i 1086} 1087 tpa r25=in0 1088 movl r18=tlb_purge_done;; 1089 DATA_VA_TO_PA(r18);; 1090 mov b1=r18 // Return location 1091 movl r18=ia64_do_tlb_purge;; 1092 DATA_VA_TO_PA(r18);; 1093 mov b2=r18 // doing tlb_flush work 1094 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode 1095 movl r17=1f;; 1096 DATA_VA_TO_PA(r17);; 1097 mov cr.iip=r17 1098 movl r16=SAL_PSR_BITS_TO_SET;; 1099 mov cr.ipsr=r16 1100 mov cr.ifs=r0;; 1101 rfi;; // note: this unmask MCA/INIT (psr.mc) 11021: 1103 /* 1104 * Invalidate all TLB data/inst 1105 */ 1106 br.sptk.many b2;; // jump to tlb purge code 1107 1108tlb_purge_done: 1109 RESTORE_REGION_REGS(r25, r17,r18,r19);; 1110 RESTORE_REG(b0, r25, r17);; 1111 RESTORE_REG(b1, r25, r17);; 1112 RESTORE_REG(b2, r25, r17);; 1113 RESTORE_REG(b3, r25, r17);; 1114 RESTORE_REG(b4, r25, r17);; 1115 RESTORE_REG(b5, r25, r17);; 1116 ld8 r1=[r25],0x08;; 1117 ld8 r12=[r25],0x08;; 1118 ld8 r13=[r25],0x08;; 1119 RESTORE_REG(ar.fpsr, r25, r17);; 1120 RESTORE_REG(ar.pfs, r25, r17);; 1121 RESTORE_REG(ar.rnat, r25, r17);; 1122 RESTORE_REG(ar.unat, r25, r17);; 1123 RESTORE_REG(ar.bspstore, r25, r17);; 1124 RESTORE_REG(cr.dcr, r25, r17);; 1125 RESTORE_REG(cr.iva, r25, r17);; 1126 RESTORE_REG(cr.pta, r25, r17);; 1127 srlz.d;; // required not to violate RAW dependency 1128 RESTORE_REG(cr.itv, r25, r17);; 1129 RESTORE_REG(cr.pmv, r25, r17);; 1130 RESTORE_REG(cr.cmcv, r25, r17);; 1131 RESTORE_REG(cr.lrr0, r25, r17);; 1132 RESTORE_REG(cr.lrr1, r25, r17);; 1133 ld8 r4=[r25],0x08;; 1134 ld8 r5=[r25],0x08;; 1135 ld8 r6=[r25],0x08;; 1136 ld8 r7=[r25],0x08;; 1137 ld8 r17=[r25],0x08;; 1138 mov pr=r17,-1;; 1139 RESTORE_REG(ar.lc, r25, r17);; 1140 /* 1141 * Now Restore floating point regs 1142 */ 1143 ldf.fill.nta f2=[r25],16;; 1144 ldf.fill.nta f3=[r25],16;; 1145 ldf.fill.nta f4=[r25],16;; 1146 ldf.fill.nta f5=[r25],16;; 1147 ldf.fill.nta f16=[r25],16;; 1148 ldf.fill.nta f17=[r25],16;; 1149 ldf.fill.nta f18=[r25],16;; 1150 ldf.fill.nta f19=[r25],16;; 1151 ldf.fill.nta f20=[r25],16;; 1152 ldf.fill.nta f21=[r25],16;; 1153 ldf.fill.nta f22=[r25],16;; 1154 ldf.fill.nta f23=[r25],16;; 1155 ldf.fill.nta f24=[r25],16;; 1156 ldf.fill.nta f25=[r25],16;; 1157 ldf.fill.nta f26=[r25],16;; 1158 ldf.fill.nta f27=[r25],16;; 1159 ldf.fill.nta f28=[r25],16;; 1160 ldf.fill.nta f29=[r25],16;; 1161 ldf.fill.nta f30=[r25],16;; 1162 ldf.fill.nta f31=[r25],16;; 1163 1164 /* 1165 * Now that we have done all the register restores 1166 * we are now ready for the big DIVE to SAL Land 1167 */ 1168 ssm psr.ic;; 1169 srlz.d;; 1170 br.ret.sptk.many b0;; 1171END(ia64_jump_to_sal) 1172#endif /* CONFIG_HOTPLUG_CPU */ 1173 1174#endif /* CONFIG_SMP */ 1175
