1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
5 */
6
7#include "imx8mm.dtsi"
8
9/ {
10	model = "Variscite VAR-SOM-MX8MM module";
11	compatible = "variscite,var-som-mx8mm", "fsl,imx8mm";
12
13	chosen {
14		stdout-path = &uart4;
15	};
16
17	memory@40000000 {
18		device_type = "memory";
19		reg = <0x0 0x40000000 0 0x80000000>;
20	};
21
22	reg_eth_phy: regulator-eth-phy {
23		compatible = "regulator-fixed";
24		pinctrl-names = "default";
25		pinctrl-0 = <&pinctrl_reg_eth_phy>;
26		regulator-name = "eth_phy_pwr";
27		regulator-min-microvolt = <3300000>;
28		regulator-max-microvolt = <3300000>;
29		gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
30		enable-active-high;
31	};
32};
33
34&A53_0 {
35	cpu-supply = <&buck2_reg>;
36};
37
38&A53_1 {
39	cpu-supply = <&buck2_reg>;
40};
41
42&A53_2 {
43	cpu-supply = <&buck2_reg>;
44};
45
46&A53_3 {
47	cpu-supply = <&buck2_reg>;
48};
49
50&ddrc {
51	operating-points-v2 = <&ddrc_opp_table>;
52
53	ddrc_opp_table: opp-table {
54		compatible = "operating-points-v2";
55
56		opp-25M {
57			opp-hz = /bits/ 64 <25000000>;
58		};
59
60		opp-100M {
61			opp-hz = /bits/ 64 <100000000>;
62		};
63
64		opp-750M {
65			opp-hz = /bits/ 64 <750000000>;
66		};
67	};
68};
69
70&ecspi1 {
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_ecspi1>;
73	cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
74		   <&gpio1  0 GPIO_ACTIVE_LOW>;
75	/delete-property/ dmas;
76	/delete-property/ dma-names;
77	status = "okay";
78
79	/* Resistive touch controller */
80	touchscreen@0 {
81		reg = <0>;
82		compatible = "ti,ads7846";
83		pinctrl-names = "default";
84		pinctrl-0 = <&pinctrl_restouch>;
85		interrupt-parent = <&gpio1>;
86		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
87
88		spi-max-frequency = <1500000>;
89		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
90
91		ti,x-min = /bits/ 16 <125>;
92		touchscreen-size-x = /bits/ 16 <4008>;
93		ti,y-min = /bits/ 16 <282>;
94		touchscreen-size-y = /bits/ 16 <3864>;
95		ti,x-plate-ohms = /bits/ 16 <180>;
96		touchscreen-max-pressure = /bits/ 16 <255>;
97		touchscreen-average-samples = /bits/ 16 <10>;
98		ti,debounce-tol = /bits/ 16 <3>;
99		ti,debounce-rep = /bits/ 16 <1>;
100		ti,settle-delay-usec = /bits/ 16 <150>;
101		ti,keep-vref-on;
102		wakeup-source;
103	};
104};
105
106&fec1 {
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_fec1>;
109	phy-mode = "rgmii";
110	phy-handle = <&ethphy>;
111	phy-supply = <&reg_eth_phy>;
112	fsl,magic-packet;
113	status = "okay";
114
115	mdio {
116		#address-cells = <1>;
117		#size-cells = <0>;
118
119		ethphy: ethernet-phy@4 {
120			compatible = "ethernet-phy-ieee802.3-c22";
121			reg = <4>;
122			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
123			reset-assert-us = <10000>;
124			reset-deassert-us = <10000>;
125		};
126	};
127};
128
129&i2c1 {
130	clock-frequency = <400000>;
131	pinctrl-names = "default";
132	pinctrl-0 = <&pinctrl_i2c1>;
133	status = "okay";
134
135	pmic@4b {
136		compatible = "rohm,bd71847";
137		reg = <0x4b>;
138		pinctrl-names = "default";
139		pinctrl-0 = <&pinctrl_pmic>;
140		interrupt-parent = <&gpio2>;
141		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
142		rohm,reset-snvs-powered;
143
144		#clock-cells = <0>;
145		clocks = <&osc_32k 0>;
146		clock-output-names = "clk-32k-out";
147
148		regulators {
149			buck1_reg: BUCK1 {
150				regulator-name = "buck1";
151				regulator-min-microvolt = <700000>;
152				regulator-max-microvolt = <1300000>;
153				regulator-boot-on;
154				regulator-always-on;
155				regulator-ramp-delay = <1250>;
156			};
157
158			buck2_reg: BUCK2 {
159				regulator-name = "buck2";
160				regulator-min-microvolt = <700000>;
161				regulator-max-microvolt = <1300000>;
162				regulator-boot-on;
163				regulator-always-on;
164				regulator-ramp-delay = <1250>;
165				rohm,dvs-run-voltage = <1000000>;
166				rohm,dvs-idle-voltage = <900000>;
167			};
168
169			buck3_reg: BUCK3 {
170				regulator-name = "buck3";
171				regulator-min-microvolt = <700000>;
172				regulator-max-microvolt = <1350000>;
173				regulator-boot-on;
174				regulator-always-on;
175			};
176
177			buck4_reg: BUCK4 {
178				regulator-name = "buck4";
179				regulator-min-microvolt = <3000000>;
180				regulator-max-microvolt = <3300000>;
181				regulator-boot-on;
182				regulator-always-on;
183			};
184
185			buck5_reg: BUCK5 {
186				regulator-name = "buck5";
187				regulator-min-microvolt = <1605000>;
188				regulator-max-microvolt = <1995000>;
189				regulator-boot-on;
190				regulator-always-on;
191			};
192
193			buck6_reg: BUCK6 {
194				regulator-name = "buck6";
195				regulator-min-microvolt = <800000>;
196				regulator-max-microvolt = <1400000>;
197				regulator-boot-on;
198				regulator-always-on;
199			};
200
201			ldo1_reg: LDO1 {
202				regulator-name = "ldo1";
203				regulator-min-microvolt = <1600000>;
204				regulator-max-microvolt = <1900000>;
205				regulator-boot-on;
206				regulator-always-on;
207			};
208
209			ldo2_reg: LDO2 {
210				regulator-name = "ldo2";
211				regulator-min-microvolt = <800000>;
212				regulator-max-microvolt = <900000>;
213				regulator-boot-on;
214				regulator-always-on;
215			};
216
217			ldo3_reg: LDO3 {
218				regulator-name = "ldo3";
219				regulator-min-microvolt = <1800000>;
220				regulator-max-microvolt = <3300000>;
221				regulator-boot-on;
222				regulator-always-on;
223			};
224
225			ldo4_reg: LDO4 {
226				regulator-name = "ldo4";
227				regulator-min-microvolt = <900000>;
228				regulator-max-microvolt = <1800000>;
229				regulator-boot-on;
230				regulator-always-on;
231			};
232
233			ldo5_reg: LDO5 {
234				regulator-compatible = "ldo5";
235				regulator-min-microvolt = <1800000>;
236				regulator-max-microvolt = <1800000>;
237				regulator-always-on;
238			};
239
240			ldo6_reg: LDO6 {
241				regulator-name = "ldo6";
242				regulator-min-microvolt = <900000>;
243				regulator-max-microvolt = <1800000>;
244				regulator-boot-on;
245				regulator-always-on;
246			};
247		};
248	};
249};
250
251&i2c3 {
252	clock-frequency = <400000>;
253	pinctrl-names = "default";
254	pinctrl-0 = <&pinctrl_i2c3>;
255	status = "okay";
256
257	/* TODO: configure audio, as of now just put a placeholder */
258	wm8904: codec@1a {
259		compatible = "wlf,wm8904";
260		reg = <0x1a>;
261		status = "disabled";
262	};
263};
264
265&snvs_pwrkey {
266	status = "okay";
267};
268
269/* Bluetooth */
270&uart2 {
271	pinctrl-names = "default";
272	pinctrl-0 = <&pinctrl_uart2>;
273	assigned-clocks = <&clk IMX8MM_CLK_UART2>;
274	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
275	uart-has-rtscts;
276	status = "okay";
277};
278
279/* Console */
280&uart4 {
281	pinctrl-names = "default";
282	pinctrl-0 = <&pinctrl_uart4>;
283	status = "okay";
284};
285
286&usbotg1 {
287	dr_mode = "otg";
288	usb-role-switch;
289	status = "okay";
290};
291
292&usbotg2 {
293	dr_mode = "otg";
294	usb-role-switch;
295	status = "okay";
296};
297
298/* WIFI */
299&usdhc1 {
300	#address-cells = <1>;
301	#size-cells = <0>;
302	pinctrl-names = "default", "state_100mhz", "state_200mhz";
303	pinctrl-0 = <&pinctrl_usdhc1>;
304	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
305	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
306	bus-width = <4>;
307	non-removable;
308	keep-power-in-suspend;
309	status = "okay";
310
311	brcmf: bcrmf@1 {
312		reg = <1>;
313		compatible = "brcm,bcm4329-fmac";
314	};
315};
316
317/* SD */
318&usdhc2 {
319	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
320	assigned-clock-rates = <200000000>;
321	pinctrl-names = "default", "state_100mhz", "state_200mhz";
322	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
323	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
324	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
325	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
326	bus-width = <4>;
327	vmmc-supply = <&reg_usdhc2_vmmc>;
328	status = "okay";
329};
330
331/* eMMC */
332&usdhc3 {
333	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
334	assigned-clock-rates = <400000000>;
335	pinctrl-names = "default", "state_100mhz", "state_200mhz";
336	pinctrl-0 = <&pinctrl_usdhc3>;
337	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
338	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
339	bus-width = <8>;
340	non-removable;
341	status = "okay";
342};
343
344&wdog1 {
345	pinctrl-names = "default";
346	pinctrl-0 = <&pinctrl_wdog>;
347	fsl,ext-reset-output;
348	status = "okay";
349};
350
351&iomuxc {
352	pinctrl_ecspi1: ecspi1grp {
353		fsl,pins = <
354			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
355			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
356			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
357			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x13
358			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x13
359		>;
360	};
361
362	pinctrl_fec1: fec1grp {
363		fsl,pins = <
364			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
365			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
366			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
367			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
368			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
369			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
370			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
371			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
372			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
373			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
374			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
375			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
376			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
377			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
378			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
379		>;
380	};
381
382	pinctrl_i2c1: i2c1grp {
383		fsl,pins = <
384			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
385			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
386		>;
387	};
388
389	pinctrl_i2c3: i2c3grp {
390		fsl,pins = <
391			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
392			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
393		>;
394	};
395
396	pinctrl_pmic: pmicirqgrp {
397		fsl,pins = <
398			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x141
399		>;
400	};
401
402	pinctrl_reg_eth_phy: regethphygrp {
403		fsl,pins = <
404			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9	0x41
405		>;
406	};
407
408	pinctrl_restouch: restouchgrp {
409		fsl,pins = <
410			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x1c0
411		>;
412	};
413
414	pinctrl_uart2: uart2grp {
415		fsl,pins = <
416			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140
417			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140
418			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140
419			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140
420		>;
421	};
422
423	pinctrl_uart4: uart4grp {
424		fsl,pins = <
425			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
426			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
427		>;
428	};
429
430	pinctrl_usdhc1: usdhc1grp {
431		fsl,pins = <
432			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
433			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
434			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
435			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
436			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
437			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
438		>;
439	};
440
441	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
442		fsl,pins = <
443			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
444			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
445			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
446			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
447			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
448			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
449		>;
450	};
451
452	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
453		fsl,pins = <
454			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
455			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
456			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
457			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
458			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
459			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
460		>;
461	};
462
463	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
464		fsl,pins = <
465			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0xc1
466		>;
467	};
468
469	pinctrl_usdhc2: usdhc2grp {
470		fsl,pins = <
471			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
472			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
473			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
474			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
475			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
476			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
477			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
478		>;
479	};
480
481	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
482		fsl,pins = <
483			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
484			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
485			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
486			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
487			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
488			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
489			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
490		>;
491	};
492
493	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
494		fsl,pins = <
495			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
496			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
497			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
498			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
499			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
500			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
501			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
502		>;
503	};
504
505	pinctrl_usdhc3: usdhc3grp {
506		fsl,pins = <
507			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
508			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
509			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
510			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
511			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
512			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
513			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
514			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
515			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
516			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
517			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
518		>;
519	};
520
521	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
522		fsl,pins = <
523			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
524			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
525			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
526			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
527			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
528			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
529			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
530			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
531			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
532			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
533			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
534		>;
535	};
536
537	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
538		fsl,pins = <
539			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
540			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
541			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
542			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
543			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
544			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
545			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
546			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
547			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
548			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
549			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
550		>;
551	};
552
553	pinctrl_wdog: wdoggrp {
554		fsl,pins = <
555			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
556		>;
557	};
558};
559