1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mm.dtsi"
10
11/ {
12	chosen {
13		stdout-path = &uart2;
14	};
15
16	memory@40000000 {
17		device_type = "memory";
18		reg = <0x0 0x40000000 0 0x80000000>;
19	};
20
21	leds {
22		compatible = "gpio-leds";
23		pinctrl-names = "default";
24		pinctrl-0 = <&pinctrl_gpio_led>;
25
26		status {
27			label = "status";
28			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
29			default-state = "on";
30		};
31	};
32
33	reg_usdhc2_vmmc: regulator-usdhc2 {
34		compatible = "regulator-fixed";
35		pinctrl-names = "default";
36		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
37		regulator-name = "VSD_3V3";
38		regulator-min-microvolt = <3300000>;
39		regulator-max-microvolt = <3300000>;
40		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
41		enable-active-high;
42	};
43
44	wm8524: audio-codec {
45		#sound-dai-cells = <0>;
46		compatible = "wlf,wm8524";
47		pinctrl-names = "default";
48		pinctrl-0 = <&pinctrl_gpio_wlf>;
49		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
50	};
51
52	sound-wm8524 {
53		compatible = "simple-audio-card";
54		simple-audio-card,name = "wm8524-audio";
55		simple-audio-card,format = "i2s";
56		simple-audio-card,frame-master = <&cpudai>;
57		simple-audio-card,bitclock-master = <&cpudai>;
58		simple-audio-card,widgets =
59			"Line", "Left Line Out Jack",
60			"Line", "Right Line Out Jack";
61		simple-audio-card,routing =
62			"Left Line Out Jack", "LINEVOUTL",
63			"Right Line Out Jack", "LINEVOUTR";
64
65		cpudai: simple-audio-card,cpu {
66			sound-dai = <&sai3>;
67			dai-tdm-slot-num = <2>;
68			dai-tdm-slot-width = <32>;
69		};
70
71		simple-audio-card,codec {
72			sound-dai = <&wm8524>;
73			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
74		};
75	};
76};
77
78&A53_0 {
79	cpu-supply = <&buck2_reg>;
80};
81
82&A53_1 {
83	cpu-supply = <&buck2_reg>;
84};
85
86&A53_2 {
87	cpu-supply = <&buck2_reg>;
88};
89
90&A53_3 {
91	cpu-supply = <&buck2_reg>;
92};
93
94&fec1 {
95	pinctrl-names = "default";
96	pinctrl-0 = <&pinctrl_fec1>;
97	phy-mode = "rgmii-id";
98	phy-handle = <&ethphy0>;
99	fsl,magic-packet;
100	status = "okay";
101
102	mdio {
103		#address-cells = <1>;
104		#size-cells = <0>;
105
106		ethphy0: ethernet-phy@0 {
107			compatible = "ethernet-phy-ieee802.3-c22";
108			reg = <0>;
109			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
110			reset-assert-us = <10000>;
111		};
112	};
113};
114
115&i2c1 {
116	clock-frequency = <400000>;
117	pinctrl-names = "default";
118	pinctrl-0 = <&pinctrl_i2c1>;
119	status = "okay";
120
121	pmic@4b {
122		compatible = "rohm,bd71847";
123		reg = <0x4b>;
124		pinctrl-names = "default";
125		pinctrl-0 = <&pinctrl_pmic>;
126		interrupt-parent = <&gpio1>;
127		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
128		rohm,reset-snvs-powered;
129
130		#clock-cells = <0>;
131		clocks = <&osc_32k 0>;
132		clock-output-names = "clk-32k-out";
133
134		regulators {
135			buck1_reg: BUCK1 {
136				regulator-name = "buck1";
137				regulator-min-microvolt = <700000>;
138				regulator-max-microvolt = <1300000>;
139				regulator-boot-on;
140				regulator-always-on;
141				regulator-ramp-delay = <1250>;
142			};
143
144			buck2_reg: BUCK2 {
145				regulator-name = "buck2";
146				regulator-min-microvolt = <700000>;
147				regulator-max-microvolt = <1300000>;
148				regulator-boot-on;
149				regulator-always-on;
150				regulator-ramp-delay = <1250>;
151				rohm,dvs-run-voltage = <1000000>;
152				rohm,dvs-idle-voltage = <900000>;
153			};
154
155			buck3_reg: BUCK3 {
156				// BUCK5 in datasheet
157				regulator-name = "buck3";
158				regulator-min-microvolt = <700000>;
159				regulator-max-microvolt = <1350000>;
160				regulator-boot-on;
161				regulator-always-on;
162			};
163
164			buck4_reg: BUCK4 {
165				// BUCK6 in datasheet
166				regulator-name = "buck4";
167				regulator-min-microvolt = <3000000>;
168				regulator-max-microvolt = <3300000>;
169				regulator-boot-on;
170				regulator-always-on;
171			};
172
173			buck5_reg: BUCK5 {
174				// BUCK7 in datasheet
175				regulator-name = "buck5";
176				regulator-min-microvolt = <1605000>;
177				regulator-max-microvolt = <1995000>;
178				regulator-boot-on;
179				regulator-always-on;
180			};
181
182			buck6_reg: BUCK6 {
183				// BUCK8 in datasheet
184				regulator-name = "buck6";
185				regulator-min-microvolt = <800000>;
186				regulator-max-microvolt = <1400000>;
187				regulator-boot-on;
188				regulator-always-on;
189			};
190
191			ldo1_reg: LDO1 {
192				regulator-name = "ldo1";
193				regulator-min-microvolt = <1600000>;
194				regulator-max-microvolt = <3300000>;
195				regulator-boot-on;
196				regulator-always-on;
197			};
198
199			ldo2_reg: LDO2 {
200				regulator-name = "ldo2";
201				regulator-min-microvolt = <800000>;
202				regulator-max-microvolt = <900000>;
203				regulator-boot-on;
204				regulator-always-on;
205			};
206
207			ldo3_reg: LDO3 {
208				regulator-name = "ldo3";
209				regulator-min-microvolt = <1800000>;
210				regulator-max-microvolt = <3300000>;
211				regulator-boot-on;
212				regulator-always-on;
213			};
214
215			ldo4_reg: LDO4 {
216				regulator-name = "ldo4";
217				regulator-min-microvolt = <900000>;
218				regulator-max-microvolt = <1800000>;
219				regulator-boot-on;
220				regulator-always-on;
221			};
222
223			ldo6_reg: LDO6 {
224				regulator-name = "ldo6";
225				regulator-min-microvolt = <900000>;
226				regulator-max-microvolt = <1800000>;
227				regulator-boot-on;
228				regulator-always-on;
229			};
230		};
231	};
232};
233
234&i2c2 {
235	clock-frequency = <400000>;
236	pinctrl-names = "default";
237	pinctrl-0 = <&pinctrl_i2c2>;
238	status = "okay";
239
240	ptn5110: tcpc@50 {
241		compatible = "nxp,ptn5110";
242		pinctrl-names = "default";
243		pinctrl-0 = <&pinctrl_typec1>;
244		reg = <0x50>;
245		interrupt-parent = <&gpio2>;
246		interrupts = <11 8>;
247		status = "okay";
248
249		port {
250			typec1_dr_sw: endpoint {
251				remote-endpoint = <&usb1_drd_sw>;
252			};
253		};
254
255		typec1_con: connector {
256			compatible = "usb-c-connector";
257			label = "USB-C";
258			power-role = "dual";
259			data-role = "dual";
260			try-power-role = "sink";
261			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
262			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
263				     PDO_VAR(5000, 20000, 3000)>;
264			op-sink-microwatt = <15000000>;
265			self-powered;
266		};
267	};
268};
269
270&i2c3 {
271	clock-frequency = <400000>;
272	pinctrl-names = "default";
273	pinctrl-0 = <&pinctrl_i2c3>;
274	status = "okay";
275
276	pca6416: gpio@20 {
277		compatible = "ti,tca6416";
278		reg = <0x20>;
279		gpio-controller;
280		#gpio-cells = <2>;
281	};
282};
283
284&sai3 {
285	pinctrl-names = "default";
286	pinctrl-0 = <&pinctrl_sai3>;
287	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
288	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
289	assigned-clock-rates = <24576000>;
290	status = "okay";
291};
292
293&snvs_pwrkey {
294	status = "okay";
295};
296
297&uart2 { /* console */
298	pinctrl-names = "default";
299	pinctrl-0 = <&pinctrl_uart2>;
300	status = "okay";
301};
302
303&usbotg1 {
304	dr_mode = "otg";
305	hnp-disable;
306	srp-disable;
307	adp-disable;
308	usb-role-switch;
309	samsung,picophy-pre-emp-curr-control = <3>;
310	samsung,picophy-dc-vol-level-adjust = <7>;
311	status = "okay";
312
313	port {
314		usb1_drd_sw: endpoint {
315			remote-endpoint = <&typec1_dr_sw>;
316		};
317	};
318};
319
320&usdhc2 {
321	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
322	assigned-clock-rates = <200000000>;
323	pinctrl-names = "default", "state_100mhz", "state_200mhz";
324	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
325	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
326	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
327	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
328	bus-width = <4>;
329	vmmc-supply = <&reg_usdhc2_vmmc>;
330	status = "okay";
331};
332
333&wdog1 {
334	pinctrl-names = "default";
335	pinctrl-0 = <&pinctrl_wdog>;
336	fsl,ext-reset-output;
337	status = "okay";
338};
339
340&iomuxc {
341	pinctrl_fec1: fec1grp {
342		fsl,pins = <
343			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
344			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
345			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
346			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
347			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
348			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
349			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
350			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
351			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
352			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
353			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
354			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
355			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
356			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
357			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
358		>;
359	};
360
361	pinctrl_gpio_led: gpioledgrp {
362		fsl,pins = <
363			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
364		>;
365	};
366
367	pinctrl_gpio_wlf: gpiowlfgrp {
368		fsl,pins = <
369			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
370		>;
371	};
372
373	pinctrl_i2c1: i2c1grp {
374		fsl,pins = <
375			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
376			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
377		>;
378	};
379
380	pinctrl_i2c2: i2c2grp {
381		fsl,pins = <
382			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
383			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
384		>;
385	};
386
387	pinctrl_i2c3: i2c3grp {
388		fsl,pins = <
389			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
390			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
391		>;
392	};
393
394	pinctrl_pmic: pmicirqgrp {
395		fsl,pins = <
396			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
397		>;
398	};
399
400	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
401		fsl,pins = <
402			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
403		>;
404	};
405
406	pinctrl_sai3: sai3grp {
407		fsl,pins = <
408			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
409			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
410			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
411			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
412		>;
413	};
414
415	pinctrl_typec1: typec1grp {
416		fsl,pins = <
417			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
418		>;
419	};
420
421	pinctrl_uart2: uart2grp {
422		fsl,pins = <
423			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
424			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
425		>;
426	};
427
428	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
429		fsl,pins = <
430			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
431		>;
432	};
433
434	pinctrl_usdhc2: usdhc2grp {
435		fsl,pins = <
436			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
437			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
438			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
439			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
440			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
441			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
442			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
443		>;
444	};
445
446	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
447		fsl,pins = <
448			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
449			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
450			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
451			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
452			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
453			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
454			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
455		>;
456	};
457
458	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
459		fsl,pins = <
460			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
461			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
462			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
463			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
464			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
465			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
466			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
467		>;
468	};
469
470	pinctrl_wdog: wdoggrp {
471		fsl,pins = <
472			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
473		>;
474	};
475};
476