1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/irqchip.h>
9 #include <linux/of_platform.h>
10 #include <linux/pci.h>
11 #include <linux/phy.h>
12 #include <linux/regmap.h>
13 #include <linux/micrel_phy.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18
19 #include "common.h"
20 #include "cpuidle.h"
21 #include "hardware.h"
22
23 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
ksz9021rn_phy_fixup(struct phy_device * phydev)24 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
25 {
26 if (IS_BUILTIN(CONFIG_PHYLIB)) {
27 /* min rx data delay */
28 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
29 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
30 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
31
32 /* max rx/tx clock delay, min rx/tx control delay */
33 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
34 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
35 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
36 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
37 MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
38 }
39
40 return 0;
41 }
42
mmd_write_reg(struct phy_device * dev,int device,int reg,int val)43 static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
44 {
45 phy_write(dev, 0x0d, device);
46 phy_write(dev, 0x0e, reg);
47 phy_write(dev, 0x0d, (1 << 14) | device);
48 phy_write(dev, 0x0e, val);
49 }
50
ksz9031rn_phy_fixup(struct phy_device * dev)51 static int ksz9031rn_phy_fixup(struct phy_device *dev)
52 {
53 /*
54 * min rx data delay, max rx/tx clock delay,
55 * min rx/tx control delay
56 */
57 mmd_write_reg(dev, 2, 4, 0);
58 mmd_write_reg(dev, 2, 5, 0);
59 mmd_write_reg(dev, 2, 8, 0x003ff);
60
61 return 0;
62 }
63
64 /*
65 * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
66 * as they are used for slots1-7 PERST#
67 */
ventana_pciesw_early_fixup(struct pci_dev * dev)68 static void ventana_pciesw_early_fixup(struct pci_dev *dev)
69 {
70 u32 dw;
71
72 if (!of_machine_is_compatible("gw,ventana"))
73 return;
74
75 if (dev->devfn != 0)
76 return;
77
78 pci_read_config_dword(dev, 0x62c, &dw);
79 dw |= 0xaaa8; // GPIO1-7 outputs
80 pci_write_config_dword(dev, 0x62c, dw);
81
82 pci_read_config_dword(dev, 0x644, &dw);
83 dw |= 0xfe; // GPIO1-7 output high
84 pci_write_config_dword(dev, 0x644, dw);
85
86 msleep(100);
87 }
88 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
89 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
90 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
91
ar8031_phy_fixup(struct phy_device * dev)92 static int ar8031_phy_fixup(struct phy_device *dev)
93 {
94 u16 val;
95
96 /* To enable AR8031 output a 125MHz clk from CLK_25M */
97 phy_write(dev, 0xd, 0x7);
98 phy_write(dev, 0xe, 0x8016);
99 phy_write(dev, 0xd, 0x4007);
100
101 val = phy_read(dev, 0xe);
102 val &= 0xffe3;
103 val |= 0x18;
104 phy_write(dev, 0xe, val);
105
106 /* introduce tx clock delay */
107 phy_write(dev, 0x1d, 0x5);
108 val = phy_read(dev, 0x1e);
109 val |= 0x0100;
110 phy_write(dev, 0x1e, val);
111
112 return 0;
113 }
114
115 #define PHY_ID_AR8031 0x004dd074
116
ar8035_phy_fixup(struct phy_device * dev)117 static int ar8035_phy_fixup(struct phy_device *dev)
118 {
119 u16 val;
120
121 /* Ar803x phy SmartEEE feature cause link status generates glitch,
122 * which cause ethernet link down/up issue, so disable SmartEEE
123 */
124 phy_write(dev, 0xd, 0x3);
125 phy_write(dev, 0xe, 0x805d);
126 phy_write(dev, 0xd, 0x4003);
127
128 val = phy_read(dev, 0xe);
129 phy_write(dev, 0xe, val & ~(1 << 8));
130
131 /*
132 * Enable 125MHz clock from CLK_25M on the AR8031. This
133 * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
134 * Also, introduce a tx clock delay.
135 *
136 * This is the same as is the AR8031 fixup.
137 */
138 ar8031_phy_fixup(dev);
139
140 /*check phy power*/
141 val = phy_read(dev, 0x0);
142 if (val & BMCR_PDOWN)
143 phy_write(dev, 0x0, val & ~BMCR_PDOWN);
144
145 return 0;
146 }
147
148 #define PHY_ID_AR8035 0x004dd072
149
imx6q_enet_phy_init(void)150 static void __init imx6q_enet_phy_init(void)
151 {
152 if (IS_BUILTIN(CONFIG_PHYLIB)) {
153 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
154 ksz9021rn_phy_fixup);
155 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
156 ksz9031rn_phy_fixup);
157 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,
158 ar8031_phy_fixup);
159 phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
160 ar8035_phy_fixup);
161 }
162 }
163
imx6q_1588_init(void)164 static void __init imx6q_1588_init(void)
165 {
166 struct device_node *np;
167 struct clk *ptp_clk;
168 struct clk *enet_ref;
169 struct regmap *gpr;
170 u32 clksel;
171
172 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
173 if (!np) {
174 pr_warn("%s: failed to find fec node\n", __func__);
175 return;
176 }
177
178 ptp_clk = of_clk_get(np, 2);
179 if (IS_ERR(ptp_clk)) {
180 pr_warn("%s: failed to get ptp clock\n", __func__);
181 goto put_node;
182 }
183
184 enet_ref = clk_get_sys(NULL, "enet_ref");
185 if (IS_ERR(enet_ref)) {
186 pr_warn("%s: failed to get enet clock\n", __func__);
187 goto put_ptp_clk;
188 }
189
190 /*
191 * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
192 * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad
193 * (external OSC), and we need to clear the bit.
194 */
195 clksel = clk_is_match(ptp_clk, enet_ref) ?
196 IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
197 IMX6Q_GPR1_ENET_CLK_SEL_PAD;
198 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
199 if (!IS_ERR(gpr))
200 regmap_update_bits(gpr, IOMUXC_GPR1,
201 IMX6Q_GPR1_ENET_CLK_SEL_MASK,
202 clksel);
203 else
204 pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
205
206 clk_put(enet_ref);
207 put_ptp_clk:
208 clk_put(ptp_clk);
209 put_node:
210 of_node_put(np);
211 }
212
imx6q_axi_init(void)213 static void __init imx6q_axi_init(void)
214 {
215 struct regmap *gpr;
216 unsigned int mask;
217
218 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
219 if (!IS_ERR(gpr)) {
220 /*
221 * Enable the cacheable attribute of VPU and IPU
222 * AXI transactions.
223 */
224 mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL |
225 IMX6Q_GPR4_VPU_RD_CACHE_SEL |
226 IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
227 IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
228 IMX6Q_GPR4_IPU_WR_CACHE_CTL |
229 IMX6Q_GPR4_IPU_RD_CACHE_CTL;
230 regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask);
231
232 /* Increase IPU read QoS priority */
233 regmap_update_bits(gpr, IOMUXC_GPR6,
234 IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
235 IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
236 (0xf << 16) | (0x7 << 20));
237 regmap_update_bits(gpr, IOMUXC_GPR7,
238 IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
239 IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
240 (0xf << 16) | (0x7 << 20));
241 } else {
242 pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
243 }
244 }
245
imx6q_init_machine(void)246 static void __init imx6q_init_machine(void)
247 {
248 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
249 imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
250 else
251 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
252 imx_get_soc_revision());
253
254 imx6q_enet_phy_init();
255
256 of_platform_default_populate(NULL, NULL, NULL);
257
258 imx_anatop_init();
259 cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
260 imx6q_1588_init();
261 imx6q_axi_init();
262 }
263
imx6q_init_late(void)264 static void __init imx6q_init_late(void)
265 {
266 /*
267 * WAIT mode is broken on imx6 Dual/Quad revision 1.0 and 1.1 so
268 * there is no point to run cpuidle on them.
269 *
270 * It does work on imx6 Solo/DualLite starting from 1.1
271 */
272 if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) ||
273 (cpu_is_imx6dl() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0))
274 imx6q_cpuidle_init();
275
276 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
277 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
278 }
279
imx6q_map_io(void)280 static void __init imx6q_map_io(void)
281 {
282 debug_ll_io_init();
283 imx_scu_map_io();
284 }
285
imx6q_init_irq(void)286 static void __init imx6q_init_irq(void)
287 {
288 imx_gpc_check_dt();
289 imx_init_revision_from_anatop();
290 imx_init_l2cache();
291 imx_src_init();
292 irqchip_init();
293 imx6_pm_ccm_init("fsl,imx6q-ccm");
294 }
295
296 static const char * const imx6q_dt_compat[] __initconst = {
297 "fsl,imx6dl",
298 "fsl,imx6q",
299 "fsl,imx6qp",
300 NULL,
301 };
302
303 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
304 .l2c_aux_val = 0,
305 .l2c_aux_mask = ~0,
306 .smp = smp_ops(imx_smp_ops),
307 .map_io = imx6q_map_io,
308 .init_irq = imx6q_init_irq,
309 .init_machine = imx6q_init_machine,
310 .init_late = imx6q_init_late,
311 .dt_compat = imx6q_dt_compat,
312 MACHINE_END
313
