1 /*
2 * TI DaVinci DM365 EVM board support
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/i2c.h>
19 #include <linux/io.h>
20 #include <linux/clk.h>
21 #include <linux/property.h>
22 #include <linux/leds.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/slab.h>
26 #include <linux/mtd/rawnand.h>
27 #include <linux/nvmem-provider.h>
28 #include <linux/input.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/eeprom.h>
31 #include <linux/v4l2-dv-timings.h>
32 #include <linux/platform_data/ti-aemif.h>
33 #include <linux/regulator/fixed.h>
34 #include <linux/regulator/machine.h>
35
36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h>
38
39 #include <mach/mux.h>
40 #include <mach/common.h>
41 #include <linux/platform_data/i2c-davinci.h>
42 #include <mach/serial.h>
43 #include <linux/platform_data/mmc-davinci.h>
44 #include <linux/platform_data/mtd-davinci.h>
45 #include <linux/platform_data/keyscan-davinci.h>
46
47 #include <media/i2c/ths7303.h>
48 #include <media/i2c/tvp514x.h>
49
50 #include "davinci.h"
51
have_imager(void)52 static inline int have_imager(void)
53 {
54 /* REVISIT when it's supported, trigger via Kconfig */
55 return 0;
56 }
57
have_tvp7002(void)58 static inline int have_tvp7002(void)
59 {
60 /* REVISIT when it's supported, trigger via Kconfig */
61 return 0;
62 }
63
64 #define DM365_EVM_PHY_ID "davinci_mdio-0:01"
65 /*
66 * A MAX-II CPLD is used for various board control functions.
67 */
68 #define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3))
69
70 #define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */
71 #define CPLD_TEST CPLD_OFFSET(0,1)
72 #define CPLD_LEDS CPLD_OFFSET(0,2)
73 #define CPLD_MUX CPLD_OFFSET(0,3)
74 #define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */
75 #define CPLD_POWER CPLD_OFFSET(1,1)
76 #define CPLD_VIDEO CPLD_OFFSET(1,2)
77 #define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */
78
79 #define CPLD_DILC_OUT CPLD_OFFSET(2,0)
80 #define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */
81
82 #define CPLD_IMG_DIR0 CPLD_OFFSET(2,2)
83 #define CPLD_IMG_MUX0 CPLD_OFFSET(2,3)
84 #define CPLD_IMG_MUX1 CPLD_OFFSET(3,0)
85 #define CPLD_IMG_DIR1 CPLD_OFFSET(3,1)
86 #define CPLD_IMG_MUX2 CPLD_OFFSET(3,2)
87 #define CPLD_IMG_MUX3 CPLD_OFFSET(3,3)
88 #define CPLD_IMG_DIR2 CPLD_OFFSET(4,0)
89 #define CPLD_IMG_MUX4 CPLD_OFFSET(4,1)
90 #define CPLD_IMG_MUX5 CPLD_OFFSET(4,2)
91
92 #define CPLD_RESETS CPLD_OFFSET(4,3)
93
94 #define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0)
95 #define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1)
96 #define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2)
97 #define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3)
98 #define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0)
99 #define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1)
100
101 static void __iomem *cpld;
102
103
104 /* NOTE: this is geared for the standard config, with a socketed
105 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
106 * swap chips with a different block size, partitioning will
107 * need to be changed. This NAND chip MT29F16G08FAA is the default
108 * NAND shipped with the Spectrum Digital DM365 EVM
109 */
110 #define NAND_BLOCK_SIZE SZ_128K
111
112 static struct mtd_partition davinci_nand_partitions[] = {
113 {
114 /* UBL (a few copies) plus U-Boot */
115 .name = "bootloader",
116 .offset = 0,
117 .size = 30 * NAND_BLOCK_SIZE,
118 .mask_flags = MTD_WRITEABLE, /* force read-only */
119 }, {
120 /* U-Boot environment */
121 .name = "params",
122 .offset = MTDPART_OFS_APPEND,
123 .size = 2 * NAND_BLOCK_SIZE,
124 .mask_flags = 0,
125 }, {
126 .name = "kernel",
127 .offset = MTDPART_OFS_APPEND,
128 .size = SZ_4M,
129 .mask_flags = 0,
130 }, {
131 .name = "filesystem1",
132 .offset = MTDPART_OFS_APPEND,
133 .size = SZ_512M,
134 .mask_flags = 0,
135 }, {
136 .name = "filesystem2",
137 .offset = MTDPART_OFS_APPEND,
138 .size = MTDPART_SIZ_FULL,
139 .mask_flags = 0,
140 }
141 /* two blocks with bad block table (and mirror) at the end */
142 };
143
144 static struct davinci_nand_pdata davinci_nand_data = {
145 .core_chipsel = 0,
146 .mask_chipsel = BIT(14),
147 .parts = davinci_nand_partitions,
148 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
149 .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
150 .bbt_options = NAND_BBT_USE_FLASH,
151 .ecc_bits = 4,
152 };
153
154 static struct resource davinci_nand_resources[] = {
155 {
156 .start = DM365_ASYNC_EMIF_DATA_CE0_BASE,
157 .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
158 .flags = IORESOURCE_MEM,
159 }, {
160 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
161 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 };
165
166 static struct platform_device davinci_aemif_devices[] = {
167 {
168 .name = "davinci_nand",
169 .id = 0,
170 .num_resources = ARRAY_SIZE(davinci_nand_resources),
171 .resource = davinci_nand_resources,
172 .dev = {
173 .platform_data = &davinci_nand_data,
174 },
175 }
176 };
177
178 static struct resource davinci_aemif_resources[] = {
179 {
180 .start = DM365_ASYNC_EMIF_CONTROL_BASE,
181 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
182 .flags = IORESOURCE_MEM,
183 },
184 };
185
186 static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
187 {
188 .cs = 1,
189 },
190 };
191
192 static struct aemif_platform_data davinci_aemif_pdata = {
193 .abus_data = da850_evm_aemif_abus_data,
194 .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data),
195 .sub_devices = davinci_aemif_devices,
196 .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices),
197 };
198
199 static struct platform_device davinci_aemif_device = {
200 .name = "ti-aemif",
201 .id = -1,
202 .dev = {
203 .platform_data = &davinci_aemif_pdata,
204 },
205 .resource = davinci_aemif_resources,
206 .num_resources = ARRAY_SIZE(davinci_aemif_resources),
207 };
208
209 static struct nvmem_cell_info davinci_nvmem_cells[] = {
210 {
211 .name = "macaddr",
212 .offset = 0x7f00,
213 .bytes = ETH_ALEN,
214 }
215 };
216
217 static struct nvmem_cell_table davinci_nvmem_cell_table = {
218 .nvmem_name = "1-00500",
219 .cells = davinci_nvmem_cells,
220 .ncells = ARRAY_SIZE(davinci_nvmem_cells),
221 };
222
223 static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
224 .nvmem_name = "1-00500",
225 .cell_name = "macaddr",
226 .dev_id = "davinci_emac.1",
227 .con_id = "mac-address",
228 };
229
230 static const struct property_entry eeprom_properties[] = {
231 PROPERTY_ENTRY_U32("pagesize", 64),
232 { }
233 };
234
235 static struct i2c_board_info i2c_info[] = {
236 {
237 I2C_BOARD_INFO("24c256", 0x50),
238 .properties = eeprom_properties,
239 },
240 {
241 I2C_BOARD_INFO("tlv320aic3x", 0x18),
242 },
243 };
244
245 static struct davinci_i2c_platform_data i2c_pdata = {
246 .bus_freq = 400 /* kHz */,
247 .bus_delay = 0 /* usec */,
248 };
249
250 /* Fixed regulator support */
251 static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
252 /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
253 REGULATOR_SUPPLY("AVDD", "1-0018"),
254 REGULATOR_SUPPLY("DRVDD", "1-0018"),
255 REGULATOR_SUPPLY("IOVDD", "1-0018"),
256 };
257
258 static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
259 /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
260 REGULATOR_SUPPLY("DVDD", "1-0018"),
261 };
262
dm365evm_keyscan_enable(struct device * dev)263 static int dm365evm_keyscan_enable(struct device *dev)
264 {
265 return davinci_cfg_reg(DM365_KEYSCAN);
266 }
267
268 static unsigned short dm365evm_keymap[] = {
269 KEY_KP2,
270 KEY_LEFT,
271 KEY_EXIT,
272 KEY_DOWN,
273 KEY_ENTER,
274 KEY_UP,
275 KEY_KP1,
276 KEY_RIGHT,
277 KEY_MENU,
278 KEY_RECORD,
279 KEY_REWIND,
280 KEY_KPMINUS,
281 KEY_STOP,
282 KEY_FASTFORWARD,
283 KEY_KPPLUS,
284 KEY_PLAYPAUSE,
285 0
286 };
287
288 static struct davinci_ks_platform_data dm365evm_ks_data = {
289 .device_enable = dm365evm_keyscan_enable,
290 .keymap = dm365evm_keymap,
291 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
292 .rep = 1,
293 /* Scan period = strobe + interval */
294 .strobe = 0x5,
295 .interval = 0x2,
296 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
297 };
298
cpld_mmc_get_cd(int module)299 static int cpld_mmc_get_cd(int module)
300 {
301 if (!cpld)
302 return -ENXIO;
303
304 /* low == card present */
305 return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
306 }
307
cpld_mmc_get_ro(int module)308 static int cpld_mmc_get_ro(int module)
309 {
310 if (!cpld)
311 return -ENXIO;
312
313 /* high == card's write protect switch active */
314 return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
315 }
316
317 static struct davinci_mmc_config dm365evm_mmc_config = {
318 .get_cd = cpld_mmc_get_cd,
319 .get_ro = cpld_mmc_get_ro,
320 .wires = 4,
321 .max_freq = 50000000,
322 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
323 };
324
dm365evm_emac_configure(void)325 static void dm365evm_emac_configure(void)
326 {
327 /*
328 * EMAC pins are multiplexed with GPIO and UART
329 * Further details are available at the DM365 ARM
330 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
331 */
332 davinci_cfg_reg(DM365_EMAC_TX_EN);
333 davinci_cfg_reg(DM365_EMAC_TX_CLK);
334 davinci_cfg_reg(DM365_EMAC_COL);
335 davinci_cfg_reg(DM365_EMAC_TXD3);
336 davinci_cfg_reg(DM365_EMAC_TXD2);
337 davinci_cfg_reg(DM365_EMAC_TXD1);
338 davinci_cfg_reg(DM365_EMAC_TXD0);
339 davinci_cfg_reg(DM365_EMAC_RXD3);
340 davinci_cfg_reg(DM365_EMAC_RXD2);
341 davinci_cfg_reg(DM365_EMAC_RXD1);
342 davinci_cfg_reg(DM365_EMAC_RXD0);
343 davinci_cfg_reg(DM365_EMAC_RX_CLK);
344 davinci_cfg_reg(DM365_EMAC_RX_DV);
345 davinci_cfg_reg(DM365_EMAC_RX_ER);
346 davinci_cfg_reg(DM365_EMAC_CRS);
347 davinci_cfg_reg(DM365_EMAC_MDIO);
348 davinci_cfg_reg(DM365_EMAC_MDCLK);
349
350 /*
351 * EMAC interrupts are multiplexed with GPIO interrupts
352 * Details are available at the DM365 ARM
353 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
354 */
355 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
356 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
357 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
358 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
359 }
360
dm365evm_mmc_configure(void)361 static void dm365evm_mmc_configure(void)
362 {
363 /*
364 * MMC/SD pins are multiplexed with GPIO and EMIF
365 * Further details are available at the DM365 ARM
366 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
367 */
368 davinci_cfg_reg(DM365_SD1_CLK);
369 davinci_cfg_reg(DM365_SD1_CMD);
370 davinci_cfg_reg(DM365_SD1_DATA3);
371 davinci_cfg_reg(DM365_SD1_DATA2);
372 davinci_cfg_reg(DM365_SD1_DATA1);
373 davinci_cfg_reg(DM365_SD1_DATA0);
374 }
375
376 static struct tvp514x_platform_data tvp5146_pdata = {
377 .clk_polarity = 0,
378 .hs_polarity = 1,
379 .vs_polarity = 1
380 };
381
382 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
383 /* Inputs available at the TVP5146 */
384 static struct v4l2_input tvp5146_inputs[] = {
385 {
386 .index = 0,
387 .name = "Composite",
388 .type = V4L2_INPUT_TYPE_CAMERA,
389 .std = TVP514X_STD_ALL,
390 },
391 {
392 .index = 1,
393 .name = "S-Video",
394 .type = V4L2_INPUT_TYPE_CAMERA,
395 .std = TVP514X_STD_ALL,
396 },
397 };
398
399 /*
400 * this is the route info for connecting each input to decoder
401 * ouput that goes to vpfe. There is a one to one correspondence
402 * with tvp5146_inputs
403 */
404 static struct vpfe_route tvp5146_routes[] = {
405 {
406 .input = INPUT_CVBS_VI2B,
407 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
408 },
409 {
410 .input = INPUT_SVIDEO_VI2C_VI1C,
411 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
412 },
413 };
414
415 static struct vpfe_subdev_info vpfe_sub_devs[] = {
416 {
417 .name = "tvp5146",
418 .grp_id = 0,
419 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
420 .inputs = tvp5146_inputs,
421 .routes = tvp5146_routes,
422 .can_route = 1,
423 .ccdc_if_params = {
424 .if_type = VPFE_BT656,
425 .hdpol = VPFE_PINPOL_POSITIVE,
426 .vdpol = VPFE_PINPOL_POSITIVE,
427 },
428 .board_info = {
429 I2C_BOARD_INFO("tvp5146", 0x5d),
430 .platform_data = &tvp5146_pdata,
431 },
432 },
433 };
434
435 static struct vpfe_config vpfe_cfg = {
436 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
437 .sub_devs = vpfe_sub_devs,
438 .i2c_adapter_id = 1,
439 .card_name = "DM365 EVM",
440 .ccdc = "ISIF",
441 };
442
443 /* venc standards timings */
444 static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
445 {
446 .name = "ntsc",
447 .timings_type = VPBE_ENC_STD,
448 .std_id = V4L2_STD_NTSC,
449 .interlaced = 1,
450 .xres = 720,
451 .yres = 480,
452 .aspect = {11, 10},
453 .fps = {30000, 1001},
454 .left_margin = 0x79,
455 .upper_margin = 0x10,
456 },
457 {
458 .name = "pal",
459 .timings_type = VPBE_ENC_STD,
460 .std_id = V4L2_STD_PAL,
461 .interlaced = 1,
462 .xres = 720,
463 .yres = 576,
464 .aspect = {54, 59},
465 .fps = {25, 1},
466 .left_margin = 0x7E,
467 .upper_margin = 0x16,
468 },
469 };
470
471 /* venc dv timings */
472 static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
473 {
474 .name = "480p59_94",
475 .timings_type = VPBE_ENC_DV_TIMINGS,
476 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
477 .interlaced = 0,
478 .xres = 720,
479 .yres = 480,
480 .aspect = {1, 1},
481 .fps = {5994, 100},
482 .left_margin = 0x8F,
483 .upper_margin = 0x2D,
484 },
485 {
486 .name = "576p50",
487 .timings_type = VPBE_ENC_DV_TIMINGS,
488 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
489 .interlaced = 0,
490 .xres = 720,
491 .yres = 576,
492 .aspect = {1, 1},
493 .fps = {50, 1},
494 .left_margin = 0x8C,
495 .upper_margin = 0x36,
496 },
497 {
498 .name = "720p60",
499 .timings_type = VPBE_ENC_DV_TIMINGS,
500 .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
501 .interlaced = 0,
502 .xres = 1280,
503 .yres = 720,
504 .aspect = {1, 1},
505 .fps = {60, 1},
506 .left_margin = 0x117,
507 .right_margin = 70,
508 .upper_margin = 38,
509 .lower_margin = 3,
510 .hsync_len = 80,
511 .vsync_len = 5,
512 },
513 {
514 .name = "1080i60",
515 .timings_type = VPBE_ENC_DV_TIMINGS,
516 .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
517 .interlaced = 1,
518 .xres = 1920,
519 .yres = 1080,
520 .aspect = {1, 1},
521 .fps = {30, 1},
522 .left_margin = 0xc9,
523 .right_margin = 80,
524 .upper_margin = 30,
525 .lower_margin = 3,
526 .hsync_len = 88,
527 .vsync_len = 5,
528 },
529 };
530
531 #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
532
533 /*
534 * The outputs available from VPBE + ecnoders. Keep the
535 * the order same as that of encoders. First those from venc followed by that
536 * from encoders. Index in the output refers to index on a particular
537 * encoder.Driver uses this index to pass it to encoder when it supports more
538 * than one output. Application uses index of the array to set an output.
539 */
540 static struct vpbe_output dm365evm_vpbe_outputs[] = {
541 {
542 .output = {
543 .index = 0,
544 .name = "Composite",
545 .type = V4L2_OUTPUT_TYPE_ANALOG,
546 .std = VENC_STD_ALL,
547 .capabilities = V4L2_OUT_CAP_STD,
548 },
549 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
550 .default_mode = "ntsc",
551 .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing),
552 .modes = dm365evm_enc_std_timing,
553 .if_params = MEDIA_BUS_FMT_FIXED,
554 },
555 {
556 .output = {
557 .index = 1,
558 .name = "Component",
559 .type = V4L2_OUTPUT_TYPE_ANALOG,
560 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
561 },
562 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME,
563 .default_mode = "480p59_94",
564 .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing),
565 .modes = dm365evm_enc_preset_timing,
566 .if_params = MEDIA_BUS_FMT_FIXED,
567 },
568 };
569
570 /*
571 * Amplifiers on the board
572 */
573 static struct ths7303_platform_data ths7303_pdata = {
574 .ch_1 = 3,
575 .ch_2 = 3,
576 .ch_3 = 3,
577 };
578
579 static struct amp_config_info vpbe_amp = {
580 .module_name = "ths7303",
581 .is_i2c = 1,
582 .board_info = {
583 I2C_BOARD_INFO("ths7303", 0x2c),
584 .platform_data = &ths7303_pdata,
585 }
586 };
587
588 static struct vpbe_config dm365evm_display_cfg = {
589 .module_name = "dm365-vpbe-display",
590 .i2c_adapter_id = 1,
591 .amp = &vpbe_amp,
592 .osd = {
593 .module_name = DM365_VPBE_OSD_SUBDEV_NAME,
594 },
595 .venc = {
596 .module_name = DM365_VPBE_VENC_SUBDEV_NAME,
597 },
598 .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs),
599 .outputs = dm365evm_vpbe_outputs,
600 };
601
evm_init_i2c(void)602 static void __init evm_init_i2c(void)
603 {
604 davinci_init_i2c(&i2c_pdata);
605 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
606 }
607
have_leds(void)608 static inline int have_leds(void)
609 {
610 #ifdef CONFIG_LEDS_CLASS
611 return 1;
612 #else
613 return 0;
614 #endif
615 }
616
617 struct cpld_led {
618 struct led_classdev cdev;
619 u8 mask;
620 };
621
622 static const struct {
623 const char *name;
624 const char *trigger;
625 } cpld_leds[] = {
626 { "dm365evm::ds2", },
627 { "dm365evm::ds3", },
628 { "dm365evm::ds4", },
629 { "dm365evm::ds5", },
630 { "dm365evm::ds6", "nand-disk", },
631 { "dm365evm::ds7", "mmc1", },
632 { "dm365evm::ds8", "mmc0", },
633 { "dm365evm::ds9", "heartbeat", },
634 };
635
cpld_led_set(struct led_classdev * cdev,enum led_brightness b)636 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
637 {
638 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
639 u8 reg = __raw_readb(cpld + CPLD_LEDS);
640
641 if (b != LED_OFF)
642 reg &= ~led->mask;
643 else
644 reg |= led->mask;
645 __raw_writeb(reg, cpld + CPLD_LEDS);
646 }
647
cpld_led_get(struct led_classdev * cdev)648 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
649 {
650 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
651 u8 reg = __raw_readb(cpld + CPLD_LEDS);
652
653 return (reg & led->mask) ? LED_OFF : LED_FULL;
654 }
655
cpld_leds_init(void)656 static int __init cpld_leds_init(void)
657 {
658 int i;
659
660 if (!have_leds() || !cpld)
661 return 0;
662
663 /* setup LEDs */
664 __raw_writeb(0xff, cpld + CPLD_LEDS);
665 for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
666 struct cpld_led *led;
667
668 led = kzalloc(sizeof(*led), GFP_KERNEL);
669 if (!led)
670 break;
671
672 led->cdev.name = cpld_leds[i].name;
673 led->cdev.brightness_set = cpld_led_set;
674 led->cdev.brightness_get = cpld_led_get;
675 led->cdev.default_trigger = cpld_leds[i].trigger;
676 led->mask = BIT(i);
677
678 if (led_classdev_register(NULL, &led->cdev) < 0) {
679 kfree(led);
680 break;
681 }
682 }
683
684 return 0;
685 }
686 /* run after subsys_initcall() for LEDs */
687 fs_initcall(cpld_leds_init);
688
689
evm_init_cpld(void)690 static void __init evm_init_cpld(void)
691 {
692 u8 mux, resets;
693 const char *label;
694 struct clk *aemif_clk;
695 int rc;
696
697 /* Make sure we can configure the CPLD through CS1. Then
698 * leave it on for later access to MMC and LED registers.
699 */
700 aemif_clk = clk_get(NULL, "aemif");
701 if (IS_ERR(aemif_clk))
702 return;
703 clk_prepare_enable(aemif_clk);
704
705 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
706 "cpld") == NULL)
707 goto fail;
708 cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
709 if (!cpld) {
710 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
711 SECTION_SIZE);
712 fail:
713 pr_err("ERROR: can't map CPLD\n");
714 clk_disable_unprepare(aemif_clk);
715 return;
716 }
717
718 /* External muxing for some signals */
719 mux = 0;
720
721 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
722 * NOTE: SW4 bus width setting must match!
723 */
724 if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
725 /* external keypad mux */
726 mux |= BIT(7);
727
728 rc = platform_device_register(&davinci_aemif_device);
729 if (rc)
730 pr_warn("%s(): error registering the aemif device: %d\n",
731 __func__, rc);
732 } else {
733 /* no OneNAND support yet */
734 }
735
736 /* Leave external chips in reset when unused. */
737 resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
738
739 /* Static video input config with SN74CBT16214 1-of-3 mux:
740 * - port b1 == tvp7002 (mux lowbits == 1 or 6)
741 * - port b2 == imager (mux lowbits == 2 or 7)
742 * - port b3 == tvp5146 (mux lowbits == 5)
743 *
744 * Runtime switching could work too, with limitations.
745 */
746 if (have_imager()) {
747 label = "HD imager";
748 mux |= 2;
749
750 /* externally mux MMC1/ENET/AIC33 to imager */
751 mux |= BIT(6) | BIT(5) | BIT(3);
752 } else {
753 struct davinci_soc_info *soc_info = &davinci_soc_info;
754
755 /* we can use MMC1 ... */
756 dm365evm_mmc_configure();
757 davinci_setup_mmc(1, &dm365evm_mmc_config);
758
759 /* ... and ENET ... */
760 dm365evm_emac_configure();
761 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
762 resets &= ~BIT(3);
763
764 /* ... and AIC33 */
765 resets &= ~BIT(1);
766
767 if (have_tvp7002()) {
768 mux |= 1;
769 resets &= ~BIT(2);
770 label = "tvp7002 HD";
771 } else {
772 /* default to tvp5146 */
773 mux |= 5;
774 resets &= ~BIT(0);
775 label = "tvp5146 SD";
776 }
777 }
778 __raw_writeb(mux, cpld + CPLD_MUX);
779 __raw_writeb(resets, cpld + CPLD_RESETS);
780 pr_info("EVM: %s video input\n", label);
781
782 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
783 }
784
dm365_evm_map_io(void)785 static void __init dm365_evm_map_io(void)
786 {
787 dm365_init();
788 }
789
790 static struct spi_eeprom at25640 = {
791 .byte_len = SZ_64K / 8,
792 .name = "at25640",
793 .page_size = 32,
794 .flags = EE_ADDR2,
795 };
796
797 static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
798 {
799 .modalias = "at25",
800 .platform_data = &at25640,
801 .max_speed_hz = 10 * 1000 * 1000,
802 .bus_num = 0,
803 .chip_select = 0,
804 .mode = SPI_MODE_0,
805 },
806 };
807
dm365_evm_init(void)808 static __init void dm365_evm_init(void)
809 {
810 int ret;
811
812 dm365_register_clocks();
813
814 ret = dm365_gpio_register();
815 if (ret)
816 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
817
818 regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
819 ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
820 regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
821 ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
822
823 nvmem_add_cell_table(&davinci_nvmem_cell_table);
824 nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
825
826 evm_init_i2c();
827 davinci_serial_init(dm365_serial_device);
828
829 dm365evm_emac_configure();
830 dm365evm_mmc_configure();
831
832 davinci_setup_mmc(0, &dm365evm_mmc_config);
833
834 dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
835
836 /* maybe setup mmc1/etc ... _after_ mmc0 */
837 evm_init_cpld();
838
839 #ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
840 dm365_init_asp();
841 #elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
842 dm365_init_vc();
843 #endif
844 dm365_init_rtc();
845 dm365_init_ks(&dm365evm_ks_data);
846
847 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
848 ARRAY_SIZE(dm365_evm_spi_info));
849 }
850
851 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
852 .atag_offset = 0x100,
853 .map_io = dm365_evm_map_io,
854 .init_irq = dm365_init_irq,
855 .init_time = dm365_init_time,
856 .init_machine = dm365_evm_init,
857 .init_late = davinci_init_late,
858 .dma_zone_size = SZ_128M,
859 MACHINE_END
860
861
