1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6#include <dt-bindings/mfd/qcom-rpm.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	model = "Qualcomm MSM8960";
13	compatible = "qcom,msm8960";
14	interrupt-parent = <&intc>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19		interrupts = <1 14 0x304>;
20
21		cpu@0 {
22			compatible = "qcom,krait";
23			enable-method = "qcom,kpss-acc-v1";
24			device_type = "cpu";
25			reg = <0>;
26			next-level-cache = <&L2>;
27			qcom,acc = <&acc0>;
28			qcom,saw = <&saw0>;
29		};
30
31		cpu@1 {
32			compatible = "qcom,krait";
33			enable-method = "qcom,kpss-acc-v1";
34			device_type = "cpu";
35			reg = <1>;
36			next-level-cache = <&L2>;
37			qcom,acc = <&acc1>;
38			qcom,saw = <&saw1>;
39		};
40
41		L2: l2-cache {
42			compatible = "cache";
43			cache-level = <2>;
44		};
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x0 0x0>;
50	};
51
52	cpu-pmu {
53		compatible = "qcom,krait-pmu";
54		interrupts = <1 10 0x304>;
55		qcom,no-pc-write;
56	};
57
58	clocks {
59		cxo_board {
60			compatible = "fixed-clock";
61			#clock-cells = <0>;
62			clock-frequency = <19200000>;
63			clock-output-names = "cxo_board";
64		};
65
66		pxo_board {
67			compatible = "fixed-clock";
68			#clock-cells = <0>;
69			clock-frequency = <27000000>;
70			clock-output-names = "pxo_board";
71		};
72
73		sleep_clk {
74			compatible = "fixed-clock";
75			#clock-cells = <0>;
76			clock-frequency = <32768>;
77			clock-output-names = "sleep_clk";
78		};
79	};
80
81	soc: soc {
82		#address-cells = <1>;
83		#size-cells = <1>;
84		ranges;
85		compatible = "simple-bus";
86
87		intc: interrupt-controller@2000000 {
88			compatible = "qcom,msm-qgic2";
89			interrupt-controller;
90			#interrupt-cells = <3>;
91			reg = <0x02000000 0x1000>,
92			      <0x02002000 0x1000>;
93		};
94
95		timer@200a000 {
96			compatible = "qcom,kpss-timer",
97				     "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
98			interrupts = <1 1 0x301>,
99				     <1 2 0x301>,
100				     <1 3 0x301>;
101			reg = <0x0200a000 0x100>;
102			clock-frequency = <27000000>,
103					  <32768>;
104			cpu-offset = <0x80000>;
105		};
106
107		msmgpio: pinctrl@800000 {
108			compatible = "qcom,msm8960-pinctrl";
109			gpio-controller;
110			gpio-ranges = <&msmgpio 0 0 152>;
111			#gpio-cells = <2>;
112			interrupts = <0 16 0x4>;
113			interrupt-controller;
114			#interrupt-cells = <2>;
115			reg = <0x800000 0x4000>;
116		};
117
118		gcc: clock-controller@900000 {
119			compatible = "qcom,gcc-msm8960";
120			#clock-cells = <1>;
121			#reset-cells = <1>;
122			reg = <0x900000 0x4000>;
123		};
124
125		lcc: clock-controller@28000000 {
126			compatible = "qcom,lcc-msm8960";
127			reg = <0x28000000 0x1000>;
128			#clock-cells = <1>;
129			#reset-cells = <1>;
130		};
131
132		clock-controller@4000000 {
133			compatible = "qcom,mmcc-msm8960";
134			reg = <0x4000000 0x1000>;
135			#clock-cells = <1>;
136			#reset-cells = <1>;
137		};
138
139		l2cc: clock-controller@2011000 {
140			compatible	= "syscon";
141			reg		= <0x2011000 0x1000>;
142		};
143
144		rpm@108000 {
145			compatible	= "qcom,rpm-msm8960";
146			reg		= <0x108000 0x1000>;
147			qcom,ipc	= <&l2cc 0x8 2>;
148
149			interrupts	= <0 19 0>, <0 21 0>, <0 22 0>;
150			interrupt-names	= "ack", "err", "wakeup";
151
152			regulators {
153				compatible = "qcom,rpm-pm8921-regulators";
154			};
155		};
156
157		acc0: clock-controller@2088000 {
158			compatible = "qcom,kpss-acc-v1";
159			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
160		};
161
162		acc1: clock-controller@2098000 {
163			compatible = "qcom,kpss-acc-v1";
164			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
165		};
166
167		saw0: regulator@2089000 {
168			compatible = "qcom,saw2";
169			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
170			regulator;
171		};
172
173		saw1: regulator@2099000 {
174			compatible = "qcom,saw2";
175			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
176			regulator;
177		};
178
179		gsbi5: gsbi@16400000 {
180			compatible = "qcom,gsbi-v1.0.0";
181			cell-index = <5>;
182			reg = <0x16400000 0x100>;
183			clocks = <&gcc GSBI5_H_CLK>;
184			clock-names = "iface";
185			#address-cells = <1>;
186			#size-cells = <1>;
187			ranges;
188
189			syscon-tcsr = <&tcsr>;
190
191			gsbi5_serial: serial@16440000 {
192				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
193				reg = <0x16440000 0x1000>,
194				      <0x16400000 0x1000>;
195				interrupts = <0 154 0x0>;
196				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
197				clock-names = "core", "iface";
198				status = "disabled";
199			};
200		};
201
202		qcom,ssbi@500000 {
203			compatible = "qcom,ssbi";
204			reg = <0x500000 0x1000>;
205			qcom,controller-type = "pmic-arbiter";
206
207			pmicintc: pmic@0 {
208				compatible = "qcom,pm8921";
209				interrupt-parent = <&msmgpio>;
210				interrupts = <104 8>;
211				#interrupt-cells = <2>;
212				interrupt-controller;
213				#address-cells = <1>;
214				#size-cells = <0>;
215
216				pwrkey@1c {
217					compatible = "qcom,pm8921-pwrkey";
218					reg = <0x1c>;
219					interrupt-parent = <&pmicintc>;
220					interrupts = <50 1>, <51 1>;
221					debounce = <15625>;
222					pull-up;
223				};
224
225				keypad@148 {
226					compatible = "qcom,pm8921-keypad";
227					reg = <0x148>;
228					interrupt-parent = <&pmicintc>;
229					interrupts = <74 1>, <75 1>;
230					debounce = <15>;
231					scan-delay = <32>;
232					row-hold = <91500>;
233				};
234
235				rtc@11d {
236					compatible = "qcom,pm8921-rtc";
237					interrupt-parent = <&pmicintc>;
238					interrupts = <39 1>;
239					reg = <0x11d>;
240					allow-set-time;
241				};
242			};
243		};
244
245		rng@1a500000 {
246			compatible = "qcom,prng";
247			reg = <0x1a500000 0x200>;
248			clocks = <&gcc PRNG_CLK>;
249			clock-names = "core";
250		};
251
252		/* Temporary fixed regulator */
253		vsdcc_fixed: vsdcc-regulator {
254			compatible = "regulator-fixed";
255			regulator-name = "SDCC Power";
256			regulator-min-microvolt = <2700000>;
257			regulator-max-microvolt = <2700000>;
258			regulator-always-on;
259		};
260
261		amba {
262			compatible = "simple-bus";
263			#address-cells = <1>;
264			#size-cells = <1>;
265			ranges;
266			sdcc1: sdcc@12400000 {
267				status		= "disabled";
268				compatible	= "arm,pl18x", "arm,primecell";
269				arm,primecell-periphid = <0x00051180>;
270				reg		= <0x12400000 0x8000>;
271				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
272				interrupt-names	= "cmd_irq";
273				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
274				clock-names	= "mclk", "apb_pclk";
275				bus-width	= <8>;
276				max-frequency	= <96000000>;
277				non-removable;
278				cap-sd-highspeed;
279				cap-mmc-highspeed;
280				vmmc-supply = <&vsdcc_fixed>;
281			};
282
283			sdcc3: sdcc@12180000 {
284				compatible	= "arm,pl18x", "arm,primecell";
285				arm,primecell-periphid = <0x00051180>;
286				status		= "disabled";
287				reg		= <0x12180000 0x8000>;
288				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
289				interrupt-names	= "cmd_irq";
290				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
291				clock-names	= "mclk", "apb_pclk";
292				bus-width	= <4>;
293				cap-sd-highspeed;
294				cap-mmc-highspeed;
295				max-frequency	= <192000000>;
296				no-1-8-v;
297				vmmc-supply = <&vsdcc_fixed>;
298			};
299		};
300
301		tcsr: syscon@1a400000 {
302			compatible = "qcom,tcsr-msm8960", "syscon";
303			reg = <0x1a400000 0x100>;
304		};
305
306		gsbi@16000000 {
307			compatible = "qcom,gsbi-v1.0.0";
308			cell-index = <1>;
309			reg = <0x16000000 0x100>;
310			clocks = <&gcc GSBI1_H_CLK>;
311			clock-names = "iface";
312			#address-cells = <1>;
313			#size-cells = <1>;
314			ranges;
315
316			spi@16080000 {
317				compatible = "qcom,spi-qup-v1.1.1";
318				#address-cells = <1>;
319				#size-cells = <0>;
320				reg = <0x16080000 0x1000>;
321				interrupts = <0 147 0>;
322				spi-max-frequency = <24000000>;
323				cs-gpios = <&msmgpio 8 0>;
324
325				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
326				clock-names = "core", "iface";
327				status = "disabled";
328			};
329		};
330	};
331};
332