1// SPDX-License-Identifier: GPL-2.0
2/* Copyright 2016-2018 NXP Semiconductors
3 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
4 */
5
6/dts-v1/;
7#include "ls1021a.dtsi"
8
9/ {
10	model = "NXP LS1021A-TSN Board";
11
12	sys_mclk: clock-mclk {
13		compatible = "fixed-clock";
14		#clock-cells = <0>;
15		clock-frequency = <24576000>;
16	};
17
18	reg_vdda_codec: regulator-3V3 {
19		compatible = "regulator-fixed";
20		regulator-name = "3P3V";
21		regulator-min-microvolt = <3300000>;
22		regulator-max-microvolt = <3300000>;
23		regulator-always-on;
24	};
25
26	reg_vddio_codec: regulator-2V5 {
27		compatible = "regulator-fixed";
28		regulator-name = "2P5V";
29		regulator-min-microvolt = <2500000>;
30		regulator-max-microvolt = <2500000>;
31		regulator-always-on;
32	};
33};
34
35&dspi0 {
36	bus-num = <0>;
37	status = "okay";
38
39	/* ADG704BRMZ 1:4 SPI mux/demux */
40	sja1105: ethernet-switch@1 {
41		reg = <0x1>;
42		#address-cells = <1>;
43		#size-cells = <0>;
44		compatible = "nxp,sja1105t";
45		/* 12 MHz */
46		spi-max-frequency = <12000000>;
47		/* Sample data on trailing clock edge */
48		spi-cpha;
49		/* SPI controller settings for SJA1105 timing requirements */
50		fsl,spi-cs-sck-delay = <1000>;
51		fsl,spi-sck-cs-delay = <1000>;
52
53		ports {
54			#address-cells = <1>;
55			#size-cells = <0>;
56
57			port@0 {
58				/* ETH5 written on chassis */
59				label = "swp5";
60				phy-handle = <&rgmii_phy6>;
61				phy-mode = "rgmii-id";
62				reg = <0>;
63			};
64
65			port@1 {
66				/* ETH2 written on chassis */
67				label = "swp2";
68				phy-handle = <&rgmii_phy3>;
69				phy-mode = "rgmii-id";
70				reg = <1>;
71			};
72
73			port@2 {
74				/* ETH3 written on chassis */
75				label = "swp3";
76				phy-handle = <&rgmii_phy4>;
77				phy-mode = "rgmii-id";
78				reg = <2>;
79			};
80
81			port@3 {
82				/* ETH4 written on chassis */
83				label = "swp4";
84				phy-handle = <&rgmii_phy5>;
85				phy-mode = "rgmii-id";
86				reg = <3>;
87			};
88
89			port@4 {
90				/* Internal port connected to eth2 */
91				ethernet = <&enet2>;
92				phy-mode = "rgmii";
93				reg = <4>;
94
95				fixed-link {
96					speed = <1000>;
97					full-duplex;
98				};
99			};
100		};
101	};
102};
103
104&enet0 {
105	tbi-handle = <&tbi0>;
106	phy-handle = <&sgmii_phy2>;
107	phy-mode = "sgmii";
108	status = "okay";
109};
110
111&enet1 {
112	tbi-handle = <&tbi1>;
113	phy-handle = <&sgmii_phy1>;
114	phy-mode = "sgmii";
115	status = "okay";
116};
117
118/* RGMII delays added via PCB traces */
119&enet2 {
120	phy-mode = "rgmii";
121	status = "okay";
122
123	fixed-link {
124		speed = <1000>;
125		full-duplex;
126	};
127};
128
129&esdhc {
130	status = "okay";
131};
132
133&i2c0 {
134	status = "okay";
135
136	/* 3 axis accelerometer */
137	accelerometer@1e {
138		compatible = "fsl,fxls8471";
139		position = <0>;
140		reg = <0x1e>;
141	};
142
143	/* Audio codec (SAI2) */
144	audio-codec@2a {
145		compatible = "fsl,sgtl5000";
146		VDDIO-supply = <&reg_vddio_codec>;
147		VDDA-supply = <&reg_vdda_codec>;
148		#sound-dai-cells = <0>;
149		clocks = <&sys_mclk>;
150		reg = <0x2a>;
151	};
152
153	/* Current sensing circuit for 1V VDDCORE PMIC rail */
154	current-sensor@44 {
155		compatible = "ti,ina220";
156		shunt-resistor = <1000>;
157		reg = <0x44>;
158	};
159
160	/* Current sensing circuit for 12V VCC rail */
161	current-sensor@45 {
162		compatible = "ti,ina220";
163		shunt-resistor = <1000>;
164		reg = <0x45>;
165	};
166
167	/* Thermal monitor - case */
168	temperature-sensor@48 {
169		compatible = "national,lm75";
170		reg = <0x48>;
171	};
172
173	/* Thermal monitor - chip */
174	temperature-sensor@4c {
175		compatible = "ti,tmp451";
176		reg = <0x4c>;
177	};
178
179	eeprom@51 {
180		compatible = "atmel,24c32";
181		reg = <0x51>;
182	};
183
184	/* Unsupported devices:
185	 * - FXAS21002C Gyroscope at 0x20
186	 * - TI ADS7924 4-channel ADC at 0x49
187	 */
188};
189
190&ifc {
191	status = "disabled";
192};
193
194&lpuart0 {
195	status = "okay";
196};
197
198&lpuart3 {
199	status = "okay";
200};
201
202&mdio0 {
203	/* AR8031 */
204	sgmii_phy1: ethernet-phy@1 {
205		reg = <0x1>;
206		/* SGMII1_PHY_INT_B: connected to IRQ2, active low */
207		interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
208	};
209
210	/* AR8031 */
211	sgmii_phy2: ethernet-phy@2 {
212		reg = <0x2>;
213		/* SGMII2_PHY_INT_B: connected to IRQ2, active low */
214		interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
215	};
216
217	/* BCM5464 quad PHY */
218	rgmii_phy3: ethernet-phy@3 {
219		reg = <0x3>;
220	};
221
222	rgmii_phy4: ethernet-phy@4 {
223		reg = <0x4>;
224	};
225
226	rgmii_phy5: ethernet-phy@5 {
227		reg = <0x5>;
228	};
229
230	rgmii_phy6: ethernet-phy@6 {
231		reg = <0x6>;
232	};
233
234	/* SGMII PCS for enet0 */
235	tbi0: tbi-phy@1f {
236		reg = <0x1f>;
237		device_type = "tbi-phy";
238	};
239};
240
241&mdio1 {
242	/* SGMII PCS for enet1 */
243	tbi1: tbi-phy@1f {
244		reg = <0x1f>;
245		device_type = "tbi-phy";
246	};
247};
248
249&qspi {
250	status = "okay";
251
252	flash@0 {
253		/* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */
254		compatible = "jedec,spi-nor", "s25fl256s1", "s25fl512s";
255		spi-max-frequency = <20000000>;
256		#address-cells = <1>;
257		#size-cells = <1>;
258		reg = <0>;
259
260		partitions {
261			compatible = "fixed-partitions";
262			#address-cells = <1>;
263			#size-cells = <1>;
264
265			partition@0 {
266				label = "RCW";
267				reg = <0x0 0x40000>;
268			};
269
270			partition@40000 {
271				label = "U-Boot";
272				reg = <0x40000 0x300000>;
273			};
274
275			partition@340000 {
276				label = "U-Boot Env";
277				reg = <0x340000 0x100000>;
278			};
279		};
280	};
281};
282
283&sai2 {
284	status = "okay";
285};
286
287&sata {
288	status = "okay";
289};
290
291&uart0 {
292	status = "okay";
293};
294