1// SPDX-License-Identifier: (GPL-2.0)
2/*
3 * Device tree for the Kobo Clara HD ebook reader
4 *
5 * Name on mainboard is: 37NB-E60K00+4A4
6 * Serials start with: E60K02 (a number also seen in
7 * vendor kernel sources)
8 *
9 * This mainboard seems to be equipped with different SoCs.
10 * In the Kobo Clara HD ebook reader it is an i.MX6SLL
11 *
12 * Copyright 2019 Andreas Kemnade
13 * based on works
14 * Copyright 2016 Freescale Semiconductor, Inc.
15 */
16
17/dts-v1/;
18
19#include <dt-bindings/input/input.h>
20#include <dt-bindings/gpio/gpio.h>
21#include "imx6sll.dtsi"
22#include "e60k02.dtsi"
23
24/ {
25	model = "Kobo Clara HD";
26	compatible = "kobo,clarahd", "fsl,imx6sll";
27};
28
29&clks {
30	assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
31	assigned-clock-rates = <393216000>;
32};
33
34&cpu0 {
35	arm-supply = <&dcdc3_reg>;
36	soc-supply = <&dcdc1_reg>;
37};
38
39&gpio_keys {
40	pinctrl-names = "default";
41	pinctrl-0 = <&pinctrl_gpio_keys>;
42};
43
44&i2c1 {
45	pinctrl-names = "default","sleep";
46	pinctrl-0 = <&pinctrl_i2c1>;
47	pinctrl-1 = <&pinctrl_i2c1_sleep>;
48};
49
50&i2c2 {
51	pinctrl-names = "default","sleep";
52	pinctrl-0 = <&pinctrl_i2c2>;
53	pinctrl-1 = <&pinctrl_i2c2_sleep>;
54};
55
56&i2c3 {
57	pinctrl-names = "default";
58	pinctrl-0 = <&pinctrl_i2c3>;
59};
60
61&iomuxc {
62	pinctrl-names = "default";
63	pinctrl-0 = <&pinctrl_hog>;
64
65	pinctrl_gpio_keys: gpio-keysgrp {
66		fsl,pins = <
67			MX6SLL_PAD_SD1_DATA1__GPIO5_IO08	0x17059	/* PWR_SW */
68			MX6SLL_PAD_SD1_DATA4__GPIO5_IO12	0x17059	/* HALL_EN */
69		>;
70	};
71
72	pinctrl_hog: hoggrp {
73		fsl,pins = <
74			MX6SLL_PAD_LCD_DATA00__GPIO2_IO20	0x79
75			MX6SLL_PAD_LCD_DATA01__GPIO2_IO21	0x79
76			MX6SLL_PAD_LCD_DATA02__GPIO2_IO22	0x79
77			MX6SLL_PAD_LCD_DATA03__GPIO2_IO23	0x79
78			MX6SLL_PAD_LCD_DATA04__GPIO2_IO24	0x79
79			MX6SLL_PAD_LCD_DATA05__GPIO2_IO25	0x79
80			MX6SLL_PAD_LCD_DATA06__GPIO2_IO26	0x79
81			MX6SLL_PAD_LCD_DATA07__GPIO2_IO27	0x79
82			MX6SLL_PAD_LCD_DATA08__GPIO2_IO28	0x79
83			MX6SLL_PAD_LCD_DATA09__GPIO2_IO29	0x79
84			MX6SLL_PAD_LCD_DATA10__GPIO2_IO30	0x79
85			MX6SLL_PAD_LCD_DATA11__GPIO2_IO31	0x79
86			MX6SLL_PAD_LCD_DATA12__GPIO3_IO00	0x79
87			MX6SLL_PAD_LCD_DATA13__GPIO3_IO01	0x79
88			MX6SLL_PAD_LCD_DATA14__GPIO3_IO02	0x79
89			MX6SLL_PAD_LCD_DATA15__GPIO3_IO03	0x79
90			MX6SLL_PAD_LCD_DATA16__GPIO3_IO04	0x79
91			MX6SLL_PAD_LCD_DATA17__GPIO3_IO05	0x79
92			MX6SLL_PAD_LCD_DATA18__GPIO3_IO06	0x79
93			MX6SLL_PAD_LCD_DATA19__GPIO3_IO07	0x79
94			MX6SLL_PAD_LCD_DATA20__GPIO3_IO08	0x79
95			MX6SLL_PAD_LCD_DATA21__GPIO3_IO09	0x79
96			MX6SLL_PAD_LCD_DATA22__GPIO3_IO10	0x79
97			MX6SLL_PAD_LCD_DATA23__GPIO3_IO11	0x79
98			MX6SLL_PAD_LCD_CLK__GPIO2_IO15		0x79
99			MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16	0x79
100			MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17	0x79
101			MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18	0x79
102			MX6SLL_PAD_LCD_RESET__GPIO2_IO19	0x79
103			MX6SLL_PAD_KEY_COL3__GPIO3_IO30		0x79
104			MX6SLL_PAD_KEY_ROW7__GPIO4_IO07		0x79
105			MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13	0x79
106			MX6SLL_PAD_KEY_COL5__GPIO4_IO02		0x79
107			MX6SLL_PAD_KEY_ROW6__GPIO4_IO05		0x79
108		>;
109	};
110
111	pinctrl_i2c1: i2c1grp {
112		fsl,pins = <
113			MX6SLL_PAD_I2C1_SCL__I2C1_SCL	0x4001f8b1
114			MX6SLL_PAD_I2C1_SDA__I2C1_SDA	0x4001f8b1
115		>;
116	};
117
118	pinctrl_i2c1_sleep: i2c1grp-sleep {
119		fsl,pins = <
120			MX6SLL_PAD_I2C1_SCL__I2C1_SCL	0x400108b1
121			MX6SLL_PAD_I2C1_SDA__I2C1_SDA	0x400108b1
122		>;
123	};
124
125	pinctrl_i2c2: i2c2grp {
126		fsl,pins = <
127			MX6SLL_PAD_I2C2_SCL__I2C2_SCL	0x4001f8b1
128			MX6SLL_PAD_I2C2_SDA__I2C2_SDA	0x4001f8b1
129		>;
130	};
131
132	pinctrl_i2c2_sleep: i2c2grp-sleep {
133		fsl,pins = <
134			MX6SLL_PAD_I2C2_SCL__I2C2_SCL	0x400108b1
135			MX6SLL_PAD_I2C2_SDA__I2C2_SDA	0x400108b1
136		>;
137	};
138
139	pinctrl_i2c3: i2c3grp {
140		fsl,pins = <
141			MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
142			MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
143		>;
144	};
145
146	pinctrl_led: ledgrp {
147		fsl,pins = <
148			MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059
149		>;
150	};
151
152	pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
153		fsl,pins = <
154			MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10	0x10059 /* HWEN */
155		>;
156	};
157
158	pinctrl_ricoh_gpio: ricoh-gpiogrp {
159		fsl,pins = <
160			MX6SLL_PAD_SD1_CLK__GPIO5_IO15	0x1b8b1 /* ricoh619 chg */
161			MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
162			MX6SLL_PAD_KEY_COL2__GPIO3_IO28	0x1b8b1 /* ricoh619 bat_low_int */
163		>;
164	};
165
166	pinctrl_uart1: uart1grp {
167		fsl,pins = <
168			MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
169			MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
170		>;
171	};
172
173	pinctrl_usbotg1: usbotg1grp {
174		fsl,pins = <
175			MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
176		>;
177	};
178
179	pinctrl_usdhc2: usdhc2grp {
180		fsl,pins = <
181			MX6SLL_PAD_SD2_CMD__SD2_CMD		0x17059
182			MX6SLL_PAD_SD2_CLK__SD2_CLK		0x13059
183			MX6SLL_PAD_SD2_DATA0__SD2_DATA0		0x17059
184			MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x17059
185			MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x17059
186			MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x17059
187		>;
188	};
189
190	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
191		fsl,pins = <
192			MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170b9
193			MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130b9
194			MX6SLL_PAD_SD2_DATA0__SD2_DATA0		0x170b9
195			MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170b9
196			MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170b9
197			MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170b9
198		>;
199	};
200
201	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
202		fsl,pins = <
203			MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170f9
204			MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130f9
205			MX6SLL_PAD_SD2_DATA0__SD2_DATA0		0x170f9
206			MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170f9
207			MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170f9
208			MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170f9
209		>;
210	};
211
212	pinctrl_usdhc2_sleep: usdhc2grp-sleep {
213		fsl,pins = <
214			MX6SLL_PAD_SD2_CMD__GPIO5_IO04		0x100f9
215			MX6SLL_PAD_SD2_CLK__GPIO5_IO05		0x100f9
216			MX6SLL_PAD_SD2_DATA0__GPIO5_IO01	0x100f9
217			MX6SLL_PAD_SD2_DATA1__GPIO4_IO30	0x100f9
218			MX6SLL_PAD_SD2_DATA2__GPIO5_IO03	0x100f9
219			MX6SLL_PAD_SD2_DATA3__GPIO4_IO28	0x100f9
220		>;
221	};
222
223	pinctrl_usdhc3: usdhc3grp {
224		fsl,pins = <
225			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x11059
226			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x11059
227			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x11059
228			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x11059
229			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x11059
230			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x11059
231		>;
232	};
233
234	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
235		fsl,pins = <
236			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170b9
237			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170b9
238			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170b9
239			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170b9
240			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170b9
241			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170b9
242		>;
243	};
244
245	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
246		fsl,pins = <
247			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170f9
248			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170f9
249			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170f9
250			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170f9
251			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170f9
252			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170f9
253		>;
254	};
255
256	pinctrl_usdhc3_sleep: usdhc3grp-sleep {
257		fsl,pins = <
258			MX6SLL_PAD_SD3_CMD__GPIO5_IO21	0x100c1
259			MX6SLL_PAD_SD3_CLK__GPIO5_IO18	0x100c1
260			MX6SLL_PAD_SD3_DATA0__GPIO5_IO19	0x100c1
261			MX6SLL_PAD_SD3_DATA1__GPIO5_IO20	0x100c1
262			MX6SLL_PAD_SD3_DATA2__GPIO5_IO16	0x100c1
263			MX6SLL_PAD_SD3_DATA3__GPIO5_IO17	0x100c1
264		>;
265	};
266
267	pinctrl_wifi_power: wifi-powergrp {
268		fsl,pins = <
269			MX6SLL_PAD_SD2_DATA6__GPIO4_IO29	0x10059		/* WIFI_3V3_ON */
270		>;
271	};
272
273	pinctrl_wifi_reset: wifi-resetgrp {
274		fsl,pins = <
275			MX6SLL_PAD_SD2_DATA7__GPIO5_IO00	0x10059		/* WIFI_RST */
276		>;
277	};
278};
279
280&leds {
281	pinctrl-names = "default";
282	pinctrl-0 = <&pinctrl_led>;
283};
284
285&lm3630a {
286	pinctrl-names = "default";
287	pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
288};
289
290&reg_wifi {
291	pinctrl-names = "default";
292	pinctrl-0 = <&pinctrl_wifi_power>;
293};
294
295&ricoh619 {
296	pinctrl-names = "default";
297	pinctrl-0 = <&pinctrl_ricoh_gpio>;
298};
299
300&uart1 {
301	pinctrl-names = "default";
302	pinctrl-0 = <&pinctrl_uart1>;
303};
304
305&usdhc2 {
306	pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
307	pinctrl-0 = <&pinctrl_usdhc2>;
308	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
309	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
310	pinctrl-3 = <&pinctrl_usdhc2_sleep>;
311};
312
313&usdhc3 {
314	pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
315	pinctrl-0 = <&pinctrl_usdhc3>;
316	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
317	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
318	pinctrl-3 = <&pinctrl_usdhc3_sleep>;
319};
320
321&wifi_pwrseq {
322	pinctrl-names = "default";
323	pinctrl-0 = <&pinctrl_wifi_reset>;
324};
325