1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2016-2017 Zodiac Inflight Innovations
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/sound/fsl-imx-audmux.h>
8
9/ {
10	chosen {
11		stdout-path = &uart1;
12	};
13
14	aliases {
15		mdio-gpio0 = &mdio1;
16		rtc0 = &ds1341;
17	};
18
19	mdio1: mdio {
20		compatible = "virtual,mdio-gpio";
21		#address-cells = <1>;
22		#size-cells = <0>;
23		pinctrl-names = "default";
24		pinctrl-0 = <&pinctrl_mdio1>;
25		gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
26		         &gpio6 4 GPIO_ACTIVE_HIGH>;
27
28		phy: ethernet-phy@0 {
29			pinctrl-0 = <&pinctrl_rmii_phy_irq>;
30			pinctrl-names = "default";
31			reg = <0>;
32			interrupt-parent = <&gpio3>;
33			interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
34		};
35	};
36
37	reg_28p0v: regulator-28p0v {
38		compatible = "regulator-fixed";
39		regulator-name = "28V_IN";
40		regulator-min-microvolt = <28000000>;
41		regulator-max-microvolt = <28000000>;
42		regulator-always-on;
43	};
44
45	reg_12p0v: regulator-12p0v {
46		compatible = "regulator-fixed";
47		vin-supply = <&reg_28p0v>;
48		regulator-name = "12V_MAIN";
49		regulator-min-microvolt = <12000000>;
50		regulator-max-microvolt = <12000000>;
51		regulator-always-on;
52	};
53
54	reg_5p0v_main: regulator-5p0v-main {
55		compatible = "regulator-fixed";
56		vin-supply = <&reg_12p0v>;
57		regulator-name = "5V_MAIN";
58		regulator-min-microvolt = <5000000>;
59		regulator-max-microvolt = <5000000>;
60		regulator-always-on;
61	};
62
63	reg_3p3v_pmic: regulator-3p3v-pmic {
64		compatible = "regulator-fixed";
65		vin-supply = <&reg_12p0v>;
66		regulator-name = "PMIC_3V3";
67		regulator-min-microvolt = <3300000>;
68		regulator-max-microvolt = <3300000>;
69		regulator-always-on;
70	};
71
72	reg_3p3v: regulator-3p3v {
73		compatible = "regulator-fixed";
74		vin-supply = <&reg_3p3v_pmic>;
75		regulator-name = "GEN_3V3";
76		regulator-min-microvolt = <3300000>;
77		regulator-max-microvolt = <3300000>;
78		regulator-always-on;
79	};
80
81	reg_3p3v_sd: regulator-3p3v-sd {
82		compatible = "regulator-fixed";
83		pinctrl-names = "default";
84		pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
85		vin-supply = <&reg_3p3v>;
86		regulator-name = "3V3_SD";
87		regulator-min-microvolt = <3300000>;
88		regulator-max-microvolt = <3300000>;
89		gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
90		startup-delay-us = <1000>;
91		enable-active-high;
92		regulator-always-on;
93	};
94
95	reg_3p3v_display: regulator-3p3v-display {
96		compatible = "regulator-fixed";
97		vin-supply = <&reg_12p0v>;
98		regulator-name = "3V3_DISPLAY";
99		regulator-min-microvolt = <3300000>;
100		regulator-max-microvolt = <3300000>;
101		regulator-always-on;
102	};
103
104	reg_3p3v_ssd: regulator-3p3v-ssd {
105		compatible = "regulator-fixed";
106		vin-supply = <&reg_12p0v>;
107		regulator-name = "3V3_SSD";
108		regulator-min-microvolt = <3300000>;
109		regulator-max-microvolt = <3300000>;
110		regulator-always-on;
111	};
112
113	sound1 {
114		compatible = "simple-audio-card";
115		simple-audio-card,name = "Front";
116		simple-audio-card,format = "i2s";
117		simple-audio-card,bitclock-master = <&sound1_codec>;
118		simple-audio-card,frame-master = <&sound1_codec>;
119		simple-audio-card,widgets =
120			"Headphone", "Headphone Jack";
121		simple-audio-card,routing =
122			"Headphone Jack", "HPLEFT",
123			"Headphone Jack", "HPRIGHT",
124			"LEFTIN", "HPL",
125			"RIGHTIN", "HPR";
126		simple-audio-card,aux-devs = <&hpa1>;
127
128		sound1_cpu: simple-audio-card,cpu {
129			sound-dai = <&ssi2>;
130		};
131
132		sound1_codec: simple-audio-card,codec {
133			sound-dai = <&codec1>;
134			clocks = <&cs2000>;
135		};
136	};
137
138	sound2 {
139		compatible = "simple-audio-card";
140		simple-audio-card,name = "Back";
141		simple-audio-card,format = "i2s";
142		simple-audio-card,bitclock-master = <&sound2_codec>;
143		simple-audio-card,frame-master = <&sound2_codec>;
144		simple-audio-card,widgets =
145			"Headphone", "Headphone Jack";
146		simple-audio-card,routing =
147			"Headphone Jack", "HPLEFT",
148			"Headphone Jack", "HPRIGHT",
149			"LEFTIN", "HPL",
150			"RIGHTIN", "HPR";
151		simple-audio-card,aux-devs = <&hpa2>;
152
153		sound2_cpu: simple-audio-card,cpu {
154			sound-dai = <&ssi1>;
155		};
156
157		sound2_codec: simple-audio-card,codec {
158			sound-dai = <&codec2>;
159			clocks = <&cs2000>;
160		};
161	};
162
163	panel {
164		power-supply = <&reg_3p3v_display>;
165		backlight = <&sp_backlight>;
166		status = "disabled";
167
168		port {
169			panel_in: endpoint {
170				remote-endpoint = <&lvds0_out>;
171			};
172		};
173	};
174
175	disp0: disp0 {
176		#address-cells = <1>;
177		#size-cells = <0>;
178		compatible = "fsl,imx-parallel-display";
179		pinctrl-names = "default";
180		pinctrl-0 = <&pinctrl_disp0>;
181		status = "disabled";
182
183		port@0 {
184			reg = <0>;
185
186			disp0_in_0: endpoint {
187				remote-endpoint = <&ipu1_di0_disp0>;
188			};
189		};
190
191		port@1 {
192			reg = <1>;
193
194			disp0_out: endpoint {
195				remote-endpoint = <&tc358767_in>;
196			};
197		};
198	};
199
200	cs2000_ref: cs2000-ref {
201		compatible = "fixed-clock";
202		#clock-cells = <0>;
203		clock-frequency = <24576000>;
204	};
205
206	cs2000_in_dummy: cs2000-in-dummy {
207		compatible = "fixed-clock";
208		#clock-cells = <0>;
209		clock-frequency = <0>;
210	};
211
212	edp_refclk: edp-refclk {
213		compatible = "fixed-clock";
214		#clock-cells = <0>;
215		clock-frequency = <19200000>;
216	};
217};
218
219&clks {
220	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
221	                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
222	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
223	                         <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
224};
225
226&cpu0 {
227	fsl,soc-operating-points = <
228		/* ARM kHz  SOC-PU uV */
229		1200000 1300000
230		996000	1275000
231		852000	1275000
232		792000	1200000
233		396000	1200000
234	>;
235};
236
237&reg_arm {
238	vin-supply = <&sw1a_reg>;
239};
240
241&reg_pu {
242	vin-supply = <&sw1c_reg>;
243};
244
245&reg_soc {
246	vin-supply = <&sw1c_reg>;
247};
248
249&ldb {
250	lvds-channel@0 {
251		port@4 {
252			reg = <4>;
253
254			lvds0_out: endpoint {
255				remote-endpoint = <&panel_in>;
256			};
257		};
258	};
259};
260
261&uart1 {
262	pinctrl-names = "default";
263	pinctrl-0 = <&pinctrl_uart1>;
264	status = "okay";
265};
266
267&uart3 {
268	pinctrl-names = "default";
269	pinctrl-0 = <&pinctrl_uart3>;
270	uart-has-rtscts;
271	linux,rs485-enabled-at-boot-time;
272	status = "okay";
273};
274
275&uart4 {
276	pinctrl-names = "default";
277	pinctrl-0 = <&pinctrl_uart4>;
278	status = "okay";
279
280	rave-sp {
281		compatible = "zii,rave-sp-rdu2";
282		current-speed = <1000000>;
283		#address-cells = <1>;
284		#size-cells = <1>;
285
286		watchdog {
287			compatible = "zii,rave-sp-watchdog";
288		};
289
290		sp_backlight: backlight {
291			compatible = "zii,rave-sp-backlight";
292		};
293
294		pwrbutton {
295			compatible = "zii,rave-sp-pwrbutton";
296		};
297
298		eeprom@a3 {
299			compatible = "zii,rave-sp-eeprom";
300			reg = <0xa3 0x4000>;
301			#address-cells = <1>;
302			#size-cells = <1>;
303			zii,eeprom-name = "dds-eeprom";
304		};
305
306		eeprom@a4 {
307			compatible = "zii,rave-sp-eeprom";
308			reg = <0xa4 0x4000>;
309			#address-cells = <1>;
310			#size-cells = <1>;
311			zii,eeprom-name = "main-eeprom";
312		};
313	};
314};
315
316&ecspi1 {
317	pinctrl-names = "default";
318	pinctrl-0 = <&pinctrl_ecspi1>;
319	cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
320	status = "okay";
321
322	flash@0 {
323		compatible = "st,m25p128", "jedec,spi-nor";
324		spi-max-frequency = <20000000>;
325		reg = <0>;
326	};
327};
328
329&gpio3 {
330	pinctrl-names = "default";
331	pinctrl-0 = <&pinctrl_gpio3_hog>;
332
333	usb-emulation {
334		gpio-hog;
335		gpios = <19 GPIO_ACTIVE_HIGH>;
336		output-low;
337		line-name = "usb-emulation";
338	};
339
340	usb-mode1 {
341		gpio-hog;
342		gpios = <20 GPIO_ACTIVE_HIGH>;
343		output-high;
344		line-name = "usb-mode1";
345	};
346
347	usb-pwr {
348		gpio-hog;
349		gpios = <22 GPIO_ACTIVE_LOW>;
350		output-high;
351		line-name = "usb-pwr-ctrl-en-n";
352	};
353
354	usb-mode2 {
355		gpio-hog;
356		gpios = <23 GPIO_ACTIVE_HIGH>;
357		output-high;
358		line-name = "usb-mode2";
359	};
360};
361
362&i2c1 {
363	pinctrl-names = "default";
364	pinctrl-0 = <&pinctrl_i2c1>;
365	clock-frequency = <100000>;
366	status = "okay";
367
368	codec2: codec@18 {
369		compatible = "ti,tlv320dac3100";
370		pinctrl-names = "default";
371		pinctrl-0 = <&pinctrl_codec2>;
372		reg = <0x18>;
373		#sound-dai-cells = <0>;
374		HPVDD-supply = <&reg_3p3v>;
375		SPRVDD-supply = <&reg_3p3v>;
376		SPLVDD-supply = <&reg_3p3v>;
377		AVDD-supply = <&reg_3p3v>;
378		IOVDD-supply = <&reg_3p3v>;
379		DVDD-supply = <&vgen4_reg>;
380		reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
381	};
382
383	accel@1c {
384		pinctrl-names = "default";
385		pinctrl-0 = <&pinctrl_accel>;
386		compatible = "fsl,mma8451";
387		reg = <0x1c>;
388		interrupt-parent = <&gpio1>;
389		interrupt-names = "INT2";
390		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
391		vdd-supply = <&reg_3p3v>;
392		vddio-supply = <&reg_3p3v>;
393	};
394
395	hpa2: amp@60 {
396		compatible = "ti,tpa6130a2";
397		pinctrl-names = "default";
398		pinctrl-0 = <&pinctrl_tpa2>;
399		reg = <0x60>;
400		power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
401		Vdd-supply = <&reg_5p0v_main>;
402	};
403
404	edp-bridge@68 {
405		compatible = "toshiba,tc358767";
406		pinctrl-names = "default";
407		pinctrl-0 = <&pinctrl_tc358767>;
408		reg = <0x68>;
409		shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
410		clock-names = "ref";
411		clocks = <&edp_refclk>;
412		status = "disabled";
413
414		ports {
415			#address-cells = <1>;
416			#size-cells = <0>;
417
418			port@1 {
419				reg = <1>;
420
421				tc358767_in: endpoint {
422					remote-endpoint = <&disp0_out>;
423				};
424			};
425		};
426	};
427};
428
429&i2c2 {
430	pinctrl-names = "default";
431	pinctrl-0 = <&pinctrl_i2c2>;
432	clock-frequency = <100000>;
433	status = "okay";
434
435	pmic@8 {
436		compatible = "fsl,pfuze100";
437		pinctrl-names = "default";
438		pinctrl-0 = <&pinctrl_pfuze100_irq>;
439		reg = <0x08>;
440		interrupt-parent = <&gpio7>;
441		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
442
443		regulators {
444			sw1a_reg: sw1ab {
445				regulator-min-microvolt = <300000>;
446				regulator-max-microvolt = <1875000>;
447				regulator-boot-on;
448				regulator-always-on;
449				regulator-ramp-delay = <6250>;
450			};
451
452			sw1c_reg: sw1c {
453				regulator-min-microvolt = <300000>;
454				regulator-max-microvolt = <1875000>;
455				regulator-boot-on;
456				regulator-always-on;
457				regulator-ramp-delay = <6250>;
458			};
459
460			sw2_reg: sw2 {
461				regulator-min-microvolt = <800000>;
462				regulator-max-microvolt = <3000000>;
463				regulator-boot-on;
464				regulator-always-on;
465			};
466
467			sw3a_reg: sw3a {
468				regulator-min-microvolt = <400000>;
469				regulator-max-microvolt = <1500000>;
470				regulator-boot-on;
471				regulator-always-on;
472			};
473
474			sw3b_reg: sw3b {
475				regulator-min-microvolt = <400000>;
476				regulator-max-microvolt = <1500000>;
477				regulator-boot-on;
478				regulator-always-on;
479			};
480
481			sw4_reg: sw4 {
482				regulator-min-microvolt = <800000>;
483				regulator-max-microvolt = <1800000>;
484				regulator-boot-on;
485				regulator-always-on;
486			};
487
488			snvs_reg: vsnvs {
489				regulator-min-microvolt = <1000000>;
490				regulator-max-microvolt = <3000000>;
491				regulator-boot-on;
492				regulator-always-on;
493			};
494
495			vref_reg: vrefddr {
496				regulator-boot-on;
497				regulator-always-on;
498			};
499
500			vgen2_reg: vgen2 {
501				regulator-min-microvolt = <1000000>;
502				regulator-max-microvolt = <1500000>;
503				regulator-always-on;
504			};
505
506			vgen4_reg: vgen4 {
507				regulator-min-microvolt = <1200000>;
508				regulator-max-microvolt = <1800000>;
509				regulator-always-on;
510			};
511
512			vgen5_reg: vgen5 {
513				regulator-min-microvolt = <1800000>;
514				regulator-max-microvolt = <2500000>;
515				regulator-always-on;
516			};
517
518			vgen6_reg: vgen6 {
519				regulator-min-microvolt = <1800000>;
520				regulator-max-microvolt = <2800000>;
521				regulator-always-on;
522			};
523		};
524	};
525
526	watchdog@38 {
527		compatible = "zii,rave-wdt";
528		reg = <0x38>;
529	};
530
531	temp-sense@48 {
532		compatible = "national,lm75";
533		reg = <0x48>;
534	};
535
536	cs2000: clkgen@4e {
537		compatible = "cirrus,cs2000-cp";
538		reg = <0x4e>;
539		#clock-cells = <0>;
540		clock-names = "clk_in", "ref_clk";
541		clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
542		assigned-clocks = <&cs2000>;
543		assigned-clock-rates = <24000000>;
544	};
545
546	eeprom@54 {
547		compatible = "atmel,24c128";
548		reg = <0x54>;
549	};
550
551	ds1341: rtc@68 {
552		compatible = "dallas,ds1341";
553		reg = <0x68>;
554	};
555};
556
557&i2c3 {
558	pinctrl-names = "default";
559	pinctrl-0 = <&pinctrl_i2c3>;
560	clock-frequency = <400000>;
561	status = "okay";
562
563	codec1: codec@18 {
564		compatible = "ti,tlv320dac3100";
565		pinctrl-names = "default";
566		pinctrl-0 = <&pinctrl_codec1>;
567		reg = <0x18>;
568		#sound-dai-cells = <0>;
569		HPVDD-supply = <&reg_3p3v>;
570		SPRVDD-supply = <&reg_3p3v>;
571		SPLVDD-supply = <&reg_3p3v>;
572		AVDD-supply = <&reg_3p3v>;
573		IOVDD-supply = <&reg_3p3v>;
574		DVDD-supply = <&vgen4_reg>;
575		reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
576	};
577
578	touchscreen@20 {
579		compatible = "syna,rmi4-i2c";
580		pinctrl-names = "default";
581		pinctrl-0 = <&pinctrl_ts>;
582		reg = <0x20>;
583		interrupt-parent = <&gpio1>;
584		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
585		vdd-supply = <&reg_5p0v_main>;
586		vio-supply = <&reg_3p3v>;
587
588		#address-cells = <1>;
589		#size-cells = <0>;
590
591		rmi4-f01@1 {
592			reg = <0x1>;
593			syna,nosleep-mode = <2>;
594		};
595
596		rmi4-f11@11 {
597			reg = <0x11>;
598			touchscreen-inverted-x;
599			touchscreen-swapped-x-y;
600			syna,sensor-type = <1>;
601		};
602
603		rmi4-f12@12 {
604			reg = <0x12>;
605			touchscreen-inverted-x;
606			touchscreen-swapped-x-y;
607			syna,sensor-type = <1>;
608		};
609	};
610
611	touchscreen@2a {
612		compatible = "eeti,exc3000";
613		pinctrl-names = "default";
614		pinctrl-0 = <&pinctrl_ts>;
615		reg = <0x2a>;
616		interrupt-parent = <&gpio1>;
617		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
618		touchscreen-inverted-x;
619		touchscreen-swapped-x-y;
620		status = "disabled";
621	};
622
623	reg_5p0v_user_usb: charger@32 {
624		compatible = "microchip,ucs1002";
625		pinctrl-names = "default";
626		pinctrl-0 = <&pinctrl_ucs1002_pins>;
627		reg = <0x32>;
628		interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>,
629				      <&gpio3 21 IRQ_TYPE_EDGE_BOTH>;
630		interrupt-names = "a_det", "alert";
631	};
632
633	hpa1: amp@60 {
634		compatible = "ti,tpa6130a2";
635		pinctrl-names = "default";
636		pinctrl-0 = <&pinctrl_tpa1>;
637		reg = <0x60>;
638		power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
639		Vdd-supply = <&reg_5p0v_main>;
640	};
641};
642
643&ipu1_di0_disp0 {
644	remote-endpoint = <&disp0_in_0>;
645};
646
647&pcie {
648	pinctrl-names = "default";
649	pinctrl-0 = <&pinctrl_pcie>;
650	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
651	status = "okay";
652
653	host@0 {
654		reg = <0 0 0 0 0>;
655
656		#address-cells = <3>;
657		#size-cells = <2>;
658
659		i210: i210@0 {
660			reg = <0 0 0 0 0>;
661		};
662	};
663};
664
665&usdhc2 {
666	pinctrl-names = "default";
667	pinctrl-0 = <&pinctrl_usdhc2>;
668	bus-width = <4>;
669	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
670	disable-wp;
671	vmmc-supply = <&reg_3p3v_sd>;
672	vqmmc-supply = <&reg_3p3v>;
673	no-1-8-v;
674	no-sdio;
675	status = "okay";
676};
677
678&usdhc3 {
679	pinctrl-names = "default";
680	pinctrl-0 = <&pinctrl_usdhc3>;
681	bus-width = <4>;
682	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
683	disable-wp;
684	vmmc-supply = <&reg_3p3v_sd>;
685	vqmmc-supply = <&reg_3p3v>;
686	no-1-8-v;
687	no-sdio;
688	status = "okay";
689};
690
691&usdhc4 {
692	pinctrl-names = "default";
693	pinctrl-0 = <&pinctrl_usdhc4>;
694	bus-width = <8>;
695	vmmc-supply = <&reg_3p3v>;
696	vqmmc-supply = <&reg_3p3v>;
697	no-1-8-v;
698	non-removable;
699	no-sdio;
700	no-sd;
701	status = "okay";
702};
703
704&sata {
705	target-supply = <&reg_3p3v_ssd>;
706	status = "okay";
707};
708
709&fec {
710	pinctrl-names = "default";
711	pinctrl-0 = <&pinctrl_enet>;
712	phy-mode = "rmii";
713	phy-handle = <&phy>;
714	phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
715	phy-reset-duration = <100>;
716	phy-supply = <&reg_3p3v>;
717	status = "okay";
718
719	mdio {
720		#address-cells = <1>;
721		#size-cells = <0>;
722		clock-frequency = <12500000>;
723		suppress-preamble;
724		status = "okay";
725
726		switch: switch@0 {
727			compatible = "marvell,mv88e6085";
728			pinctrl-0 = <&pinctrl_switch_irq>;
729			pinctrl-names = "default";
730			reg = <0>;
731			dsa,member = <0 0>;
732			eeprom-length = <512>;
733			interrupt-parent = <&gpio6>;
734			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
735			interrupt-controller;
736			#interrupt-cells = <2>;
737
738			ports {
739				#address-cells = <1>;
740				#size-cells = <0>;
741
742				port@0 {
743					reg = <0>;
744					label = "gigabit_proc";
745					phy-handle = <&switchphy0>;
746				};
747
748				port@1 {
749					reg = <1>;
750					label = "netaux";
751					phy-handle = <&switchphy1>;
752				};
753
754				port@2 {
755					reg = <2>;
756					label = "cpu";
757					ethernet = <&fec>;
758
759					fixed-link {
760						speed = <100>;
761						full-duplex;
762					};
763				};
764
765				port@3 {
766					reg = <3>;
767					label = "netright";
768					phy-handle = <&switchphy3>;
769				};
770
771				port@4 {
772					reg = <4>;
773					label = "netleft";
774					phy-handle = <&switchphy4>;
775				};
776			};
777
778			mdio {
779				#address-cells = <1>;
780				#size-cells = <0>;
781
782				switchphy0: switchphy@0 {
783					reg = <0>;
784					interrupt-parent = <&switch>;
785					interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
786				};
787
788				switchphy1: switchphy@1 {
789					reg = <1>;
790					interrupt-parent = <&switch>;
791					interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
792				};
793
794				switchphy2: switchphy@2 {
795					reg = <2>;
796					interrupt-parent = <&switch>;
797					interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
798				};
799
800				switchphy3: switchphy@3 {
801					reg = <3>;
802					interrupt-parent = <&switch>;
803					interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
804				};
805
806				switchphy4: switchphy@4 {
807					reg = <4>;
808					interrupt-parent = <&switch>;
809					interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
810				};
811			};
812		};
813	};
814};
815
816&usbh1 {
817	vbus-supply = <&reg_5p0v_main>;
818	disable-over-current;
819	maximum-speed = "full-speed";
820	status = "okay";
821};
822
823&usbotg {
824	vbus-supply = <&reg_5p0v_user_usb>;
825	disable-over-current;
826	dr_mode = "host";
827	status = "okay";
828};
829
830&snvs_rtc {
831	status = "disabled";
832};
833
834&ssi1 {
835	status = "okay";
836};
837
838&ssi2 {
839	status = "okay";
840};
841
842&audmux {
843	pinctrl-names = "default";
844	pinctrl-0 = <&pinctrl_audmux>;
845	status = "okay";
846
847	ssi1 {
848		fsl,audmux-port = <0>;
849		fsl,port-config = <
850			(IMX_AUDMUX_V2_PTCR_SYN |
851			 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
852			 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
853			 IMX_AUDMUX_V2_PTCR_TFSDIR |
854			 IMX_AUDMUX_V2_PTCR_TCLKDIR)
855			IMX_AUDMUX_V2_PDCR_RXDSEL(2)
856		>;
857	};
858
859	aud3 {
860		fsl,audmux-port = <2>;
861		fsl,port-config = <
862			IMX_AUDMUX_V2_PTCR_SYN
863			IMX_AUDMUX_V2_PDCR_RXDSEL(0)
864		>;
865	};
866
867	ssi2 {
868		fsl,audmux-port = <1>;
869		fsl,port-config = <
870			(IMX_AUDMUX_V2_PTCR_SYN |
871			 IMX_AUDMUX_V2_PTCR_TFSEL(4) |
872			 IMX_AUDMUX_V2_PTCR_TCSEL(4) |
873			 IMX_AUDMUX_V2_PTCR_TFSDIR |
874			 IMX_AUDMUX_V2_PTCR_TCLKDIR)
875			IMX_AUDMUX_V2_PDCR_RXDSEL(4)
876		>;
877	};
878
879	aud5 {
880		fsl,audmux-port = <4>;
881		fsl,port-config = <
882			IMX_AUDMUX_V2_PTCR_SYN
883			IMX_AUDMUX_V2_PDCR_RXDSEL(1)
884		>;
885	};
886};
887
888&wdog1 {
889	status = "disabled";
890};
891
892&iomuxc {
893	pinctrl_accel: accelgrp {
894		fsl,pins = <
895			MX6QDL_PAD_SD1_CLK__GPIO1_IO20		0x4001b000
896		>;
897	};
898
899	pinctrl_audmux: audmuxgrp {
900		fsl,pins = <
901			MX6QDL_PAD_KEY_COL0__AUD5_TXC		0x130b0
902			MX6QDL_PAD_KEY_ROW0__AUD5_TXD		0x130b0
903			MX6QDL_PAD_KEY_COL1__AUD5_TXFS		0x130b0
904			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
905			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x130b0
906			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
907		>;
908	};
909
910	pinctrl_codec1: dac1grp {
911		fsl,pins = <
912			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x40000038
913		>;
914	};
915
916	pinctrl_codec2: dac2grp {
917		fsl,pins = <
918			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x40000038
919		>;
920	};
921
922	pinctrl_disp0: disp0grp {
923		fsl,pins = <
924			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
925			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
926			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
927			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
928			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
929			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
930			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
931			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
932			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
933			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
934			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
935			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
936			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
937			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
938			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
939			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
940			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
941			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
942			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
943			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
944			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
945			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
946			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
947			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
948			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
949			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
950			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
951			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
952		>;
953	};
954
955	pinctrl_ecspi1: ecspi1grp {
956		fsl,pins = <
957			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
958			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
959			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
960			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b1
961		>;
962	};
963
964	pinctrl_enet: enetgrp {
965		fsl,pins = <
966			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x000b1
967			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b1
968			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x100f5
969			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x100f5
970			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x100c0
971			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x100c0
972			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x100f5
973			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x100f5
974			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x40010040
975			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x100b0
976			MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23	0x1b0b0
977		>;
978	};
979
980	pinctrl_gpio3_hog: gpio3hoggrp {
981		fsl,pins = <
982			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x1b0b0
983			MX6QDL_PAD_EIM_D20__GPIO3_IO20		0x1b0b0
984			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0
985			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x1b0b0
986		>;
987	};
988
989	pinctrl_i2c1: i2c1grp {
990		fsl,pins = <
991			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
992			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
993		>;
994	};
995
996	pinctrl_i2c2: i2c2grp {
997		fsl,pins = <
998			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
999			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
1000		>;
1001	};
1002
1003	pinctrl_i2c3: i2c3grp {
1004		fsl,pins = <
1005			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
1006			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
1007		>;
1008	};
1009
1010	pinctrl_mdio1: bitbangmdiogrp {
1011		fsl,pins = <
1012			/* Bitbang MDIO for DEB Switch */
1013			MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05	0x4001b030
1014			MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04	0x40018830
1015		>;
1016	};
1017
1018	pinctrl_pcie: pciegrp {
1019		fsl,pins = <
1020			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x10038
1021		>;
1022	};
1023
1024	pinctrl_pfuze100_irq: pfuze100grp {
1025		fsl,pins = <
1026			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x40010000
1027		>;
1028	};
1029
1030	pinctrl_reg_3p3v_sd: mmcsupply1grp {
1031		fsl,pins = <
1032			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x858
1033		>;
1034	};
1035
1036	pinctrl_rmii_phy_irq: phygrp {
1037		fsl,pins = <
1038			MX6QDL_PAD_EIM_D30__GPIO3_IO30		0x40010000
1039		>;
1040	};
1041
1042	pinctrl_switch_irq: switchgrp {
1043		fsl,pins = <
1044			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x4001b000
1045		>;
1046	};
1047
1048	pinctrl_tc358767: tc358767grp {
1049		fsl,pins = <
1050			MX6QDL_PAD_GPIO_9__GPIO1_IO09		0x10
1051		>;
1052	};
1053
1054	pinctrl_tpa1: tpa6130-1grp {
1055		fsl,pins = <
1056			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x40000038
1057		>;
1058	};
1059
1060	pinctrl_tpa2: tpa6130-2grp {
1061		fsl,pins = <
1062			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x40000038
1063		>;
1064	};
1065
1066	pinctrl_ts: tsgrp {
1067		fsl,pins = <
1068			MX6QDL_PAD_GPIO_8__GPIO1_IO08		0x1b0b0
1069			MX6QDL_PAD_GPIO_7__GPIO1_IO07		0x1b0b0
1070		>;
1071	};
1072
1073	pinctrl_uart1: uart1grp {
1074		fsl,pins = <
1075			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
1076			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
1077		>;
1078	};
1079
1080	pinctrl_uart3: uart3grp {
1081		fsl,pins = <
1082			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
1083			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
1084			MX6QDL_PAD_EIM_D31__UART3_RTS_B		0x1b0b1
1085		>;
1086	};
1087
1088	pinctrl_uart4: uart4grp {
1089		fsl,pins = <
1090			MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA	0x1b0b1
1091			MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA	0x1b0b1
1092		>;
1093	};
1094
1095	pinctrl_ucs1002_pins: ucs1002grp {
1096		fsl,pins = <
1097			MX6QDL_PAD_EIM_A25__GPIO5_IO02  	0x1b0b0
1098			MX6QDL_PAD_EIM_D21__GPIO3_IO21  	0x1b0b0
1099		>;
1100	};
1101
1102	pinctrl_usdhc2: usdhc2grp {
1103		fsl,pins = <
1104			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x10059
1105			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10069
1106			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
1107			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
1108			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
1109			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
1110			MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x40010040
1111		>;
1112	};
1113
1114	pinctrl_usdhc3: usdhc3grp {
1115		fsl,pins = <
1116			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x10059
1117			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10069
1118			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
1119			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
1120			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
1121			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
1122			MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x40010040
1123
1124		>;
1125	};
1126
1127	pinctrl_usdhc4: usdhc4grp {
1128		fsl,pins = <
1129			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
1130			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
1131			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
1132			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
1133			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
1134			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
1135			MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
1136			MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
1137			MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
1138			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
1139			MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x1b0b1
1140		>;
1141	};
1142};
1143