1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11	/* these are used by bootloader for disabling nodes */
12	aliases {
13		led0 = &led0;
14		led1 = &led1;
15		led2 = &led2;
16		nand = &gpmi;
17		usb0 = &usbh1;
18		usb1 = &usbotg;
19	};
20
21	chosen {
22		stdout-path = &uart2;
23	};
24
25	gpio-keys {
26		compatible = "gpio-keys";
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		user-pb {
31			label = "user_pb";
32			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
33			linux,code = <BTN_0>;
34		};
35
36		user-pb1x {
37			label = "user_pb1x";
38			linux,code = <BTN_1>;
39			interrupt-parent = <&gsc>;
40			interrupts = <0>;
41		};
42
43		key-erased {
44			label = "key-erased";
45			linux,code = <BTN_2>;
46			interrupt-parent = <&gsc>;
47			interrupts = <1>;
48		};
49
50		eeprom-wp {
51			label = "eeprom_wp";
52			linux,code = <BTN_3>;
53			interrupt-parent = <&gsc>;
54			interrupts = <2>;
55		};
56
57		tamper {
58			label = "tamper";
59			linux,code = <BTN_4>;
60			interrupt-parent = <&gsc>;
61			interrupts = <5>;
62		};
63
64		switch-hold {
65			label = "switch_hold";
66			linux,code = <BTN_5>;
67			interrupt-parent = <&gsc>;
68			interrupts = <7>;
69		};
70	};
71
72	leds {
73		compatible = "gpio-leds";
74		pinctrl-names = "default";
75		pinctrl-0 = <&pinctrl_gpio_leds>;
76
77		led0: user1 {
78			label = "user1";
79			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
80			default-state = "on";
81			linux,default-trigger = "heartbeat";
82		};
83
84		led1: user2 {
85			label = "user2";
86			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
87			default-state = "off";
88		};
89
90		led2: user3 {
91			label = "user3";
92			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
93			default-state = "off";
94		};
95	};
96
97	memory@10000000 {
98		device_type = "memory";
99		reg = <0x10000000 0x40000000>;
100	};
101
102	pps {
103		compatible = "pps-gpio";
104		pinctrl-names = "default";
105		pinctrl-0 = <&pinctrl_pps>;
106		gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
107	};
108
109	reg_3p3v: regulator-3p3v {
110		compatible = "regulator-fixed";
111		regulator-name = "3P3V";
112		regulator-min-microvolt = <3300000>;
113		regulator-max-microvolt = <3300000>;
114		regulator-always-on;
115	};
116
117	reg_usb_vbus: regulator-5p0v {
118		compatible = "regulator-fixed";
119		regulator-name = "usb_vbus";
120		regulator-min-microvolt = <5000000>;
121		regulator-max-microvolt = <5000000>;
122		regulator-always-on;
123	};
124};
125
126&can1 {
127	pinctrl-names = "default";
128	pinctrl-0 = <&pinctrl_flexcan1>;
129	status = "okay";
130};
131
132&ecspi2 {
133	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
134	pinctrl-names = "default";
135	pinctrl-0 = <&pinctrl_ecspi2>;
136	status = "okay";
137};
138
139&fec {
140	pinctrl-names = "default";
141	pinctrl-0 = <&pinctrl_enet>;
142	phy-mode = "rgmii-id";
143	status = "okay";
144};
145
146&gpmi {
147	pinctrl-names = "default";
148	pinctrl-0 = <&pinctrl_gpmi_nand>;
149	status = "okay";
150};
151
152&i2c1 {
153	clock-frequency = <100000>;
154	pinctrl-names = "default";
155	pinctrl-0 = <&pinctrl_i2c1>;
156	status = "okay";
157
158	gsc: gsc@20 {
159		compatible = "gw,gsc";
160		reg = <0x20>;
161		interrupt-parent = <&gpio1>;
162		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
163		interrupt-controller;
164		#interrupt-cells = <1>;
165		#address-cells = <1>;
166		#size-cells = <0>;
167
168		adc {
169			compatible = "gw,gsc-adc";
170			#address-cells = <1>;
171			#size-cells = <0>;
172
173			channel@0 {
174				gw,mode = <0>;
175				reg = <0x00>;
176				label = "temp";
177			};
178
179			channel@2 {
180				gw,mode = <1>;
181				reg = <0x02>;
182				label = "vdd_vin";
183			};
184
185			channel@5 {
186				gw,mode = <1>;
187				reg = <0x05>;
188				label = "vdd_3p3";
189			};
190
191			channel@8 {
192				gw,mode = <1>;
193				reg = <0x08>;
194				label = "vdd_bat";
195			};
196
197			channel@b {
198				gw,mode = <1>;
199				reg = <0x0b>;
200				label = "vdd_5p0";
201			};
202
203			channel@e {
204				gw,mode = <1>;
205				reg = <0xe>;
206				label = "vdd_arm";
207			};
208
209			channel@11 {
210				gw,mode = <1>;
211				reg = <0x11>;
212				label = "vdd_soc";
213			};
214
215			channel@14 {
216				gw,mode = <1>;
217				reg = <0x14>;
218				label = "vdd_3p0";
219			};
220
221			channel@17 {
222				gw,mode = <1>;
223				reg = <0x17>;
224				label = "vdd_1p5";
225			};
226
227			channel@1d {
228				gw,mode = <1>;
229				reg = <0x1d>;
230				label = "vdd_1p8";
231			};
232
233			channel@20 {
234				gw,mode = <1>;
235				reg = <0x20>;
236				label = "vdd_1p0";
237			};
238
239			channel@23 {
240				gw,mode = <1>;
241				reg = <0x23>;
242				label = "vdd_2p5";
243			};
244		};
245
246		fan-controller@a {
247			compatible = "gw,gsc-fan";
248			#address-cells = <1>;
249			#size-cells = <0>;
250			reg = <0x0a>;
251		};
252	};
253
254	gsc_gpio: gpio@23 {
255		compatible = "nxp,pca9555";
256		reg = <0x23>;
257		gpio-controller;
258		#gpio-cells = <2>;
259		interrupt-parent = <&gsc>;
260		interrupts = <4>;
261	};
262
263	eeprom@50 {
264		compatible = "atmel,24c02";
265		reg = <0x50>;
266		pagesize = <16>;
267	};
268
269	eeprom@51 {
270		compatible = "atmel,24c02";
271		reg = <0x51>;
272		pagesize = <16>;
273	};
274
275	eeprom@52 {
276		compatible = "atmel,24c02";
277		reg = <0x52>;
278		pagesize = <16>;
279	};
280
281	eeprom@53 {
282		compatible = "atmel,24c02";
283		reg = <0x53>;
284		pagesize = <16>;
285	};
286
287	rtc@68 {
288		compatible = "dallas,ds1672";
289		reg = <0x68>;
290	};
291};
292
293&i2c2 {
294	clock-frequency = <100000>;
295	pinctrl-names = "default";
296	pinctrl-0 = <&pinctrl_i2c2>;
297	status = "okay";
298};
299
300&i2c3 {
301	clock-frequency = <100000>;
302	pinctrl-names = "default";
303	pinctrl-0 = <&pinctrl_i2c3>;
304	status = "okay";
305
306	accel@19 {
307		pinctrl-names = "default";
308		pinctrl-0 = <&pinctrl_accel>;
309		compatible = "st,lis2de12";
310		reg = <0x19>;
311		st,drdy-int-pin = <1>;
312		interrupt-parent = <&gpio7>;
313		interrupts = <13 0>;
314		interrupt-names = "INT1";
315	};
316};
317
318&pcie {
319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_pcie>;
321	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
322	status = "okay";
323};
324
325&pwm1 {
326	pinctrl-names = "default";
327	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
328	status = "disabled";
329};
330
331&pwm2 {
332	pinctrl-names = "default";
333	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
334	status = "disabled";
335};
336
337&pwm3 {
338	pinctrl-names = "default";
339	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
340	status = "disabled";
341};
342
343&pwm4 {
344	pinctrl-names = "default";
345	pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
346	status = "disabled";
347};
348
349&uart1 {
350	pinctrl-names = "default";
351	pinctrl-0 = <&pinctrl_uart1>;
352	rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
353	status = "okay";
354};
355
356&uart2 {
357	pinctrl-names = "default";
358	pinctrl-0 = <&pinctrl_uart2>;
359	status = "okay";
360};
361
362&uart5 {
363	pinctrl-names = "default";
364	pinctrl-0 = <&pinctrl_uart5>;
365	status = "okay";
366};
367
368&usbotg {
369	vbus-supply = <&reg_usb_vbus>;
370	pinctrl-names = "default";
371	pinctrl-0 = <&pinctrl_usbotg>;
372	disable-over-current;
373	dr_mode = "host";
374	status = "okay";
375};
376
377&usbh1 {
378	vbus-supply = <&reg_usb_vbus>;
379	status = "okay";
380};
381
382&usdhc3 {
383	pinctrl-names = "default", "state_100mhz", "state_200mhz";
384	pinctrl-0 = <&pinctrl_usdhc3>;
385	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
386	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
387	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
388	vmmc-supply = <&reg_3p3v>;
389	no-1-8-v; /* firmware will remove if board revision supports */
390	status = "okay";
391};
392
393&wdog1 {
394	status = "disabled";
395};
396
397&wdog2 {
398	pinctrl-names = "default";
399	pinctrl-0 = <&pinctrl_wdog>;
400	fsl,ext-reset-output;
401	status = "okay";
402};
403
404&iomuxc {
405	pinctrl_accel: accelmuxgrp {
406		fsl,pins = <
407			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b1
408		>;
409	};
410
411	pinctrl_enet: enetgrp {
412		fsl,pins = <
413			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
414			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
415			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
416			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
417			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
418			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
419			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
420			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
421			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
422			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
423			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
424			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
425			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
426			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
427			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
428		>;
429	};
430
431	pinctrl_ecspi2: escpi2grp {
432		fsl,pins = <
433			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK	0x100b1
434			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI	0x100b1
435			MX6QDL_PAD_EIM_OE__ECSPI2_MISO	0x100b1
436			MX6QDL_PAD_EIM_RW__GPIO2_IO26	0x100b1
437		>;
438	};
439
440	pinctrl_flexcan1: flexcan1grp {
441		fsl,pins = <
442			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
443			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b1
444			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x4001b0b0
445		>;
446	};
447
448	pinctrl_gpio_leds: gpioledsgrp {
449		fsl,pins = <
450			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
451			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
452			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
453		>;
454	};
455
456	pinctrl_gpmi_nand: gpminandgrp {
457		fsl,pins = <
458			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
459			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
460			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
461			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
462			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
463			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
464			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
465			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
466			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
467			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
468			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
469			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
470			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
471			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
472			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
473		>;
474	};
475
476	pinctrl_i2c1: i2c1grp {
477		fsl,pins = <
478			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
479			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
480			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x0001b0b0
481		>;
482	};
483
484	pinctrl_i2c2: i2c2grp {
485		fsl,pins = <
486			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
487			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
488		>;
489	};
490
491	pinctrl_i2c3: i2c3grp {
492		fsl,pins = <
493			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
494			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
495		>;
496	};
497
498	pinctrl_pcie: pciegrp {
499		fsl,pins = <
500			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
501			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0
502		>;
503	};
504
505	pinctrl_pps: ppsgrp {
506		fsl,pins = <
507			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x1b0b1
508		>;
509	};
510
511	pinctrl_pwm1: pwm1grp {
512		fsl,pins = <
513			MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
514		>;
515	};
516
517	pinctrl_pwm2: pwm2grp {
518		fsl,pins = <
519			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
520		>;
521	};
522
523	pinctrl_pwm3: pwm3grp {
524		fsl,pins = <
525			MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
526		>;
527	};
528
529	pinctrl_pwm4: pwm4grp {
530		fsl,pins = <
531			MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
532		>;
533	};
534
535	pinctrl_uart1: uart1grp {
536		fsl,pins = <
537			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
538			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
539			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x4001b0b1
540		>;
541	};
542
543	pinctrl_uart2: uart2grp {
544		fsl,pins = <
545			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
546			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
547			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11		0x4001b0b1
548		>;
549	};
550
551	pinctrl_uart5: uart5grp {
552		fsl,pins = <
553			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
554			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
555		>;
556	};
557
558	pinctrl_usbotg: usbotggrp {
559		fsl,pins = <
560			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x13059
561		>;
562	};
563
564	pinctrl_usdhc3: usdhc3grp {
565		fsl,pins = <
566			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
567			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
568			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
569			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
570			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
571			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
572			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
573			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
574		>;
575	};
576
577	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
578		fsl,pins = <
579			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
580			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
581			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
582			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
583			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
584			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
585			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
586			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
587		>;
588	};
589
590	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
591		fsl,pins = <
592			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
593			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
594			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
595			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
596			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
597			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
598			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
599			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
600		>;
601	};
602
603	pinctrl_wdog: wdoggrp {
604		fsl,pins = <
605			MX6QDL_PAD_SD1_DAT3__WDOG2_B		0x1b0b0
606		>;
607	};
608};
609