1/* 2 * Copyright 2017 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49#include <dt-bindings/input/linux-event-codes.h> 50#include <dt-bindings/interrupt-controller/irq.h> 51 52/ { 53 /* these are used by bootloader for disabling nodes */ 54 aliases { 55 led0 = &led0; 56 led1 = &led1; 57 led2 = &led2; 58 usb0 = &usbh1; 59 usb1 = &usbotg; 60 }; 61 62 chosen { 63 stdout-path = &uart2; 64 }; 65 66 backlight { 67 compatible = "pwm-backlight"; 68 pwms = <&pwm4 0 5000000>; 69 brightness-levels = <0 4 8 16 32 64 128 255>; 70 default-brightness-level = <7>; 71 }; 72 73 gpio-keys { 74 compatible = "gpio-keys"; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 user-pb { 79 label = "user_pb"; 80 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 81 linux,code = <BTN_0>; 82 }; 83 84 user-pb1x { 85 label = "user_pb1x"; 86 linux,code = <BTN_1>; 87 interrupt-parent = <&gsc>; 88 interrupts = <0>; 89 }; 90 91 key-erased { 92 label = "key-erased"; 93 linux,code = <BTN_2>; 94 interrupt-parent = <&gsc>; 95 interrupts = <1>; 96 }; 97 98 eeprom-wp { 99 label = "eeprom_wp"; 100 linux,code = <BTN_3>; 101 interrupt-parent = <&gsc>; 102 interrupts = <2>; 103 }; 104 105 tamper { 106 label = "tamper"; 107 linux,code = <BTN_4>; 108 interrupt-parent = <&gsc>; 109 interrupts = <5>; 110 }; 111 112 switch-hold { 113 label = "switch_hold"; 114 linux,code = <BTN_5>; 115 interrupt-parent = <&gsc>; 116 interrupts = <7>; 117 }; 118 }; 119 120 leds { 121 compatible = "gpio-leds"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_gpio_leds>; 124 125 led0: user1 { 126 label = "user1"; 127 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 128 default-state = "on"; 129 linux,default-trigger = "heartbeat"; 130 }; 131 132 led1: user2 { 133 label = "user2"; 134 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 135 default-state = "off"; 136 }; 137 138 led2: user3 { 139 label = "user3"; 140 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 141 default-state = "off"; 142 }; 143 }; 144 145 memory@10000000 { 146 device_type = "memory"; 147 reg = <0x10000000 0x40000000>; 148 }; 149 150 pps { 151 compatible = "pps-gpio"; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_pps>; 154 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 155 }; 156 157 reg_1p0v: regulator-1p0v { 158 compatible = "regulator-fixed"; 159 regulator-name = "1P0V"; 160 regulator-min-microvolt = <1000000>; 161 regulator-max-microvolt = <1000000>; 162 regulator-always-on; 163 }; 164 165 reg_3p3v: regulator-3p3v { 166 compatible = "regulator-fixed"; 167 regulator-name = "3P3V"; 168 regulator-min-microvolt = <3300000>; 169 regulator-max-microvolt = <3300000>; 170 regulator-always-on; 171 }; 172 173 reg_usb_h1_vbus: regulator-usb-h1-vbus { 174 compatible = "regulator-fixed"; 175 regulator-name = "usb_h1_vbus"; 176 regulator-min-microvolt = <5000000>; 177 regulator-max-microvolt = <5000000>; 178 regulator-always-on; 179 }; 180 181 reg_usb_otg_vbus: regulator-usb-otg-vbus { 182 compatible = "regulator-fixed"; 183 regulator-name = "usb_otg_vbus"; 184 regulator-min-microvolt = <5000000>; 185 regulator-max-microvolt = <5000000>; 186 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 187 enable-active-high; 188 }; 189}; 190 191&clks { 192 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 193 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 194 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 195 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 196}; 197 198&fec { 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_enet>; 201 phy-mode = "rgmii-id"; 202 status = "okay"; 203 204 fixed-link { 205 speed = <1000>; 206 full-duplex; 207 }; 208 209 mdio { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 213 switch@0 { 214 compatible = "marvell,mv88e6085"; 215 reg = <0>; 216 217 ports { 218 #address-cells = <1>; 219 #size-cells = <0>; 220 221 port@0 { 222 reg = <0>; 223 label = "lan4"; 224 }; 225 226 port@1 { 227 reg = <1>; 228 label = "lan3"; 229 }; 230 231 port@2 { 232 reg = <2>; 233 label = "lan2"; 234 }; 235 236 port@3 { 237 reg = <3>; 238 label = "lan1"; 239 }; 240 241 port@5 { 242 reg = <5>; 243 label = "cpu"; 244 ethernet = <&fec>; 245 }; 246 }; 247 }; 248 }; 249}; 250 251&i2c1 { 252 clock-frequency = <100000>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_i2c1>; 255 status = "okay"; 256 257 gsc: gsc@20 { 258 compatible = "gw,gsc"; 259 reg = <0x20>; 260 interrupt-parent = <&gpio1>; 261 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 262 interrupt-controller; 263 #interrupt-cells = <1>; 264 #size-cells = <0>; 265 266 adc { 267 compatible = "gw,gsc-adc"; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 271 channel@0 { 272 gw,mode = <0>; 273 reg = <0x00>; 274 label = "temp"; 275 }; 276 277 channel@2 { 278 gw,mode = <1>; 279 reg = <0x02>; 280 label = "vdd_vin"; 281 }; 282 283 channel@5 { 284 gw,mode = <1>; 285 reg = <0x05>; 286 label = "vdd_3p3"; 287 }; 288 289 channel@8 { 290 gw,mode = <1>; 291 reg = <0x08>; 292 label = "vdd_bat"; 293 }; 294 295 channel@b { 296 gw,mode = <1>; 297 reg = <0x0b>; 298 label = "vdd_5p0"; 299 }; 300 301 channel@e { 302 gw,mode = <1>; 303 reg = <0xe>; 304 label = "vdd_arm"; 305 }; 306 307 channel@11 { 308 gw,mode = <1>; 309 reg = <0x11>; 310 label = "vdd_soc"; 311 }; 312 313 channel@14 { 314 gw,mode = <1>; 315 reg = <0x14>; 316 label = "vdd_3p0"; 317 }; 318 319 channel@17 { 320 gw,mode = <1>; 321 reg = <0x17>; 322 label = "vdd_1p5"; 323 }; 324 325 channel@1d { 326 gw,mode = <1>; 327 reg = <0x1d>; 328 label = "vdd_1p8"; 329 }; 330 331 channel@20 { 332 gw,mode = <1>; 333 reg = <0x20>; 334 label = "vdd_an1"; 335 }; 336 337 channel@23 { 338 gw,mode = <1>; 339 reg = <0x23>; 340 label = "vdd_2p5"; 341 }; 342 }; 343 }; 344 345 gsc_gpio: gpio@23 { 346 compatible = "nxp,pca9555"; 347 reg = <0x23>; 348 gpio-controller; 349 #gpio-cells = <2>; 350 interrupt-parent = <&gsc>; 351 interrupts = <4>; 352 }; 353 354 eeprom1: eeprom@50 { 355 compatible = "atmel,24c02"; 356 reg = <0x50>; 357 pagesize = <16>; 358 }; 359 360 eeprom2: eeprom@51 { 361 compatible = "atmel,24c02"; 362 reg = <0x51>; 363 pagesize = <16>; 364 }; 365 366 eeprom3: eeprom@52 { 367 compatible = "atmel,24c02"; 368 reg = <0x52>; 369 pagesize = <16>; 370 }; 371 372 eeprom4: eeprom@53 { 373 compatible = "atmel,24c02"; 374 reg = <0x53>; 375 pagesize = <16>; 376 }; 377 378 dts1672: rtc@68 { 379 compatible = "dallas,ds1672"; 380 reg = <0x68>; 381 }; 382}; 383 384&i2c2 { 385 clock-frequency = <100000>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_i2c2>; 388 status = "okay"; 389 390 magn@1c { 391 compatible = "st,lsm9ds1-magn"; 392 reg = <0x1c>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_mag>; 395 interrupt-parent = <&gpio5>; 396 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 397 }; 398 399 ltc3676: pmic@3c { 400 compatible = "lltc,ltc3676"; 401 reg = <0x3c>; 402 interrupt-parent = <&gpio1>; 403 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 404 405 regulators { 406 /* VDD_SOC (1+R1/R2 = 1.635) */ 407 reg_vdd_soc: sw1 { 408 regulator-name = "vddsoc"; 409 regulator-min-microvolt = <674400>; 410 regulator-max-microvolt = <1308000>; 411 lltc,fb-voltage-divider = <127000 200000>; 412 regulator-ramp-delay = <7000>; 413 regulator-boot-on; 414 regulator-always-on; 415 }; 416 417 /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ 418 reg_1p8v: sw2 { 419 regulator-name = "vdd1p8"; 420 regulator-min-microvolt = <1033310>; 421 regulator-max-microvolt = <2004000>; 422 lltc,fb-voltage-divider = <301000 200000>; 423 regulator-ramp-delay = <7000>; 424 regulator-boot-on; 425 regulator-always-on; 426 }; 427 428 /* VDD_ARM (1+R1/R2 = 1.635) */ 429 reg_vdd_arm: sw3 { 430 regulator-name = "vddarm"; 431 regulator-min-microvolt = <674400>; 432 regulator-max-microvolt = <1308000>; 433 lltc,fb-voltage-divider = <127000 200000>; 434 regulator-ramp-delay = <7000>; 435 regulator-boot-on; 436 regulator-always-on; 437 }; 438 439 /* VDD_DDR (1+R1/R2 = 2.105) */ 440 reg_vdd_ddr: sw4 { 441 regulator-name = "vddddr"; 442 regulator-min-microvolt = <868310>; 443 regulator-max-microvolt = <1684000>; 444 lltc,fb-voltage-divider = <221000 200000>; 445 regulator-ramp-delay = <7000>; 446 regulator-boot-on; 447 regulator-always-on; 448 }; 449 450 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 451 reg_2p5v: ldo2 { 452 regulator-name = "vdd2p5"; 453 regulator-min-microvolt = <2490375>; 454 regulator-max-microvolt = <2490375>; 455 lltc,fb-voltage-divider = <487000 200000>; 456 regulator-boot-on; 457 regulator-always-on; 458 }; 459 460 /* VDD_HIGH (1+R1/R2 = 4.17) */ 461 reg_3p0v: ldo4 { 462 regulator-name = "vdd3p0"; 463 regulator-min-microvolt = <3023250>; 464 regulator-max-microvolt = <3023250>; 465 lltc,fb-voltage-divider = <634000 200000>; 466 regulator-boot-on; 467 regulator-always-on; 468 }; 469 }; 470 }; 471 472 imu@6a { 473 compatible = "st,lsm9ds1-imu"; 474 reg = <0x6a>; 475 st,drdy-int-pin = <1>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pinctrl_imu>; 478 interrupt-parent = <&gpio4>; 479 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 480 }; 481}; 482 483&i2c3 { 484 clock-frequency = <100000>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pinctrl_i2c3>; 487 status = "okay"; 488 489 egalax_ts: touchscreen@4 { 490 compatible = "eeti,egalax_ts"; 491 reg = <0x04>; 492 interrupt-parent = <&gpio1>; 493 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 494 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 495 }; 496}; 497 498&ldb { 499 status = "okay"; 500 501 lvds-channel@0 { 502 fsl,data-mapping = "spwg"; 503 fsl,data-width = <18>; 504 status = "okay"; 505 506 display-timings { 507 native-mode = <&timing0>; 508 timing0: hsd100pxn1 { 509 clock-frequency = <65000000>; 510 hactive = <1024>; 511 vactive = <768>; 512 hback-porch = <220>; 513 hfront-porch = <40>; 514 vback-porch = <21>; 515 vfront-porch = <7>; 516 hsync-len = <60>; 517 vsync-len = <10>; 518 }; 519 }; 520 }; 521}; 522 523&pcie { 524 pinctrl-names = "default"; 525 pinctrl-0 = <&pinctrl_pcie>; 526 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 527 status = "okay"; 528}; 529 530&pwm2 { 531 pinctrl-names = "default"; 532 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 533 status = "disabled"; 534}; 535 536&pwm3 { 537 pinctrl-names = "default"; 538 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 539 status = "disabled"; 540}; 541 542&pwm4 { 543 #pwm-cells = <2>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pinctrl_pwm4>; 546 status = "okay"; 547}; 548 549&uart1 { 550 pinctrl-names = "default"; 551 pinctrl-0 = <&pinctrl_uart1>; 552 status = "okay"; 553}; 554 555&uart2 { 556 pinctrl-names = "default"; 557 pinctrl-0 = <&pinctrl_uart2>; 558 status = "okay"; 559}; 560 561&uart3 { 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_uart3>; 564 uart-has-rtscts; 565 status = "okay"; 566}; 567 568&uart4 { 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_uart4>; 571 uart-has-rtscts; 572 status = "okay"; 573}; 574 575&uart5 { 576 pinctrl-names = "default"; 577 pinctrl-0 = <&pinctrl_uart5>; 578 status = "okay"; 579}; 580 581&usbotg { 582 vbus-supply = <®_usb_otg_vbus>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&pinctrl_usbotg>; 585 disable-over-current; 586 status = "okay"; 587}; 588 589&usbh1 { 590 vbus-supply = <®_usb_h1_vbus>; 591 status = "okay"; 592}; 593 594&usdhc3 { 595 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 596 pinctrl-0 = <&pinctrl_usdhc3>; 597 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 598 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 599 non-removable; 600 vmmc-supply = <®_3p3v>; 601 keep-power-in-suspend; 602 status = "okay"; 603}; 604 605&wdog1 { 606 pinctrl-names = "default"; 607 pinctrl-0 = <&pinctrl_wdog>; 608 fsl,ext-reset-output; 609}; 610 611&iomuxc { 612 pinctrl_enet: enetgrp { 613 fsl,pins = < 614 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 615 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 616 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 617 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 618 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 619 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 620 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 621 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 622 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 623 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 624 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 625 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 626 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 627 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 628 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 629 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 630 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 631 >; 632 }; 633 634 pinctrl_gpio_leds: gpioledsgrp { 635 fsl,pins = < 636 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 637 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 638 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 639 >; 640 }; 641 642 pinctrl_i2c1: i2c1grp { 643 fsl,pins = < 644 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 645 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 646 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 647 >; 648 }; 649 650 pinctrl_i2c2: i2c2grp { 651 fsl,pins = < 652 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 653 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 654 >; 655 }; 656 657 pinctrl_i2c3: i2c3grp { 658 fsl,pins = < 659 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 660 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 661 >; 662 }; 663 664 pinctrl_imu: imugrp { 665 fsl,pins = < 666 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 667 >; 668 }; 669 670 pinctrl_mag: maggrp { 671 fsl,pins = < 672 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 673 >; 674 }; 675 676 pinctrl_pcie: pciegrp { 677 fsl,pins = < 678 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ 679 >; 680 }; 681 682 pinctrl_pmic: pmicgrp { 683 fsl,pins = < 684 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ 685 >; 686 }; 687 688 pinctrl_pps: ppsgrp { 689 fsl,pins = < 690 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 691 >; 692 }; 693 694 pinctrl_pwm2: pwm2grp { 695 fsl,pins = < 696 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 697 >; 698 }; 699 700 pinctrl_pwm3: pwm3grp { 701 fsl,pins = < 702 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 703 >; 704 }; 705 706 pinctrl_pwm4: pwm4grp { 707 fsl,pins = < 708 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 709 >; 710 }; 711 712 pinctrl_uart1: uart1grp { 713 fsl,pins = < 714 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 715 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 716 >; 717 }; 718 719 pinctrl_uart2: uart2grp { 720 fsl,pins = < 721 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 722 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 723 >; 724 }; 725 726 pinctrl_uart3: uart3grp { 727 fsl,pins = < 728 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 729 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 730 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 731 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 732 >; 733 }; 734 735 pinctrl_uart4: uart4grp { 736 fsl,pins = < 737 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 738 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 739 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 740 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 741 >; 742 }; 743 744 pinctrl_uart5: uart5grp { 745 fsl,pins = < 746 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 747 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 748 >; 749 }; 750 751 pinctrl_usbotg: usbotggrp { 752 fsl,pins = < 753 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 754 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 755 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 756 >; 757 }; 758 759 pinctrl_usdhc3: usdhc3grp { 760 fsl,pins = < 761 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 762 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 763 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 764 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 765 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 766 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 767 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 768 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 769 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 770 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 771 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 772 >; 773 }; 774 775 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 776 fsl,pins = < 777 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 778 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 779 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 780 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 781 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 782 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 783 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 784 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 785 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 786 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 787 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 788 >; 789 }; 790 791 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 792 fsl,pins = < 793 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 794 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 795 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 796 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 797 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 798 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 799 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 800 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 801 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 802 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 803 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 804 >; 805 }; 806 807 pinctrl_wdog: wdoggrp { 808 fsl,pins = < 809 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 810 >; 811 }; 812}; 813
