1/* 2 * Copyright 2017 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49#include <dt-bindings/input/linux-event-codes.h> 50#include <dt-bindings/interrupt-controller/irq.h> 51 52/ { 53 chosen { 54 stdout-path = &uart2; 55 }; 56 57 backlight { 58 compatible = "pwm-backlight"; 59 pwms = <&pwm1 0 5000000>; 60 brightness-levels = < 61 0 1 2 3 4 5 6 7 8 9 62 10 11 12 13 14 15 16 17 18 19 63 20 21 22 23 24 25 26 27 28 29 64 30 31 32 33 34 35 36 37 38 39 65 40 41 42 43 44 45 46 47 48 49 66 50 51 52 53 54 55 56 57 58 59 67 60 61 62 63 64 65 66 67 68 69 68 70 71 72 73 74 75 76 77 78 79 69 80 81 82 83 84 85 86 87 88 89 70 90 91 92 93 94 95 96 97 98 99 71 100 72 >; 73 default-brightness-level = <100>; 74 }; 75 76 gpio-keys { 77 compatible = "gpio-keys"; 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 user-pb { 82 label = "user_pb"; 83 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 84 linux,code = <BTN_0>; 85 }; 86 87 user-pb1x { 88 label = "user_pb1x"; 89 linux,code = <BTN_1>; 90 interrupt-parent = <&gsc>; 91 interrupts = <0>; 92 }; 93 94 key-erased { 95 label = "key-erased"; 96 linux,code = <BTN_2>; 97 interrupt-parent = <&gsc>; 98 interrupts = <1>; 99 }; 100 101 eeprom-wp { 102 label = "eeprom_wp"; 103 linux,code = <BTN_3>; 104 interrupt-parent = <&gsc>; 105 interrupts = <2>; 106 }; 107 108 tamper { 109 label = "tamper"; 110 linux,code = <BTN_4>; 111 interrupt-parent = <&gsc>; 112 interrupts = <5>; 113 }; 114 115 switch-hold { 116 label = "switch_hold"; 117 linux,code = <BTN_5>; 118 interrupt-parent = <&gsc>; 119 interrupts = <7>; 120 }; 121 }; 122 123 leds { 124 compatible = "gpio-leds"; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_gpio_leds>; 127 128 led0: user1 { 129 label = "user1"; 130 gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 131 default-state = "off"; 132 }; 133 }; 134 135 memory@10000000 { 136 device_type = "memory"; 137 reg = <0x10000000 0x40000000>; 138 }; 139 140 reg_5p0v: regulator-5p0v { 141 compatible = "regulator-fixed"; 142 regulator-name = "5P0V"; 143 regulator-min-microvolt = <5000000>; 144 regulator-max-microvolt = <5000000>; 145 regulator-always-on; 146 }; 147 148 reg_3p3v: regulator-3p3v { 149 compatible = "regulator-fixed"; 150 regulator-name = "3P3V"; 151 regulator-min-microvolt = <3300000>; 152 regulator-max-microvolt = <3300000>; 153 regulator-always-on; 154 }; 155 156 reg_2p5v: regulator-2p5v { 157 compatible = "regulator-fixed"; 158 regulator-name = "2P5V"; 159 regulator-min-microvolt = <2500000>; 160 regulator-max-microvolt = <2500000>; 161 regulator-always-on; 162 }; 163 164 reg_usb_h1_vbus: regulator-usb-h1-vbus { 165 compatible = "regulator-fixed"; 166 regulator-name = "usb_h1_vbus"; 167 regulator-min-microvolt = <5000000>; 168 regulator-max-microvolt = <5000000>; 169 gpio = <&gpio3 30 0>; 170 enable-active-high; 171 }; 172 173 reg_usb_otg_vbus: regulator-usb-otg-vbus { 174 compatible = "regulator-fixed"; 175 regulator-name = "usb_otg_vbus"; 176 regulator-min-microvolt = <5000000>; 177 regulator-max-microvolt = <5000000>; 178 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; 179 enable-active-high; 180 }; 181 182 reg_12p0: regulator-12p0v { 183 compatible = "regulator-fixed"; 184 regulator-name = "12P0V"; 185 regulator-min-microvolt = <12000000>; 186 regulator-max-microvolt = <12000000>; 187 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 188 enable-active-high; 189 }; 190 191 sound { 192 compatible = "fsl,imx-audio-tlv320"; 193 model = "imx-tlv320"; 194 ssi-controller = <&ssi1>; 195 audio-codec = <&tlv320aic3105>; 196 /* routing of sink, source */ 197 audio-routing = 198 /* TLV320 LINE1L pin <-> Mic Jack connector */ 199 "LINE1L", "Mic Jack", 200 /* board Headphone Jack <-> HPOUT */ 201 "Headphone Jack", "HPLOUT", 202 "Headphone Jack", "HPROUT", 203 "Mic Jack", "Mic Bias"; 204 mux-int-port = <1>; 205 mux-ext-port = <6>; 206 }; 207}; 208 209&audmux { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_audmux>; 212 status = "okay"; 213}; 214 215&clks { 216 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 217 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 218 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 219 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 220}; 221 222&fec { 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_enet>; 225 phy-mode = "rgmii-id"; 226 status = "okay"; 227}; 228 229&i2c1 { 230 clock-frequency = <100000>; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_i2c1>; 233 status = "okay"; 234 235 gsc: gsc@20 { 236 compatible = "gw,gsc"; 237 reg = <0x20>; 238 interrupt-parent = <&gpio1>; 239 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 240 interrupt-controller; 241 #interrupt-cells = <1>; 242 #size-cells = <0>; 243 244 adc { 245 compatible = "gw,gsc-adc"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 249 channel@0 { 250 gw,mode = <0>; 251 reg = <0x00>; 252 label = "temp"; 253 }; 254 255 channel@2 { 256 gw,mode = <1>; 257 reg = <0x02>; 258 label = "vdd_vin"; 259 }; 260 261 channel@5 { 262 gw,mode = <1>; 263 reg = <0x05>; 264 label = "vdd_3p3"; 265 }; 266 267 channel@8 { 268 gw,mode = <1>; 269 reg = <0x08>; 270 label = "vdd_bat"; 271 }; 272 273 channel@b { 274 gw,mode = <1>; 275 reg = <0x0b>; 276 label = "vdd_5p0"; 277 }; 278 279 channel@e { 280 gw,mode = <1>; 281 reg = <0xe>; 282 label = "vdd_arm"; 283 }; 284 285 channel@11 { 286 gw,mode = <1>; 287 reg = <0x11>; 288 label = "vdd_soc"; 289 }; 290 291 channel@14 { 292 gw,mode = <1>; 293 reg = <0x14>; 294 label = "vdd_3p0"; 295 }; 296 297 channel@17 { 298 gw,mode = <1>; 299 reg = <0x17>; 300 label = "vdd_1p5"; 301 }; 302 303 channel@1d { 304 gw,mode = <1>; 305 reg = <0x1d>; 306 label = "vdd_1p8"; 307 }; 308 309 channel@20 { 310 gw,mode = <1>; 311 reg = <0x20>; 312 label = "vdd_an1"; 313 }; 314 315 channel@23 { 316 gw,mode = <1>; 317 reg = <0x23>; 318 label = "vdd_2p5"; 319 }; 320 }; 321 }; 322 323 gsc_gpio: gpio@23 { 324 compatible = "nxp,pca9555"; 325 reg = <0x23>; 326 gpio-controller; 327 #gpio-cells = <2>; 328 interrupt-parent = <&gsc>; 329 interrupts = <4>; 330 }; 331 332 eeprom1: eeprom@50 { 333 compatible = "atmel,24c02"; 334 reg = <0x50>; 335 pagesize = <16>; 336 }; 337 338 eeprom2: eeprom@51 { 339 compatible = "atmel,24c02"; 340 reg = <0x51>; 341 pagesize = <16>; 342 }; 343 344 eeprom3: eeprom@52 { 345 compatible = "atmel,24c02"; 346 reg = <0x52>; 347 pagesize = <16>; 348 }; 349 350 eeprom4: eeprom@53 { 351 compatible = "atmel,24c02"; 352 reg = <0x53>; 353 pagesize = <16>; 354 }; 355 356 dts1672: rtc@68 { 357 compatible = "dallas,ds1672"; 358 reg = <0x68>; 359 }; 360}; 361 362&i2c2 { 363 clock-frequency = <400000>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pinctrl_i2c2>; 366 status = "okay"; 367 368 ltc3676: pmic@3c { 369 compatible = "lltc,ltc3676"; 370 reg = <0x3c>; 371 interrupt-parent = <&gpio1>; 372 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 373 374 regulators { 375 /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */ 376 reg_1p8v: sw1 { 377 regulator-name = "vdd1p8"; 378 regulator-min-microvolt = <1033310>; 379 regulator-max-microvolt = <2004000>; 380 lltc,fb-voltage-divider = <301000 200000>; 381 regulator-ramp-delay = <7000>; 382 regulator-boot-on; 383 regulator-always-on; 384 }; 385 386 /* VDD_DDR (1+R1/R2 = 2.105) */ 387 reg_vdd_ddr: sw2 { 388 regulator-name = "vddddr"; 389 regulator-min-microvolt = <868310>; 390 regulator-max-microvolt = <1684000>; 391 lltc,fb-voltage-divider = <221000 200000>; 392 regulator-ramp-delay = <7000>; 393 regulator-boot-on; 394 regulator-always-on; 395 }; 396 397 /* VDD_ARM (1+R1/R2 = 1.635) */ 398 reg_vdd_arm: sw3 { 399 regulator-name = "vddarm"; 400 regulator-min-microvolt = <674400>; 401 regulator-max-microvolt = <1308000>; 402 lltc,fb-voltage-divider = <127000 200000>; 403 regulator-ramp-delay = <7000>; 404 regulator-boot-on; 405 regulator-always-on; 406 linux,phandle = <®_vdd_arm>; 407 }; 408 409 /* VDD_SOC (1+R1/R2 = 1.635) */ 410 reg_vdd_soc: sw4 { 411 regulator-name = "vddsoc"; 412 regulator-min-microvolt = <674400>; 413 regulator-max-microvolt = <1308000>; 414 lltc,fb-voltage-divider = <127000 200000>; 415 regulator-ramp-delay = <7000>; 416 regulator-boot-on; 417 regulator-always-on; 418 linux,phandle = <®_vdd_soc>; 419 }; 420 421 /* VDD_1P0 (1+R1/R2 = 1.38): */ 422 reg_1p0v: ldo2 { 423 regulator-name = "vdd1p0"; 424 regulator-min-microvolt = <1002777>; 425 regulator-max-microvolt = <1002777>; 426 lltc,fb-voltage-divider = <100000 261000>; 427 regulator-boot-on; 428 regulator-always-on; 429 }; 430 431 /* VDD_HIGH (1+R1/R2 = 4.17) */ 432 reg_3p0v: ldo4 { 433 regulator-name = "vdd3p0"; 434 regulator-min-microvolt = <3023250>; 435 regulator-max-microvolt = <3023250>; 436 lltc,fb-voltage-divider = <634000 200000>; 437 regulator-boot-on; 438 regulator-always-on; 439 }; 440 }; 441 }; 442}; 443 444&i2c3 { 445 clock-frequency = <400000>; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&pinctrl_i2c3>; 448 status = "okay"; 449 450 tlv320aic3105: codec@18 { 451 compatible = "ti,tlv320aic3x"; 452 reg = <0x18>; 453 reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; 454 clocks = <&clks IMX6QDL_CLK_CKO>; 455 ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ 456 /* Regulators */ 457 DRVDD-supply = <®_3p3v>; 458 AVDD-supply = <®_3p3v>; 459 IOVDD-supply = <®_3p3v>; 460 DVDD-supply = <®_1p8v>; 461 }; 462 463 accelerometer@1d { 464 compatible = "fsl,mma8451"; 465 reg = <0x1d>; 466 interrupt-parent = <&gpio7>; 467 interrupts = <11 IRQ_TYPE_EDGE_RISING>; 468 interrupt-names = "INT2"; 469 }; 470 471 /* headphone detect */ 472 ts3a227e@3b { 473 compatible = "ti,ts3a227e"; 474 reg = <0x3b>; 475 interrupt-parent = <&gpio5>; 476 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 477 ti,micbias = <4>; /* 2.5V micbias */ 478 }; 479}; 480 481&ldb { 482 status = "okay"; 483 484 lvds-channel@0 { 485 fsl,data-mapping = "spwg"; 486 fsl,data-width = <18>; 487 status = "okay"; 488 489 display-timings { 490 native-mode = <&timing0>; 491 timing0: g101evn010 { 492 clock-frequency = <68930000>; 493 hactive = <1280>; 494 vactive = <800>; 495 hback-porch = <220>; 496 hfront-porch = <40>; 497 vback-porch = <21>; 498 vfront-porch = <7>; 499 hsync-len = <60>; 500 vsync-len = <10>; 501 }; 502 }; 503 }; 504}; 505 506&pwm1 { 507 #pwm-cells = <2>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&pinctrl_pwm1>; 510 status = "okay"; 511}; 512 513&ssi1 { 514 status = "okay"; 515}; 516 517&uart1 { 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pinctrl_uart1>; 520 status = "okay"; 521}; 522 523&uart2 { 524 pinctrl-names = "default"; 525 pinctrl-0 = <&pinctrl_uart2>; 526 status = "okay"; 527}; 528 529&usbotg { 530 vbus-supply = <®_usb_otg_vbus>; 531 pinctrl-names = "default"; 532 pinctrl-0 = <&pinctrl_usbotg>; 533 disable-over-current; 534 status = "okay"; 535}; 536 537&usbh1 { 538 vbus-supply = <®_usb_h1_vbus>; 539 status = "okay"; 540}; 541 542&usdhc1 { 543 pinctrl-names = "default"; 544 pinctrl-0 = <&pinctrl_usdhc1_200mhz>; 545 vmmc-supply = <®_3p3v>; 546 non-removable; 547 bus-width = <4>; 548 status = "okay"; 549}; 550 551&usdhc2 { 552 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 553 pinctrl-0 = <&pinctrl_usdhc2>; 554 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 555 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 556 cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 557 vmmc-supply = <®_3p3v>; 558 max-frequency = <100000000>; 559 status = "okay"; 560}; 561 562&usdhc3 { 563 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 564 pinctrl-0 = <&pinctrl_usdhc3>; 565 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 566 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 567 non-removable; 568 vmmc-supply = <®_3p3v>; 569 keep-power-in-suspend; 570 status = "okay"; 571}; 572 573&wdog1 { 574 pinctrl-names = "default"; 575 pinctrl-0 = <&pinctrl_wdog>; 576 fsl,ext-reset-output; 577}; 578 579&iomuxc { 580 pinctrl_audmux: audmuxgrp { 581 fsl,pins = < 582 MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0 583 MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0 584 MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0 585 MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0 586 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */ 587 >; 588 }; 589 590 pinctrl_enet: enetgrp { 591 fsl,pins = < 592 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 593 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 594 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 595 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 596 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 597 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 598 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 599 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 600 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 601 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 602 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 603 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 604 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 605 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 606 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 607 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 608 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */ 609 >; 610 }; 611 612 pinctrl_gpio_leds: gpioledsgrp { 613 fsl,pins = < 614 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 615 >; 616 }; 617 618 pinctrl_i2c1: i2c1grp { 619 fsl,pins = < 620 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 621 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 622 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 623 >; 624 }; 625 626 pinctrl_i2c2: i2c2grp { 627 fsl,pins = < 628 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 629 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 630 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 631 >; 632 }; 633 634 pinctrl_i2c3: i2c3grp { 635 fsl,pins = < 636 /* I2C3 */ 637 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 638 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 639 640 /* Headphone Detect */ 641 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */ 642 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */ 643 644 /* Codec */ 645 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */ 646 647 /* Touch Controller */ 648 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */ 649 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */ 650 651 /* Stow Sensor */ 652 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */ 653 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */ 654 >; 655 }; 656 657 pinctrl_pwm1: pwm1grp { 658 fsl,pins = < 659 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 660 >; 661 }; 662 663 pinctrl_uart1: uart1grp { 664 fsl,pins = < 665 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 666 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 667 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */ 668 >; 669 }; 670 671 pinctrl_uart2: uart2grp { 672 fsl,pins = < 673 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 674 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 675 >; 676 }; 677 678 pinctrl_usbotg: usbotggrp { 679 fsl,pins = < 680 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 681 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */ 682 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 683 >; 684 }; 685 686 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 687 fsl,pins = < 688 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */ 689 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */ 690 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */ 691 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */ 692 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */ 693 694 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 695 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9 696 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 697 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 698 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 699 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 700 >; 701 }; 702 703 pinctrl_usdhc2: usdhc2grp { 704 fsl,pins = < 705 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 706 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 707 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 708 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 709 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 710 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 711 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */ 712 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059 713 >; 714 }; 715 716 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 717 fsl,pins = < 718 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 719 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 720 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 721 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 722 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 723 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 724 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */ 725 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9 726 >; 727 }; 728 729 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 730 fsl,pins = < 731 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 732 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 733 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 734 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 735 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 736 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 737 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */ 738 MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9 739 >; 740 }; 741 742 pinctrl_usdhc3: usdhc3grp { 743 fsl,pins = < 744 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 745 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 746 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 747 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 748 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 749 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 750 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 751 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 752 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 753 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 754 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 755 >; 756 }; 757 758 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 759 fsl,pins = < 760 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 761 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 762 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 763 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 764 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 765 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 766 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 767 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 768 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 769 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 770 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 771 >; 772 }; 773 774 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 775 fsl,pins = < 776 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 777 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 778 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 779 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 780 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 781 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 782 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 783 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 784 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 785 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 786 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 787 >; 788 }; 789 790 pinctrl_wdog: wdoggrp { 791 fsl,pins = < 792 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 793 >; 794 }; 795}; 796
