1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's Exynos3250 SoC device tree source 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 9 * based board files can include this file and provide values for board specfic 10 * bindings. 11 * 12 * Note: This file does not include device nodes for all the controllers in 13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional 14 * nodes can be added to this file. 15 */ 16 17#include "exynos4-cpu-thermal.dtsi" 18#include <dt-bindings/clock/exynos3250.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/interrupt-controller/irq.h> 21 22/ { 23 compatible = "samsung,exynos3250"; 24 interrupt-parent = <&gic>; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 28 aliases { 29 pinctrl0 = &pinctrl_0; 30 pinctrl1 = &pinctrl_1; 31 mshc0 = &mshc_0; 32 mshc1 = &mshc_1; 33 mshc2 = &mshc_2; 34 spi0 = &spi_0; 35 spi1 = &spi_1; 36 i2c0 = &i2c_0; 37 i2c1 = &i2c_1; 38 i2c2 = &i2c_2; 39 i2c3 = &i2c_3; 40 i2c4 = &i2c_4; 41 i2c5 = &i2c_5; 42 i2c6 = &i2c_6; 43 i2c7 = &i2c_7; 44 serial0 = &serial_0; 45 serial1 = &serial_1; 46 serial2 = &serial_2; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0>; 57 clock-frequency = <1000000000>; 58 clocks = <&cmu CLK_ARM_CLK>; 59 clock-names = "cpu"; 60 #cooling-cells = <2>; 61 62 operating-points = < 63 1000000 1150000 64 900000 1112500 65 800000 1075000 66 700000 1037500 67 600000 1000000 68 500000 962500 69 400000 925000 70 300000 887500 71 200000 850000 72 100000 850000 73 >; 74 }; 75 76 cpu1: cpu@1 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a7"; 79 reg = <1>; 80 clock-frequency = <1000000000>; 81 clocks = <&cmu CLK_ARM_CLK>; 82 clock-names = "cpu"; 83 #cooling-cells = <2>; 84 85 operating-points = < 86 1000000 1150000 87 900000 1112500 88 800000 1075000 89 700000 1037500 90 600000 1000000 91 500000 962500 92 400000 925000 93 300000 887500 94 200000 850000 95 100000 850000 96 >; 97 }; 98 }; 99 100 xusbxti: clock-0 { 101 compatible = "fixed-clock"; 102 clock-frequency = <0>; 103 #clock-cells = <0>; 104 clock-output-names = "xusbxti"; 105 }; 106 107 xxti: clock-1 { 108 compatible = "fixed-clock"; 109 clock-frequency = <0>; 110 #clock-cells = <0>; 111 clock-output-names = "xxti"; 112 }; 113 114 xtcxo: clock-2 { 115 compatible = "fixed-clock"; 116 clock-frequency = <0>; 117 #clock-cells = <0>; 118 clock-output-names = "xtcxo"; 119 }; 120 121 pmu { 122 compatible = "arm,cortex-a7-pmu"; 123 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 125 }; 126 127 soc: soc { 128 compatible = "simple-bus"; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 133 sram@2020000 { 134 compatible = "mmio-sram"; 135 reg = <0x02020000 0x40000>; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 ranges = <0 0x02020000 0x40000>; 139 140 smp-sram@0 { 141 compatible = "samsung,exynos4210-sysram"; 142 reg = <0x0 0x1000>; 143 }; 144 145 smp-sram@3f000 { 146 compatible = "samsung,exynos4210-sysram-ns"; 147 reg = <0x3f000 0x1000>; 148 }; 149 }; 150 151 chipid@10000000 { 152 compatible = "samsung,exynos4210-chipid"; 153 reg = <0x10000000 0x100>; 154 }; 155 156 sys_reg: syscon@10010000 { 157 compatible = "samsung,exynos3-sysreg", "syscon"; 158 reg = <0x10010000 0x400>; 159 }; 160 161 pmu_system_controller: system-controller@10020000 { 162 compatible = "samsung,exynos3250-pmu", "syscon"; 163 reg = <0x10020000 0x4000>; 164 interrupt-controller; 165 #interrupt-cells = <3>; 166 interrupt-parent = <&gic>; 167 clock-names = "clkout8"; 168 clocks = <&cmu CLK_FIN_PLL>; 169 #clock-cells = <1>; 170 }; 171 172 mipi_phy: video-phy { 173 compatible = "samsung,s5pv210-mipi-video-phy"; 174 #phy-cells = <1>; 175 syscon = <&pmu_system_controller>; 176 }; 177 178 pd_cam: power-domain@10023c00 { 179 compatible = "samsung,exynos4210-pd"; 180 reg = <0x10023C00 0x20>; 181 #power-domain-cells = <0>; 182 label = "CAM"; 183 }; 184 185 pd_mfc: power-domain@10023c40 { 186 compatible = "samsung,exynos4210-pd"; 187 reg = <0x10023C40 0x20>; 188 #power-domain-cells = <0>; 189 label = "MFC"; 190 }; 191 192 pd_g3d: power-domain@10023c60 { 193 compatible = "samsung,exynos4210-pd"; 194 reg = <0x10023C60 0x20>; 195 #power-domain-cells = <0>; 196 label = "G3D"; 197 }; 198 199 pd_lcd0: power-domain@10023c80 { 200 compatible = "samsung,exynos4210-pd"; 201 reg = <0x10023C80 0x20>; 202 #power-domain-cells = <0>; 203 label = "LCD0"; 204 }; 205 206 pd_isp: power-domain@10023ca0 { 207 compatible = "samsung,exynos4210-pd"; 208 reg = <0x10023CA0 0x20>; 209 #power-domain-cells = <0>; 210 label = "ISP"; 211 }; 212 213 cmu: clock-controller@10030000 { 214 compatible = "samsung,exynos3250-cmu"; 215 reg = <0x10030000 0x20000>; 216 #clock-cells = <1>; 217 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>, 218 <&cmu CLK_MOUT_ACLK_266_SUB>; 219 assigned-clock-parents = <&cmu CLK_FIN_PLL>, 220 <&cmu CLK_FIN_PLL>; 221 }; 222 223 cmu_dmc: clock-controller@105c0000 { 224 compatible = "samsung,exynos3250-cmu-dmc"; 225 reg = <0x105C0000 0x2000>; 226 #clock-cells = <1>; 227 }; 228 229 rtc: rtc@10070000 { 230 compatible = "samsung,s3c6410-rtc"; 231 reg = <0x10070000 0x100>; 232 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 234 interrupt-parent = <&pmu_system_controller>; 235 status = "disabled"; 236 }; 237 238 tmu: tmu@100c0000 { 239 compatible = "samsung,exynos3250-tmu"; 240 reg = <0x100C0000 0x100>; 241 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&cmu CLK_TMU_APBIF>; 243 clock-names = "tmu_apbif"; 244 #thermal-sensor-cells = <0>; 245 status = "disabled"; 246 }; 247 248 gic: interrupt-controller@10481000 { 249 compatible = "arm,cortex-a15-gic"; 250 #interrupt-cells = <3>; 251 interrupt-controller; 252 reg = <0x10481000 0x1000>, 253 <0x10482000 0x2000>, 254 <0x10484000 0x2000>, 255 <0x10486000 0x2000>; 256 interrupts = <GIC_PPI 9 257 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 258 }; 259 260 timer@10050000 { 261 compatible = "samsung,exynos4210-mct"; 262 reg = <0x10050000 0x800>; 263 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; 272 clock-names = "fin_pll", "mct"; 273 }; 274 275 pinctrl_1: pinctrl@11000000 { 276 compatible = "samsung,exynos3250-pinctrl"; 277 reg = <0x11000000 0x1000>; 278 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 279 280 wakeup-interrupt-controller { 281 compatible = "samsung,exynos4210-wakeup-eint"; 282 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 283 }; 284 }; 285 286 pinctrl_0: pinctrl@11400000 { 287 compatible = "samsung,exynos3250-pinctrl"; 288 reg = <0x11400000 0x1000>; 289 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 290 }; 291 292 jpeg: codec@11830000 { 293 compatible = "samsung,exynos3250-jpeg"; 294 reg = <0x11830000 0x1000>; 295 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; 297 clock-names = "jpeg", "sclk"; 298 power-domains = <&pd_cam>; 299 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; 300 assigned-clock-rates = <0>, <150000000>; 301 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; 302 iommus = <&sysmmu_jpeg>; 303 status = "disabled"; 304 }; 305 306 sysmmu_jpeg: sysmmu@11a60000 { 307 compatible = "samsung,exynos-sysmmu"; 308 reg = <0x11a60000 0x1000>; 309 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 310 clock-names = "sysmmu", "master"; 311 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; 312 power-domains = <&pd_cam>; 313 #iommu-cells = <0>; 314 }; 315 316 fimd: fimd@11c00000 { 317 compatible = "samsung,exynos3250-fimd"; 318 reg = <0x11c00000 0x30000>; 319 interrupt-names = "fifo", "vsync", "lcd_sys"; 320 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 324 clock-names = "sclk_fimd", "fimd"; 325 power-domains = <&pd_lcd0>; 326 iommus = <&sysmmu_fimd0>; 327 samsung,sysreg = <&sys_reg>; 328 status = "disabled"; 329 }; 330 331 dsi_0: dsi@11c80000 { 332 compatible = "samsung,exynos3250-mipi-dsi"; 333 reg = <0x11C80000 0x10000>; 334 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 335 samsung,phy-type = <0>; 336 power-domains = <&pd_lcd0>; 337 phys = <&mipi_phy 1>; 338 phy-names = "dsim"; 339 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 340 clock-names = "bus_clk", "pll_clk"; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 status = "disabled"; 344 }; 345 346 sysmmu_fimd0: sysmmu@11e20000 { 347 compatible = "samsung,exynos-sysmmu"; 348 reg = <0x11e20000 0x1000>; 349 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 350 clock-names = "sysmmu", "master"; 351 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; 352 power-domains = <&pd_lcd0>; 353 #iommu-cells = <0>; 354 }; 355 356 hsotg: hsotg@12480000 { 357 compatible = "samsung,s3c6400-hsotg"; 358 reg = <0x12480000 0x20000>; 359 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&cmu CLK_USBOTG>; 361 clock-names = "otg"; 362 phys = <&exynos_usbphy 0>; 363 phy-names = "usb2-phy"; 364 status = "disabled"; 365 }; 366 367 mshc_0: mshc@12510000 { 368 compatible = "samsung,exynos5420-dw-mshc"; 369 reg = <0x12510000 0x1000>; 370 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; 372 clock-names = "biu", "ciu"; 373 fifo-depth = <0x80>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 status = "disabled"; 377 }; 378 379 mshc_1: mshc@12520000 { 380 compatible = "samsung,exynos5420-dw-mshc"; 381 reg = <0x12520000 0x1000>; 382 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; 384 clock-names = "biu", "ciu"; 385 fifo-depth = <0x80>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 status = "disabled"; 389 }; 390 391 mshc_2: mshc@12530000 { 392 compatible = "samsung,exynos5250-dw-mshc"; 393 reg = <0x12530000 0x1000>; 394 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; 396 clock-names = "biu", "ciu"; 397 fifo-depth = <0x80>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 status = "disabled"; 401 }; 402 403 exynos_usbphy: exynos-usbphy@125b0000 { 404 compatible = "samsung,exynos3250-usb2-phy"; 405 reg = <0x125B0000 0x100>; 406 samsung,pmureg-phandle = <&pmu_system_controller>; 407 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; 408 clock-names = "phy", "ref"; 409 #phy-cells = <1>; 410 status = "disabled"; 411 }; 412 413 pdma0: pdma@12680000 { 414 compatible = "arm,pl330", "arm,primecell"; 415 reg = <0x12680000 0x1000>; 416 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&cmu CLK_PDMA0>; 418 clock-names = "apb_pclk"; 419 #dma-cells = <1>; 420 #dma-channels = <8>; 421 #dma-requests = <32>; 422 }; 423 424 pdma1: pdma@12690000 { 425 compatible = "arm,pl330", "arm,primecell"; 426 reg = <0x12690000 0x1000>; 427 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&cmu CLK_PDMA1>; 429 clock-names = "apb_pclk"; 430 #dma-cells = <1>; 431 #dma-channels = <8>; 432 #dma-requests = <32>; 433 }; 434 435 adc: adc@126c0000 { 436 compatible = "samsung,exynos3250-adc"; 437 reg = <0x126C0000 0x100>; 438 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 439 clock-names = "adc", "sclk"; 440 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; 441 #io-channel-cells = <1>; 442 io-channel-ranges; 443 samsung,syscon-phandle = <&pmu_system_controller>; 444 status = "disabled"; 445 }; 446 447 gpu: gpu@13000000 { 448 compatible = "samsung,exynos4210-mali", "arm,mali-400"; 449 reg = <0x13000000 0x10000>; 450 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "gp", 462 "gpmmu", 463 "pp0", 464 "ppmmu0", 465 "pp1", 466 "ppmmu1", 467 "pp2", 468 "ppmmu2", 469 "pp3", 470 "ppmmu3", 471 "pmu"; 472 clocks = <&cmu CLK_G3D>, 473 <&cmu CLK_SCLK_G3D>; 474 clock-names = "bus", "core"; 475 power-domains = <&pd_g3d>; 476 status = "disabled"; 477 /* TODO: operating points for DVFS, assigned clock as 134 MHz */ 478 }; 479 480 mfc: codec@13400000 { 481 compatible = "samsung,mfc-v7"; 482 reg = <0x13400000 0x10000>; 483 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 484 clock-names = "mfc", "sclk_mfc"; 485 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; 486 power-domains = <&pd_mfc>; 487 iommus = <&sysmmu_mfc>; 488 }; 489 490 sysmmu_mfc: sysmmu@13620000 { 491 compatible = "samsung,exynos-sysmmu"; 492 reg = <0x13620000 0x1000>; 493 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 494 clock-names = "sysmmu", "master"; 495 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; 496 power-domains = <&pd_mfc>; 497 #iommu-cells = <0>; 498 }; 499 500 serial_0: serial@13800000 { 501 compatible = "samsung,exynos4210-uart"; 502 reg = <0x13800000 0x100>; 503 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 505 clock-names = "uart", "clk_uart_baud0"; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&uart0_data &uart0_fctl>; 508 status = "disabled"; 509 }; 510 511 serial_1: serial@13810000 { 512 compatible = "samsung,exynos4210-uart"; 513 reg = <0x13810000 0x100>; 514 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 516 clock-names = "uart", "clk_uart_baud0"; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&uart1_data>; 519 status = "disabled"; 520 }; 521 522 serial_2: serial@13820000 { 523 compatible = "samsung,exynos4210-uart"; 524 reg = <0x13820000 0x100>; 525 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; 527 clock-names = "uart", "clk_uart_baud0"; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&uart2_data>; 530 status = "disabled"; 531 }; 532 533 i2c_0: i2c@13860000 { 534 #address-cells = <1>; 535 #size-cells = <0>; 536 compatible = "samsung,s3c2440-i2c"; 537 reg = <0x13860000 0x100>; 538 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cmu CLK_I2C0>; 540 clock-names = "i2c"; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&i2c0_bus>; 543 status = "disabled"; 544 }; 545 546 i2c_1: i2c@13870000 { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 compatible = "samsung,s3c2440-i2c"; 550 reg = <0x13870000 0x100>; 551 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&cmu CLK_I2C1>; 553 clock-names = "i2c"; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&i2c1_bus>; 556 status = "disabled"; 557 }; 558 559 i2c_2: i2c@13880000 { 560 #address-cells = <1>; 561 #size-cells = <0>; 562 compatible = "samsung,s3c2440-i2c"; 563 reg = <0x13880000 0x100>; 564 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cmu CLK_I2C2>; 566 clock-names = "i2c"; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&i2c2_bus>; 569 status = "disabled"; 570 }; 571 572 i2c_3: i2c@13890000 { 573 #address-cells = <1>; 574 #size-cells = <0>; 575 compatible = "samsung,s3c2440-i2c"; 576 reg = <0x13890000 0x100>; 577 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cmu CLK_I2C3>; 579 clock-names = "i2c"; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&i2c3_bus>; 582 status = "disabled"; 583 }; 584 585 i2c_4: i2c@138a0000 { 586 #address-cells = <1>; 587 #size-cells = <0>; 588 compatible = "samsung,s3c2440-i2c"; 589 reg = <0x138A0000 0x100>; 590 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&cmu CLK_I2C4>; 592 clock-names = "i2c"; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&i2c4_bus>; 595 status = "disabled"; 596 }; 597 598 i2c_5: i2c@138b0000 { 599 #address-cells = <1>; 600 #size-cells = <0>; 601 compatible = "samsung,s3c2440-i2c"; 602 reg = <0x138B0000 0x100>; 603 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&cmu CLK_I2C5>; 605 clock-names = "i2c"; 606 pinctrl-names = "default"; 607 pinctrl-0 = <&i2c5_bus>; 608 status = "disabled"; 609 }; 610 611 i2c_6: i2c@138c0000 { 612 #address-cells = <1>; 613 #size-cells = <0>; 614 compatible = "samsung,s3c2440-i2c"; 615 reg = <0x138C0000 0x100>; 616 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&cmu CLK_I2C6>; 618 clock-names = "i2c"; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&i2c6_bus>; 621 status = "disabled"; 622 }; 623 624 i2c_7: i2c@138d0000 { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 compatible = "samsung,s3c2440-i2c"; 628 reg = <0x138D0000 0x100>; 629 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cmu CLK_I2C7>; 631 clock-names = "i2c"; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&i2c7_bus>; 634 status = "disabled"; 635 }; 636 637 spi_0: spi@13920000 { 638 compatible = "samsung,exynos4210-spi"; 639 reg = <0x13920000 0x100>; 640 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 641 dmas = <&pdma0 7>, <&pdma0 6>; 642 dma-names = "tx", "rx"; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; 646 clock-names = "spi", "spi_busclk0"; 647 samsung,spi-src-clk = <0>; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&spi0_bus>; 650 status = "disabled"; 651 }; 652 653 spi_1: spi@13930000 { 654 compatible = "samsung,exynos4210-spi"; 655 reg = <0x13930000 0x100>; 656 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 657 dmas = <&pdma1 7>, <&pdma1 6>; 658 dma-names = "tx", "rx"; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; 662 clock-names = "spi", "spi_busclk0"; 663 samsung,spi-src-clk = <0>; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&spi1_bus>; 666 status = "disabled"; 667 }; 668 669 i2s2: i2s@13970000 { 670 compatible = "samsung,s3c6410-i2s"; 671 reg = <0x13970000 0x100>; 672 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>; 674 clock-names = "iis", "i2s_opclk0"; 675 dmas = <&pdma0 14>, <&pdma0 13>; 676 dma-names = "tx", "rx"; 677 pinctrl-0 = <&i2s2_bus>; 678 pinctrl-names = "default"; 679 status = "disabled"; 680 }; 681 682 pwm: pwm@139d0000 { 683 compatible = "samsung,exynos4210-pwm"; 684 reg = <0x139D0000 0x1000>; 685 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 690 #pwm-cells = <3>; 691 status = "disabled"; 692 }; 693 694 ppmu_dmc0: ppmu_dmc0@106a0000 { 695 compatible = "samsung,exynos-ppmu"; 696 reg = <0x106a0000 0x2000>; 697 status = "disabled"; 698 }; 699 700 ppmu_dmc1: ppmu_dmc1@106b0000 { 701 compatible = "samsung,exynos-ppmu"; 702 reg = <0x106b0000 0x2000>; 703 status = "disabled"; 704 }; 705 706 ppmu_cpu: ppmu_cpu@106c0000 { 707 compatible = "samsung,exynos-ppmu"; 708 reg = <0x106c0000 0x2000>; 709 status = "disabled"; 710 }; 711 712 ppmu_rightbus: ppmu_rightbus@112a0000 { 713 compatible = "samsung,exynos-ppmu"; 714 reg = <0x112a0000 0x2000>; 715 clocks = <&cmu CLK_PPMURIGHT>; 716 clock-names = "ppmu"; 717 status = "disabled"; 718 }; 719 720 ppmu_leftbus: ppmu_leftbus0@116a0000 { 721 compatible = "samsung,exynos-ppmu"; 722 reg = <0x116a0000 0x2000>; 723 clocks = <&cmu CLK_PPMULEFT>; 724 clock-names = "ppmu"; 725 status = "disabled"; 726 }; 727 728 ppmu_camif: ppmu_camif@11ac0000 { 729 compatible = "samsung,exynos-ppmu"; 730 reg = <0x11ac0000 0x2000>; 731 clocks = <&cmu CLK_PPMUCAMIF>; 732 clock-names = "ppmu"; 733 status = "disabled"; 734 }; 735 736 ppmu_lcd0: ppmu_lcd0@11e40000 { 737 compatible = "samsung,exynos-ppmu"; 738 reg = <0x11e40000 0x2000>; 739 clocks = <&cmu CLK_PPMULCD0>; 740 clock-names = "ppmu"; 741 status = "disabled"; 742 }; 743 744 ppmu_fsys: ppmu_fsys@12630000 { 745 compatible = "samsung,exynos-ppmu"; 746 reg = <0x12630000 0x2000>; 747 clocks = <&cmu CLK_PPMUFILE>; 748 clock-names = "ppmu"; 749 status = "disabled"; 750 }; 751 752 ppmu_g3d: ppmu_g3d@13220000 { 753 compatible = "samsung,exynos-ppmu"; 754 reg = <0x13220000 0x2000>; 755 clocks = <&cmu CLK_PPMUG3D>; 756 clock-names = "ppmu"; 757 status = "disabled"; 758 }; 759 760 ppmu_mfc: ppmu_mfc@13660000 { 761 compatible = "samsung,exynos-ppmu"; 762 reg = <0x13660000 0x2000>; 763 clocks = <&cmu CLK_PPMUMFC_L>; 764 clock-names = "ppmu"; 765 status = "disabled"; 766 }; 767 768 bus_dmc: bus_dmc { 769 compatible = "samsung,exynos-bus"; 770 clocks = <&cmu_dmc CLK_DIV_DMC>; 771 clock-names = "bus"; 772 operating-points-v2 = <&bus_dmc_opp_table>; 773 status = "disabled"; 774 }; 775 776 bus_dmc_opp_table: opp_table1 { 777 compatible = "operating-points-v2"; 778 opp-shared; 779 780 opp-50000000 { 781 opp-hz = /bits/ 64 <50000000>; 782 opp-microvolt = <800000>; 783 }; 784 opp-100000000 { 785 opp-hz = /bits/ 64 <100000000>; 786 opp-microvolt = <800000>; 787 }; 788 opp-134000000 { 789 opp-hz = /bits/ 64 <134000000>; 790 opp-microvolt = <800000>; 791 }; 792 opp-200000000 { 793 opp-hz = /bits/ 64 <200000000>; 794 opp-microvolt = <825000>; 795 }; 796 opp-400000000 { 797 opp-hz = /bits/ 64 <400000000>; 798 opp-microvolt = <875000>; 799 }; 800 }; 801 802 bus_leftbus: bus_leftbus { 803 compatible = "samsung,exynos-bus"; 804 clocks = <&cmu CLK_DIV_GDL>; 805 clock-names = "bus"; 806 operating-points-v2 = <&bus_leftbus_opp_table>; 807 status = "disabled"; 808 }; 809 810 bus_rightbus: bus_rightbus { 811 compatible = "samsung,exynos-bus"; 812 clocks = <&cmu CLK_DIV_GDR>; 813 clock-names = "bus"; 814 operating-points-v2 = <&bus_leftbus_opp_table>; 815 status = "disabled"; 816 }; 817 818 bus_lcd0: bus_lcd0 { 819 compatible = "samsung,exynos-bus"; 820 clocks = <&cmu CLK_DIV_ACLK_160>; 821 clock-names = "bus"; 822 operating-points-v2 = <&bus_leftbus_opp_table>; 823 status = "disabled"; 824 }; 825 826 bus_fsys: bus_fsys { 827 compatible = "samsung,exynos-bus"; 828 clocks = <&cmu CLK_DIV_ACLK_200>; 829 clock-names = "bus"; 830 operating-points-v2 = <&bus_leftbus_opp_table>; 831 status = "disabled"; 832 }; 833 834 bus_mcuisp: bus_mcuisp { 835 compatible = "samsung,exynos-bus"; 836 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; 837 clock-names = "bus"; 838 operating-points-v2 = <&bus_mcuisp_opp_table>; 839 status = "disabled"; 840 }; 841 842 bus_isp: bus_isp { 843 compatible = "samsung,exynos-bus"; 844 clocks = <&cmu CLK_DIV_ACLK_266>; 845 clock-names = "bus"; 846 operating-points-v2 = <&bus_isp_opp_table>; 847 status = "disabled"; 848 }; 849 850 bus_peril: bus_peril { 851 compatible = "samsung,exynos-bus"; 852 clocks = <&cmu CLK_DIV_ACLK_100>; 853 clock-names = "bus"; 854 operating-points-v2 = <&bus_peril_opp_table>; 855 status = "disabled"; 856 }; 857 858 bus_mfc: bus_mfc { 859 compatible = "samsung,exynos-bus"; 860 clocks = <&cmu CLK_SCLK_MFC>; 861 clock-names = "bus"; 862 operating-points-v2 = <&bus_leftbus_opp_table>; 863 status = "disabled"; 864 }; 865 866 bus_leftbus_opp_table: opp_table2 { 867 compatible = "operating-points-v2"; 868 opp-shared; 869 870 opp-50000000 { 871 opp-hz = /bits/ 64 <50000000>; 872 opp-microvolt = <900000>; 873 }; 874 opp-80000000 { 875 opp-hz = /bits/ 64 <80000000>; 876 opp-microvolt = <900000>; 877 }; 878 opp-100000000 { 879 opp-hz = /bits/ 64 <100000000>; 880 opp-microvolt = <1000000>; 881 }; 882 opp-134000000 { 883 opp-hz = /bits/ 64 <134000000>; 884 opp-microvolt = <1000000>; 885 }; 886 opp-200000000 { 887 opp-hz = /bits/ 64 <200000000>; 888 opp-microvolt = <1000000>; 889 }; 890 }; 891 892 bus_mcuisp_opp_table: opp_table3 { 893 compatible = "operating-points-v2"; 894 opp-shared; 895 896 opp-50000000 { 897 opp-hz = /bits/ 64 <50000000>; 898 }; 899 opp-80000000 { 900 opp-hz = /bits/ 64 <80000000>; 901 }; 902 opp-100000000 { 903 opp-hz = /bits/ 64 <100000000>; 904 }; 905 opp-200000000 { 906 opp-hz = /bits/ 64 <200000000>; 907 }; 908 opp-400000000 { 909 opp-hz = /bits/ 64 <400000000>; 910 }; 911 }; 912 913 bus_isp_opp_table: opp_table4 { 914 compatible = "operating-points-v2"; 915 opp-shared; 916 917 opp-50000000 { 918 opp-hz = /bits/ 64 <50000000>; 919 }; 920 opp-80000000 { 921 opp-hz = /bits/ 64 <80000000>; 922 }; 923 opp-100000000 { 924 opp-hz = /bits/ 64 <100000000>; 925 }; 926 opp-200000000 { 927 opp-hz = /bits/ 64 <200000000>; 928 }; 929 opp-300000000 { 930 opp-hz = /bits/ 64 <300000000>; 931 }; 932 }; 933 934 bus_peril_opp_table: opp_table5 { 935 compatible = "operating-points-v2"; 936 opp-shared; 937 938 opp-50000000 { 939 opp-hz = /bits/ 64 <50000000>; 940 }; 941 opp-80000000 { 942 opp-hz = /bits/ 64 <80000000>; 943 }; 944 opp-100000000 { 945 opp-hz = /bits/ 64 <100000000>; 946 }; 947 }; 948 }; 949}; 950 951#include "exynos3250-pinctrl.dtsi" 952#include "exynos-syscon-restart.dtsi" 953
