1Cortina Systems Gemini Ethernet Controller 2========================================== 3 4This ethernet controller is found in the Gemini SoC family: 5StorLink SL3512 and SL3516, also known as Cortina Systems 6CS3512 and CS3516. 7 8Required properties: 9- compatible: must be "cortina,gemini-ethernet" 10- reg: must contain the global registers and the V-bit and A-bit 11 memory areas, in total three register sets. 12- syscon: a phandle to the system controller 13- #address-cells: must be specified, must be <1> 14- #size-cells: must be specified, must be <1> 15- ranges: should be state like this giving a 1:1 address translation 16 for the subnodes 17 18The subnodes represents the two ethernet ports in this device. 19They are not independent of each other since they share resources 20in the parent node, and are thus children. 21 22Required subnodes: 23- port0: contains the resources for ethernet port 0 24- port1: contains the resources for ethernet port 1 25 26Required subnode properties: 27- compatible: must be "cortina,gemini-ethernet-port" 28- reg: must contain two register areas: the DMA/TOE memory and 29 the GMAC memory area of the port 30- interrupts: should contain the interrupt line of the port. 31 this is nominally a level interrupt active high. 32- resets: this must provide an SoC-integrated reset line for 33 the port. 34- clocks: this should contain a handle to the PCLK clock for 35 clocking the silicon in this port 36- clock-names: must be "PCLK" 37 38Optional subnode properties: 39- phy-mode: see ethernet.txt 40- phy-handle: see ethernet.txt 41 42Example: 43 44mdio-bus { 45 (...) 46 phy0: ethernet-phy@1 { 47 reg = <1>; 48 device_type = "ethernet-phy"; 49 }; 50 phy1: ethernet-phy@3 { 51 reg = <3>; 52 device_type = "ethernet-phy"; 53 }; 54}; 55 56 57ethernet@60000000 { 58 compatible = "cortina,gemini-ethernet"; 59 reg = <0x60000000 0x4000>, /* Global registers, queue */ 60 <0x60004000 0x2000>, /* V-bit */ 61 <0x60006000 0x2000>; /* A-bit */ 62 syscon = <&syscon>; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 ranges; 66 67 gmac0: ethernet-port@0 { 68 compatible = "cortina,gemini-ethernet-port"; 69 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ 70 <0x6000a000 0x2000>; /* Port 0 GMAC */ 71 interrupt-parent = <&intcon>; 72 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 73 resets = <&syscon GEMINI_RESET_GMAC0>; 74 clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; 75 clock-names = "PCLK"; 76 phy-mode = "rgmii"; 77 phy-handle = <&phy0>; 78 }; 79 80 gmac1: ethernet-port@1 { 81 compatible = "cortina,gemini-ethernet-port"; 82 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ 83 <0x6000e000 0x2000>; /* Port 1 GMAC */ 84 interrupt-parent = <&intcon>; 85 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 86 resets = <&syscon GEMINI_RESET_GMAC1>; 87 clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; 88 clock-names = "PCLK"; 89 phy-mode = "rgmii"; 90 phy-handle = <&phy1>; 91 }; 92}; 93