1Qualcomm Technologies Inc. adreno/snapdragon DSI output
2
3DSI Controller:
4Required properties:
5- compatible:
6  * "qcom,mdss-dsi-ctrl"
7- reg: Physical base address and length of the registers of controller
8- reg-names: The names of register regions. The following regions are required:
9  * "dsi_ctrl"
10- interrupts: The interrupt signal from the DSI block.
11- power-domains: Should be <&mmcc MDSS_GDSC>.
12- clocks: Phandles to device clocks.
13- clock-names: the following clocks are required:
14  * "mdp_core"
15  * "iface"
16  * "bus"
17  * "core_mmss"
18  * "byte"
19  * "pixel"
20  * "core"
21  For DSIv2, we need an additional clock:
22   * "src"
23  For DSI6G v2.0 onwards, we need also need the clock:
24   * "byte_intf"
25- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
27  by a DSI PHY block. See [1] for details on clock bindings.
28- vdd-supply: phandle to vdd regulator device node
29- vddio-supply: phandle to vdd-io regulator device node
30- vdda-supply: phandle to vdda regulator device node
31- phys: phandle to DSI PHY device node
32- phy-names: the name of the corresponding PHY device
33- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
34- ports: Contains 2 DSI controller ports as child nodes. Each port contains
35  an endpoint subnode as defined in [2] and [3].
36
37Optional properties:
38- panel@0: Node of panel connected to this DSI controller.
39  See files in [4] for each supported panel.
40- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
41  driving a panel which needs 2 DSI links.
42- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
43  the master link of the 2-DSI panel.
44- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
45  driving a 2-DSI panel whose 2 links need receive command simultaneously.
46- pinctrl-names: the pin control state names; should contain "default"
47- pinctrl-0: the default pinctrl state (active)
48- pinctrl-n: the "sleep" pinctrl state
49- ports: contains DSI controller input and output ports as children, each
50  containing one endpoint subnode.
51
52  DSI Endpoint properties:
53  - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
54    input endpoint. For port@1, set to the MDP interface output. See [2] for
55    device graph info.
56
57  - data-lanes: this describes how the physical DSI data lanes are mapped
58    to the logical lanes on the given platform. The value contained in
59    index n describes what physical lane is mapped to the logical lane n
60    (DATAn, where n lies between 0 and 3). The clock lane position is fixed
61    and can't be changed. Hence, they aren't a part of the DT bindings. See
62    [3] for more info on the data-lanes property.
63
64    For example:
65
66    data-lanes = <3 0 1 2>;
67
68    The above mapping describes that the logical data lane DATA0 is mapped to
69    the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
70    to phys DATA1 and logic DATA3 to phys DATA2.
71
72    There are only a limited number of physical to logical mappings possible:
73    <0 1 2 3>
74    <1 2 3 0>
75    <2 3 0 1>
76    <3 0 1 2>
77    <0 3 2 1>
78    <1 0 3 2>
79    <2 1 0 3>
80    <3 2 1 0>
81
82DSI PHY:
83Required properties:
84- compatible: Could be the following
85  * "qcom,dsi-phy-28nm-hpm"
86  * "qcom,dsi-phy-28nm-lp"
87  * "qcom,dsi-phy-20nm"
88  * "qcom,dsi-phy-28nm-8960"
89  * "qcom,dsi-phy-14nm"
90  * "qcom,dsi-phy-14nm-660"
91  * "qcom,dsi-phy-10nm"
92  * "qcom,dsi-phy-10nm-8998"
93  * "qcom,dsi-phy-7nm"
94  * "qcom,dsi-phy-7nm-8150"
95- reg: Physical base address and length of the registers of PLL, PHY. Some
96  revisions require the PHY regulator base address, whereas others require the
97  PHY lane base address. See below for each PHY revision.
98- reg-names: The names of register regions. The following regions are required:
99  For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
100  * "dsi_pll"
101  * "dsi_phy"
102  * "dsi_phy_regulator"
103  For DSI 14nm, 10nm and 7nm PHYs:
104  * "dsi_pll"
105  * "dsi_phy"
106  * "dsi_phy_lane"
107- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
108  2 clocks: A byte clock (index 0), and a pixel clock (index 1).
109- power-domains: Should be <&mmcc MDSS_GDSC>.
110- clocks: Phandles to device clocks. See [1] for details on clock bindings.
111- clock-names: the following clocks are required:
112  * "iface"
113  * "ref" (only required for new DTS files/entries)
114  For 28nm HPM/LP, 28nm 8960 PHYs:
115- vddio-supply: phandle to vdd-io regulator device node
116  For 20nm PHY:
117- vddio-supply: phandle to vdd-io regulator device node
118- vcca-supply: phandle to vcca regulator device node
119  For 14nm PHY:
120- vcca-supply: phandle to vcca regulator device node
121  For 10nm and 7nm PHY:
122- vdds-supply: phandle to vdds regulator device node
123
124Optional properties:
125- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
126  regulator is wanted.
127- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode
128					panels in microseconds. Driver uses this number to adjust
129					the clock rate according to the expected transfer time.
130					Increasing this value would slow down the mdp processing
131					and can result in slower performance.
132					Decreasing this value can speed up the mdp processing,
133					but this can also impact power consumption.
134					As a rule this time should not be higher than the time
135					that would be expected with the processing at the
136					dsi link rate since anyways this would be the maximum
137					transfer time that could be achieved.
138					If ping pong split is enabled, this time should not be higher
139					than two times the dsi link rate time.
140					If the property is not specified, then the default value is 14000 us.
141
142[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
143[2] Documentation/devicetree/bindings/graph.txt
144[3] Documentation/devicetree/bindings/media/video-interfaces.txt
145[4] Documentation/devicetree/bindings/display/panel/
146
147Example:
148	dsi0: dsi@fd922800 {
149		compatible = "qcom,mdss-dsi-ctrl";
150		qcom,dsi-host-index = <0>;
151		interrupt-parent = <&mdp>;
152		interrupts = <4 0>;
153		reg-names = "dsi_ctrl";
154		reg = <0xfd922800 0x200>;
155		power-domains = <&mmcc MDSS_GDSC>;
156		clock-names =
157			"bus",
158			"byte",
159			"core",
160			"core_mmss",
161			"iface",
162			"mdp_core",
163			"pixel";
164		clocks =
165			<&mmcc MDSS_AXI_CLK>,
166			<&mmcc MDSS_BYTE0_CLK>,
167			<&mmcc MDSS_ESC0_CLK>,
168			<&mmcc MMSS_MISC_AHB_CLK>,
169			<&mmcc MDSS_AHB_CLK>,
170			<&mmcc MDSS_MDP_CLK>,
171			<&mmcc MDSS_PCLK0_CLK>;
172
173		assigned-clocks =
174				 <&mmcc BYTE0_CLK_SRC>,
175				 <&mmcc PCLK0_CLK_SRC>;
176		assigned-clock-parents =
177				 <&dsi_phy0 0>,
178				 <&dsi_phy0 1>;
179
180		vdda-supply = <&pma8084_l2>;
181		vdd-supply = <&pma8084_l22>;
182		vddio-supply = <&pma8084_l12>;
183
184		phys = <&dsi_phy0>;
185		phy-names ="dsi-phy";
186
187		qcom,dual-dsi-mode;
188		qcom,master-dsi;
189		qcom,sync-dual-dsi;
190
191		qcom,mdss-mdp-transfer-time-us = <12000>;
192
193		pinctrl-names = "default", "sleep";
194		pinctrl-0 = <&dsi_active>;
195		pinctrl-1 = <&dsi_suspend>;
196
197		ports {
198			#address-cells = <1>;
199			#size-cells = <0>;
200
201			port@0 {
202				reg = <0>;
203				dsi0_in: endpoint {
204					remote-endpoint = <&mdp_intf1_out>;
205				};
206			};
207
208			port@1 {
209				reg = <1>;
210				dsi0_out: endpoint {
211					remote-endpoint = <&panel_in>;
212					data-lanes = <0 1 2 3>;
213				};
214			};
215		};
216
217		panel: panel@0 {
218			compatible = "sharp,lq101r1sx01";
219			reg = <0>;
220			link2 = <&secondary>;
221
222			power-supply = <...>;
223			backlight = <...>;
224
225			port {
226				panel_in: endpoint {
227					remote-endpoint = <&dsi0_out>;
228				};
229			};
230		};
231	};
232
233	dsi_phy0: dsi-phy@fd922a00 {
234		compatible = "qcom,dsi-phy-28nm-hpm";
235		qcom,dsi-phy-index = <0>;
236		reg-names =
237			"dsi_pll",
238			"dsi_phy",
239			"dsi_phy_regulator";
240		reg =   <0xfd922a00 0xd4>,
241			<0xfd922b00 0x2b0>,
242			<0xfd922d80 0x7b>;
243		clock-names = "iface";
244		clocks = <&mmcc MDSS_AHB_CLK>;
245		#clock-cells = <1>;
246		vddio-supply = <&pma8084_l12>;
247
248		qcom,dsi-phy-regulator-ldo-mode;
249	};
250