1Mediatek HDMI Encoder
2=====================
3
4The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
5its parallel input.
6
7Required properties:
8- compatible: Should be "mediatek,<chip>-hdmi".
9- the supported chips are mt2701, mt7623 and mt8173
10- reg: Physical base address and length of the controller's registers
11- interrupts: The interrupt signal from the function block.
12- clocks: device clocks
13  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
14- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
15- phys: phandle link to the HDMI PHY node.
16  See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
17- phy-names: must contain "hdmi"
18- mediatek,syscon-hdmi: phandle link and register offset to the system
19  configuration registers. For mt8173 this must be offset 0x900 into the
20  MMSYS_CONFIG region: <&mmsys 0x900>.
21- ports: A node containing input and output port nodes with endpoint
22  definitions as documented in Documentation/devicetree/bindings/graph.txt.
23- port@0: The input port in the ports node should be connected to a DPI output
24  port.
25- port@1: The output port in the ports node should be connected to the input
26  port of a connector node that contains a ddc-i2c-bus property, or to the
27  input port of an attached bridge chip, such as a SlimPort transmitter.
28
29HDMI CEC
30========
31
32The HDMI CEC controller handles hotplug detection and CEC communication.
33
34Required properties:
35- compatible: Should be "mediatek,<chip>-cec"
36- the supported chips are mt7623 and mt8173
37- reg: Physical base address and length of the controller's registers
38- interrupts: The interrupt signal from the function block.
39- clocks: device clock
40
41HDMI DDC
42========
43
44The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
45The Mediatek's I2C controller is used to interface with I2C devices.
46
47Required properties:
48- compatible: Should be "mediatek,<chip>-hdmi-ddc"
49- the supported chips are mt7623 and mt8173
50- reg: Physical base address and length of the controller's registers
51- clocks: device clock
52- clock-names: Should be "ddc-i2c".
53
54HDMI PHY
55========
56
57The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
58output and drives the HDMI pads.
59
60Required properties:
61- compatible: "mediatek,<chip>-hdmi-phy"
62- the supported chips are mt2701, mt7623 and mt8173
63- reg: Physical base address and length of the module's registers
64- clocks: PLL reference clock
65- clock-names: must contain "pll_ref"
66- clock-output-names: must be "hdmitx_dig_cts" on mt8173
67- #phy-cells: must be <0>
68- #clock-cells: must be <0>
69
70Optional properties:
71- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
72- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
73
74Example:
75
76cec: cec@10013000 {
77	compatible = "mediatek,mt8173-cec";
78	reg = <0 0x10013000 0 0xbc>;
79	interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
80	clocks = <&infracfg CLK_INFRA_CEC>;
81};
82
83hdmi_phy: hdmi-phy@10209100 {
84	compatible = "mediatek,mt8173-hdmi-phy";
85	reg = <0 0x10209100 0 0x24>;
86	clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
87	clock-names = "pll_ref";
88	clock-output-names = "hdmitx_dig_cts";
89	mediatek,ibias = <0xa>;
90	mediatek,ibias_up = <0x1c>;
91	#clock-cells = <0>;
92	#phy-cells = <0>;
93};
94
95hdmi_ddc0: i2c@11012000 {
96	compatible = "mediatek,mt8173-hdmi-ddc";
97	reg = <0 0x11012000 0 0x1c>;
98	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
99	clocks = <&pericfg CLK_PERI_I2C5>;
100	clock-names = "ddc-i2c";
101};
102
103hdmi0: hdmi@14025000 {
104	compatible = "mediatek,mt8173-hdmi";
105	reg = <0 0x14025000 0 0x400>;
106	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
107	clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
108		 <&mmsys CLK_MM_HDMI_PLLCK>,
109		 <&mmsys CLK_MM_HDMI_AUDIO>,
110		 <&mmsys CLK_MM_HDMI_SPDIF>;
111	clock-names = "pixel", "pll", "bclk", "spdif";
112	pinctrl-names = "default";
113	pinctrl-0 = <&hdmi_pin>;
114	phys = <&hdmi_phy>;
115	phy-names = "hdmi";
116	mediatek,syscon-hdmi = <&mmsys 0x900>;
117	assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
118	assigned-clock-parents = <&hdmi_phy>;
119
120	ports {
121		#address-cells = <1>;
122		#size-cells = <0>;
123
124		port@0 {
125			reg = <0>;
126
127			hdmi0_in: endpoint {
128				remote-endpoint = <&dpi0_out>;
129			};
130		};
131
132		port@1 {
133			reg = <1>;
134
135			hdmi0_out: endpoint {
136				remote-endpoint = <&hdmi_con_in>;
137			};
138		};
139	};
140};
141
142connector {
143	compatible = "hdmi-connector";
144	type = "a";
145	ddc-i2c-bus = <&hdmiddc0>;
146
147	port {
148		hdmi_con_in: endpoint {
149			remote-endpoint = <&hdmi0_out>;
150		};
151	};
152};
153