1 /*
2 * intel_hdmi_audio.c - Intel HDMI audio driver
3 *
4 * Copyright (C) 2016 Intel Corp
5 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
6 * Ramesh Babu K V <ramesh.babu@intel.com>
7 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
8 * Jerome Anand <jerome.anand@intel.com>
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 * ALSA driver for Intel HDMI audio
22 */
23
24 #include <linux/types.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/slab.h>
28 #include <linux/module.h>
29 #include <linux/interrupt.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <asm/set_memory.h>
34 #include <sound/core.h>
35 #include <sound/asoundef.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/initval.h>
39 #include <sound/control.h>
40 #include <sound/jack.h>
41 #include <drm/drm_edid.h>
42 #include <drm/intel_lpe_audio.h>
43 #include "intel_hdmi_audio.h"
44
45 #define for_each_pipe(card_ctx, pipe) \
46 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++)
47 #define for_each_port(card_ctx, port) \
48 for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++)
49
50 /*standard module options for ALSA. This module supports only one card*/
51 static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
52 static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
53 static bool single_port;
54
55 module_param_named(index, hdmi_card_index, int, 0444);
56 MODULE_PARM_DESC(index,
57 "Index value for INTEL Intel HDMI Audio controller.");
58 module_param_named(id, hdmi_card_id, charp, 0444);
59 MODULE_PARM_DESC(id,
60 "ID string for INTEL Intel HDMI Audio controller.");
61 module_param(single_port, bool, 0444);
62 MODULE_PARM_DESC(single_port,
63 "Single-port mode (for compatibility)");
64
65 /*
66 * ELD SA bits in the CEA Speaker Allocation data block
67 */
68 static const int eld_speaker_allocation_bits[] = {
69 [0] = FL | FR,
70 [1] = LFE,
71 [2] = FC,
72 [3] = RL | RR,
73 [4] = RC,
74 [5] = FLC | FRC,
75 [6] = RLC | RRC,
76 /* the following are not defined in ELD yet */
77 [7] = 0,
78 };
79
80 /*
81 * This is an ordered list!
82 *
83 * The preceding ones have better chances to be selected by
84 * hdmi_channel_allocation().
85 */
86 static struct cea_channel_speaker_allocation channel_allocations[] = {
87 /* channel: 7 6 5 4 3 2 1 0 */
88 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
89 /* 2.1 */
90 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
91 /* Dolby Surround */
92 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
93 /* surround40 */
94 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
95 /* surround41 */
96 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
97 /* surround50 */
98 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
99 /* surround51 */
100 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
101 /* 6.1 */
102 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
103 /* surround71 */
104 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
105
106 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
107 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
108 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
109 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
110 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
111 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
112 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
113 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
114 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
115 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
116 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
117 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
118 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
119 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
120 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
121 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
122 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
123 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
124 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
125 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
126 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
127 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
128 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
129 };
130
131 static const struct channel_map_table map_tables[] = {
132 { SNDRV_CHMAP_FL, 0x00, FL },
133 { SNDRV_CHMAP_FR, 0x01, FR },
134 { SNDRV_CHMAP_RL, 0x04, RL },
135 { SNDRV_CHMAP_RR, 0x05, RR },
136 { SNDRV_CHMAP_LFE, 0x02, LFE },
137 { SNDRV_CHMAP_FC, 0x03, FC },
138 { SNDRV_CHMAP_RLC, 0x06, RLC },
139 { SNDRV_CHMAP_RRC, 0x07, RRC },
140 {} /* terminator */
141 };
142
143 /* hardware capability structure */
144 static const struct snd_pcm_hardware had_pcm_hardware = {
145 .info = (SNDRV_PCM_INFO_INTERLEAVED |
146 SNDRV_PCM_INFO_MMAP |
147 SNDRV_PCM_INFO_MMAP_VALID |
148 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
149 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
150 SNDRV_PCM_FMTBIT_S24_LE |
151 SNDRV_PCM_FMTBIT_S32_LE),
152 .rates = SNDRV_PCM_RATE_32000 |
153 SNDRV_PCM_RATE_44100 |
154 SNDRV_PCM_RATE_48000 |
155 SNDRV_PCM_RATE_88200 |
156 SNDRV_PCM_RATE_96000 |
157 SNDRV_PCM_RATE_176400 |
158 SNDRV_PCM_RATE_192000,
159 .rate_min = HAD_MIN_RATE,
160 .rate_max = HAD_MAX_RATE,
161 .channels_min = HAD_MIN_CHANNEL,
162 .channels_max = HAD_MAX_CHANNEL,
163 .buffer_bytes_max = HAD_MAX_BUFFER,
164 .period_bytes_min = HAD_MIN_PERIOD_BYTES,
165 .period_bytes_max = HAD_MAX_PERIOD_BYTES,
166 .periods_min = HAD_MIN_PERIODS,
167 .periods_max = HAD_MAX_PERIODS,
168 .fifo_size = HAD_FIFO_SIZE,
169 };
170
171 /* Get the active PCM substream;
172 * Call had_substream_put() for unreferecing.
173 * Don't call this inside had_spinlock, as it takes by itself
174 */
175 static struct snd_pcm_substream *
had_substream_get(struct snd_intelhad * intelhaddata)176 had_substream_get(struct snd_intelhad *intelhaddata)
177 {
178 struct snd_pcm_substream *substream;
179 unsigned long flags;
180
181 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
182 substream = intelhaddata->stream_info.substream;
183 if (substream)
184 intelhaddata->stream_info.substream_refcount++;
185 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
186 return substream;
187 }
188
189 /* Unref the active PCM substream;
190 * Don't call this inside had_spinlock, as it takes by itself
191 */
had_substream_put(struct snd_intelhad * intelhaddata)192 static void had_substream_put(struct snd_intelhad *intelhaddata)
193 {
194 unsigned long flags;
195
196 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
197 intelhaddata->stream_info.substream_refcount--;
198 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
199 }
200
had_config_offset(int pipe)201 static u32 had_config_offset(int pipe)
202 {
203 switch (pipe) {
204 default:
205 case 0:
206 return AUDIO_HDMI_CONFIG_A;
207 case 1:
208 return AUDIO_HDMI_CONFIG_B;
209 case 2:
210 return AUDIO_HDMI_CONFIG_C;
211 }
212 }
213
214 /* Register access functions */
had_read_register_raw(struct snd_intelhad_card * card_ctx,int pipe,u32 reg)215 static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx,
216 int pipe, u32 reg)
217 {
218 return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg);
219 }
220
had_write_register_raw(struct snd_intelhad_card * card_ctx,int pipe,u32 reg,u32 val)221 static void had_write_register_raw(struct snd_intelhad_card *card_ctx,
222 int pipe, u32 reg, u32 val)
223 {
224 iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg);
225 }
226
had_read_register(struct snd_intelhad * ctx,u32 reg,u32 * val)227 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
228 {
229 if (!ctx->connected)
230 *val = 0;
231 else
232 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg);
233 }
234
had_write_register(struct snd_intelhad * ctx,u32 reg,u32 val)235 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
236 {
237 if (ctx->connected)
238 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val);
239 }
240
241 /*
242 * enable / disable audio configuration
243 *
244 * The normal read/modify should not directly be used on VLV2 for
245 * updating AUD_CONFIG register.
246 * This is because:
247 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
248 * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
249 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
250 * register. This field should be 1xy binary for configuration with 6 or
251 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
252 * causes the "channels" field to be updated as 0xy binary resulting in
253 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
254 * appropriate value when doing read-modify of AUD_CONFIG register.
255 */
had_enable_audio(struct snd_intelhad * intelhaddata,bool enable)256 static void had_enable_audio(struct snd_intelhad *intelhaddata,
257 bool enable)
258 {
259 /* update the cached value */
260 intelhaddata->aud_config.regx.aud_en = enable;
261 had_write_register(intelhaddata, AUD_CONFIG,
262 intelhaddata->aud_config.regval);
263 }
264
265 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */
had_ack_irqs(struct snd_intelhad * ctx)266 static void had_ack_irqs(struct snd_intelhad *ctx)
267 {
268 u32 status_reg;
269
270 if (!ctx->connected)
271 return;
272 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
273 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
274 had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
275 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
276 }
277
278 /* Reset buffer pointers */
had_reset_audio(struct snd_intelhad * intelhaddata)279 static void had_reset_audio(struct snd_intelhad *intelhaddata)
280 {
281 had_write_register(intelhaddata, AUD_HDMI_STATUS,
282 AUD_HDMI_STATUSG_MASK_FUNCRST);
283 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
284 }
285
286 /*
287 * initialize audio channel status registers
288 * This function is called in the prepare callback
289 */
had_prog_status_reg(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)290 static int had_prog_status_reg(struct snd_pcm_substream *substream,
291 struct snd_intelhad *intelhaddata)
292 {
293 union aud_ch_status_0 ch_stat0 = {.regval = 0};
294 union aud_ch_status_1 ch_stat1 = {.regval = 0};
295
296 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
297 IEC958_AES0_NONAUDIO) >> 1;
298 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
299 IEC958_AES3_CON_CLOCK) >> 4;
300
301 switch (substream->runtime->rate) {
302 case AUD_SAMPLE_RATE_32:
303 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
304 break;
305
306 case AUD_SAMPLE_RATE_44_1:
307 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
308 break;
309 case AUD_SAMPLE_RATE_48:
310 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
311 break;
312 case AUD_SAMPLE_RATE_88_2:
313 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
314 break;
315 case AUD_SAMPLE_RATE_96:
316 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
317 break;
318 case AUD_SAMPLE_RATE_176_4:
319 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
320 break;
321 case AUD_SAMPLE_RATE_192:
322 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
323 break;
324
325 default:
326 /* control should never come here */
327 return -EINVAL;
328 }
329
330 had_write_register(intelhaddata,
331 AUD_CH_STATUS_0, ch_stat0.regval);
332
333 switch (substream->runtime->format) {
334 case SNDRV_PCM_FORMAT_S16_LE:
335 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
336 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
337 break;
338 case SNDRV_PCM_FORMAT_S24_LE:
339 case SNDRV_PCM_FORMAT_S32_LE:
340 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
341 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
342 break;
343 default:
344 return -EINVAL;
345 }
346
347 had_write_register(intelhaddata,
348 AUD_CH_STATUS_1, ch_stat1.regval);
349 return 0;
350 }
351
352 /*
353 * function to initialize audio
354 * registers and buffer confgiuration registers
355 * This function is called in the prepare callback
356 */
had_init_audio_ctrl(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)357 static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
358 struct snd_intelhad *intelhaddata)
359 {
360 union aud_cfg cfg_val = {.regval = 0};
361 union aud_buf_config buf_cfg = {.regval = 0};
362 u8 channels;
363
364 had_prog_status_reg(substream, intelhaddata);
365
366 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
367 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
368 buf_cfg.regx.aud_delay = 0;
369 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
370
371 channels = substream->runtime->channels;
372 cfg_val.regx.num_ch = channels - 2;
373 if (channels <= 2)
374 cfg_val.regx.layout = LAYOUT0;
375 else
376 cfg_val.regx.layout = LAYOUT1;
377
378 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
379 cfg_val.regx.packet_mode = 1;
380
381 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE)
382 cfg_val.regx.left_align = 1;
383
384 cfg_val.regx.val_bit = 1;
385
386 /* fix up the DP bits */
387 if (intelhaddata->dp_output) {
388 cfg_val.regx.dp_modei = 1;
389 cfg_val.regx.set = 1;
390 }
391
392 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
393 intelhaddata->aud_config = cfg_val;
394 return 0;
395 }
396
397 /*
398 * Compute derived values in channel_allocations[].
399 */
init_channel_allocations(void)400 static void init_channel_allocations(void)
401 {
402 int i, j;
403 struct cea_channel_speaker_allocation *p;
404
405 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
406 p = channel_allocations + i;
407 p->channels = 0;
408 p->spk_mask = 0;
409 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
410 if (p->speakers[j]) {
411 p->channels++;
412 p->spk_mask |= p->speakers[j];
413 }
414 }
415 }
416
417 /*
418 * The transformation takes two steps:
419 *
420 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
421 * spk_mask => (channel_allocations[]) => ai->CA
422 *
423 * TODO: it could select the wrong CA from multiple candidates.
424 */
had_channel_allocation(struct snd_intelhad * intelhaddata,int channels)425 static int had_channel_allocation(struct snd_intelhad *intelhaddata,
426 int channels)
427 {
428 int i;
429 int ca = 0;
430 int spk_mask = 0;
431
432 /*
433 * CA defaults to 0 for basic stereo audio
434 */
435 if (channels <= 2)
436 return 0;
437
438 /*
439 * expand ELD's speaker allocation mask
440 *
441 * ELD tells the speaker mask in a compact(paired) form,
442 * expand ELD's notions to match the ones used by Audio InfoFrame.
443 */
444
445 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
446 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
447 spk_mask |= eld_speaker_allocation_bits[i];
448 }
449
450 /* search for the first working match in the CA table */
451 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
452 if (channels == channel_allocations[i].channels &&
453 (spk_mask & channel_allocations[i].spk_mask) ==
454 channel_allocations[i].spk_mask) {
455 ca = channel_allocations[i].ca_index;
456 break;
457 }
458 }
459
460 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
461
462 return ca;
463 }
464
465 /* from speaker bit mask to ALSA API channel position */
spk_to_chmap(int spk)466 static int spk_to_chmap(int spk)
467 {
468 const struct channel_map_table *t = map_tables;
469
470 for (; t->map; t++) {
471 if (t->spk_mask == spk)
472 return t->map;
473 }
474 return 0;
475 }
476
had_build_channel_allocation_map(struct snd_intelhad * intelhaddata)477 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
478 {
479 int i, c;
480 int spk_mask = 0;
481 struct snd_pcm_chmap_elem *chmap;
482 u8 eld_high, eld_high_mask = 0xF0;
483 u8 high_msb;
484
485 kfree(intelhaddata->chmap->chmap);
486 intelhaddata->chmap->chmap = NULL;
487
488 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
489 if (!chmap)
490 return;
491
492 dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
493 intelhaddata->eld[DRM_ELD_SPEAKER]);
494
495 /* WA: Fix the max channel supported to 8 */
496
497 /*
498 * Sink may support more than 8 channels, if eld_high has more than
499 * one bit set. SOC supports max 8 channels.
500 * Refer eld_speaker_allocation_bits, for sink speaker allocation
501 */
502
503 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
504 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
505 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
506 /* eld_high & (eld_high-1): if more than 1 bit set */
507 /* 0x1F: 7 channels */
508 for (i = 1; i < 4; i++) {
509 high_msb = eld_high & (0x80 >> i);
510 if (high_msb) {
511 intelhaddata->eld[DRM_ELD_SPEAKER] &=
512 high_msb | 0xF;
513 break;
514 }
515 }
516 }
517
518 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
519 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
520 spk_mask |= eld_speaker_allocation_bits[i];
521 }
522
523 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
524 if (spk_mask == channel_allocations[i].spk_mask) {
525 for (c = 0; c < channel_allocations[i].channels; c++) {
526 chmap->map[c] = spk_to_chmap(
527 channel_allocations[i].speakers[
528 (MAX_SPEAKERS - 1) - c]);
529 }
530 chmap->channels = channel_allocations[i].channels;
531 intelhaddata->chmap->chmap = chmap;
532 break;
533 }
534 }
535 if (i >= ARRAY_SIZE(channel_allocations))
536 kfree(chmap);
537 }
538
539 /*
540 * ALSA API channel-map control callbacks
541 */
had_chmap_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)542 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
543 struct snd_ctl_elem_info *uinfo)
544 {
545 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
546 uinfo->count = HAD_MAX_CHANNEL;
547 uinfo->value.integer.min = 0;
548 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
549 return 0;
550 }
551
had_chmap_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)552 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
553 struct snd_ctl_elem_value *ucontrol)
554 {
555 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
556 struct snd_intelhad *intelhaddata = info->private_data;
557 int i;
558 const struct snd_pcm_chmap_elem *chmap;
559
560 memset(ucontrol->value.integer.value, 0,
561 sizeof(long) * HAD_MAX_CHANNEL);
562 mutex_lock(&intelhaddata->mutex);
563 if (!intelhaddata->chmap->chmap) {
564 mutex_unlock(&intelhaddata->mutex);
565 return 0;
566 }
567
568 chmap = intelhaddata->chmap->chmap;
569 for (i = 0; i < chmap->channels; i++)
570 ucontrol->value.integer.value[i] = chmap->map[i];
571 mutex_unlock(&intelhaddata->mutex);
572
573 return 0;
574 }
575
had_register_chmap_ctls(struct snd_intelhad * intelhaddata,struct snd_pcm * pcm)576 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
577 struct snd_pcm *pcm)
578 {
579 int err;
580
581 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
582 NULL, 0, (unsigned long)intelhaddata,
583 &intelhaddata->chmap);
584 if (err < 0)
585 return err;
586
587 intelhaddata->chmap->private_data = intelhaddata;
588 intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
589 intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
590 intelhaddata->chmap->chmap = NULL;
591 return 0;
592 }
593
594 /*
595 * Initialize Data Island Packets registers
596 * This function is called in the prepare callback
597 */
had_prog_dip(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)598 static void had_prog_dip(struct snd_pcm_substream *substream,
599 struct snd_intelhad *intelhaddata)
600 {
601 int i;
602 union aud_ctrl_st ctrl_state = {.regval = 0};
603 union aud_info_frame2 frame2 = {.regval = 0};
604 union aud_info_frame3 frame3 = {.regval = 0};
605 u8 checksum = 0;
606 u32 info_frame;
607 int channels;
608 int ca;
609
610 channels = substream->runtime->channels;
611
612 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
613
614 ca = had_channel_allocation(intelhaddata, channels);
615 if (intelhaddata->dp_output) {
616 info_frame = DP_INFO_FRAME_WORD1;
617 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
618 } else {
619 info_frame = HDMI_INFO_FRAME_WORD1;
620 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
621 frame3.regx.chnl_alloc = ca;
622
623 /* Calculte the byte wide checksum for all valid DIP words */
624 for (i = 0; i < BYTES_PER_WORD; i++)
625 checksum += (info_frame >> (i * 8)) & 0xff;
626 for (i = 0; i < BYTES_PER_WORD; i++)
627 checksum += (frame2.regval >> (i * 8)) & 0xff;
628 for (i = 0; i < BYTES_PER_WORD; i++)
629 checksum += (frame3.regval >> (i * 8)) & 0xff;
630
631 frame2.regx.chksum = -(checksum);
632 }
633
634 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
635 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
636 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
637
638 /* program remaining DIP words with zero */
639 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
640 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
641
642 ctrl_state.regx.dip_freq = 1;
643 ctrl_state.regx.dip_en_sta = 1;
644 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
645 }
646
had_calculate_maud_value(u32 aud_samp_freq,u32 link_rate)647 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
648 {
649 u32 maud_val;
650
651 /* Select maud according to DP 1.2 spec */
652 if (link_rate == DP_2_7_GHZ) {
653 switch (aud_samp_freq) {
654 case AUD_SAMPLE_RATE_32:
655 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
656 break;
657
658 case AUD_SAMPLE_RATE_44_1:
659 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
660 break;
661
662 case AUD_SAMPLE_RATE_48:
663 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
664 break;
665
666 case AUD_SAMPLE_RATE_88_2:
667 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
668 break;
669
670 case AUD_SAMPLE_RATE_96:
671 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
672 break;
673
674 case AUD_SAMPLE_RATE_176_4:
675 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
676 break;
677
678 case HAD_MAX_RATE:
679 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
680 break;
681
682 default:
683 maud_val = -EINVAL;
684 break;
685 }
686 } else if (link_rate == DP_1_62_GHZ) {
687 switch (aud_samp_freq) {
688 case AUD_SAMPLE_RATE_32:
689 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
690 break;
691
692 case AUD_SAMPLE_RATE_44_1:
693 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
694 break;
695
696 case AUD_SAMPLE_RATE_48:
697 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
698 break;
699
700 case AUD_SAMPLE_RATE_88_2:
701 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
702 break;
703
704 case AUD_SAMPLE_RATE_96:
705 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
706 break;
707
708 case AUD_SAMPLE_RATE_176_4:
709 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
710 break;
711
712 case HAD_MAX_RATE:
713 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
714 break;
715
716 default:
717 maud_val = -EINVAL;
718 break;
719 }
720 } else
721 maud_val = -EINVAL;
722
723 return maud_val;
724 }
725
726 /*
727 * Program HDMI audio CTS value
728 *
729 * @aud_samp_freq: sampling frequency of audio data
730 * @tmds: sampling frequency of the display data
731 * @link_rate: DP link rate
732 * @n_param: N value, depends on aud_samp_freq
733 * @intelhaddata: substream private data
734 *
735 * Program CTS register based on the audio and display sampling frequency
736 */
had_prog_cts(u32 aud_samp_freq,u32 tmds,u32 link_rate,u32 n_param,struct snd_intelhad * intelhaddata)737 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
738 u32 n_param, struct snd_intelhad *intelhaddata)
739 {
740 u32 cts_val;
741 u64 dividend, divisor;
742
743 if (intelhaddata->dp_output) {
744 /* Substitute cts_val with Maud according to DP 1.2 spec*/
745 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
746 } else {
747 /* Calculate CTS according to HDMI 1.3a spec*/
748 dividend = (u64)tmds * n_param*1000;
749 divisor = 128 * aud_samp_freq;
750 cts_val = div64_u64(dividend, divisor);
751 }
752 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
753 tmds, n_param, cts_val);
754 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
755 }
756
had_calculate_n_value(u32 aud_samp_freq)757 static int had_calculate_n_value(u32 aud_samp_freq)
758 {
759 int n_val;
760
761 /* Select N according to HDMI 1.3a spec*/
762 switch (aud_samp_freq) {
763 case AUD_SAMPLE_RATE_32:
764 n_val = 4096;
765 break;
766
767 case AUD_SAMPLE_RATE_44_1:
768 n_val = 6272;
769 break;
770
771 case AUD_SAMPLE_RATE_48:
772 n_val = 6144;
773 break;
774
775 case AUD_SAMPLE_RATE_88_2:
776 n_val = 12544;
777 break;
778
779 case AUD_SAMPLE_RATE_96:
780 n_val = 12288;
781 break;
782
783 case AUD_SAMPLE_RATE_176_4:
784 n_val = 25088;
785 break;
786
787 case HAD_MAX_RATE:
788 n_val = 24576;
789 break;
790
791 default:
792 n_val = -EINVAL;
793 break;
794 }
795 return n_val;
796 }
797
798 /*
799 * Program HDMI audio N value
800 *
801 * @aud_samp_freq: sampling frequency of audio data
802 * @n_param: N value, depends on aud_samp_freq
803 * @intelhaddata: substream private data
804 *
805 * This function is called in the prepare callback.
806 * It programs based on the audio and display sampling frequency
807 */
had_prog_n(u32 aud_samp_freq,u32 * n_param,struct snd_intelhad * intelhaddata)808 static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
809 struct snd_intelhad *intelhaddata)
810 {
811 int n_val;
812
813 if (intelhaddata->dp_output) {
814 /*
815 * According to DP specs, Maud and Naud values hold
816 * a relationship, which is stated as:
817 * Maud/Naud = 512 * fs / f_LS_Clk
818 * where, fs is the sampling frequency of the audio stream
819 * and Naud is 32768 for Async clock.
820 */
821
822 n_val = DP_NAUD_VAL;
823 } else
824 n_val = had_calculate_n_value(aud_samp_freq);
825
826 if (n_val < 0)
827 return n_val;
828
829 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
830 *n_param = n_val;
831 return 0;
832 }
833
834 /*
835 * PCM ring buffer handling
836 *
837 * The hardware provides a ring buffer with the fixed 4 buffer descriptors
838 * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping
839 * moves at each period elapsed. The below illustrates how it works:
840 *
841 * At time=0
842 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
843 * BD | 0 | 1 | 2 | 3 |
844 *
845 * At time=1 (period elapsed)
846 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
847 * BD | 1 | 2 | 3 | 0 |
848 *
849 * At time=2 (second period elapsed)
850 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
851 * BD | 2 | 3 | 0 | 1 |
852 *
853 * The bd_head field points to the index of the BD to be read. It's also the
854 * position to be filled at next. The pcm_head and the pcm_filled fields
855 * point to the indices of the current position and of the next position to
856 * be filled, respectively. For PCM buffer there are both _head and _filled
857 * because they may be difference when nperiods > 4. For example, in the
858 * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5:
859 *
860 * pcm_head (=1) --v v-- pcm_filled (=5)
861 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
862 * BD | 1 | 2 | 3 | 0 |
863 * bd_head (=1) --^ ^-- next to fill (= bd_head)
864 *
865 * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that
866 * the hardware skips those BDs in the loop.
867 *
868 * An exceptional setup is the case with nperiods=1. Since we have to update
869 * BDs after finishing one BD processing, we'd need at least two BDs, where
870 * both BDs point to the same content, the same address, the same size of the
871 * whole PCM buffer.
872 */
873
874 #define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
875 #define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
876
877 /* Set up a buffer descriptor at the "filled" position */
had_prog_bd(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)878 static void had_prog_bd(struct snd_pcm_substream *substream,
879 struct snd_intelhad *intelhaddata)
880 {
881 int idx = intelhaddata->bd_head;
882 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
883 u32 addr = substream->runtime->dma_addr + ofs;
884
885 addr |= AUD_BUF_VALID;
886 if (!substream->runtime->no_period_wakeup)
887 addr |= AUD_BUF_INTR_EN;
888 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
889 had_write_register(intelhaddata, AUD_BUF_LEN(idx),
890 intelhaddata->period_bytes);
891
892 /* advance the indices to the next */
893 intelhaddata->bd_head++;
894 intelhaddata->bd_head %= intelhaddata->num_bds;
895 intelhaddata->pcmbuf_filled++;
896 intelhaddata->pcmbuf_filled %= substream->runtime->periods;
897 }
898
899 /* invalidate a buffer descriptor with the given index */
had_invalidate_bd(struct snd_intelhad * intelhaddata,int idx)900 static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
901 int idx)
902 {
903 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
904 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
905 }
906
907 /* Initial programming of ring buffer */
had_init_ringbuf(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)908 static void had_init_ringbuf(struct snd_pcm_substream *substream,
909 struct snd_intelhad *intelhaddata)
910 {
911 struct snd_pcm_runtime *runtime = substream->runtime;
912 int i, num_periods;
913
914 num_periods = runtime->periods;
915 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
916 /* set the minimum 2 BDs for num_periods=1 */
917 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U);
918 intelhaddata->period_bytes =
919 frames_to_bytes(runtime, runtime->period_size);
920 WARN_ON(intelhaddata->period_bytes & 0x3f);
921
922 intelhaddata->bd_head = 0;
923 intelhaddata->pcmbuf_head = 0;
924 intelhaddata->pcmbuf_filled = 0;
925
926 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
927 if (i < intelhaddata->num_bds)
928 had_prog_bd(substream, intelhaddata);
929 else /* invalidate the rest */
930 had_invalidate_bd(intelhaddata, i);
931 }
932
933 intelhaddata->bd_head = 0; /* reset at head again before starting */
934 }
935
936 /* process a bd, advance to the next */
had_advance_ringbuf(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)937 static void had_advance_ringbuf(struct snd_pcm_substream *substream,
938 struct snd_intelhad *intelhaddata)
939 {
940 int num_periods = substream->runtime->periods;
941
942 /* reprogram the next buffer */
943 had_prog_bd(substream, intelhaddata);
944
945 /* proceed to next */
946 intelhaddata->pcmbuf_head++;
947 intelhaddata->pcmbuf_head %= num_periods;
948 }
949
950 /* process the current BD(s);
951 * returns the current PCM buffer byte position, or -EPIPE for underrun.
952 */
had_process_ringbuf(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)953 static int had_process_ringbuf(struct snd_pcm_substream *substream,
954 struct snd_intelhad *intelhaddata)
955 {
956 int len, processed;
957 unsigned long flags;
958
959 processed = 0;
960 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
961 for (;;) {
962 /* get the remaining bytes on the buffer */
963 had_read_register(intelhaddata,
964 AUD_BUF_LEN(intelhaddata->bd_head),
965 &len);
966 if (len < 0 || len > intelhaddata->period_bytes) {
967 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
968 len);
969 len = -EPIPE;
970 goto out;
971 }
972
973 if (len > 0) /* OK, this is the current buffer */
974 break;
975
976 /* len=0 => already empty, check the next buffer */
977 if (++processed >= intelhaddata->num_bds) {
978 len = -EPIPE; /* all empty? - report underrun */
979 goto out;
980 }
981 had_advance_ringbuf(substream, intelhaddata);
982 }
983
984 len = intelhaddata->period_bytes - len;
985 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
986 out:
987 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
988 return len;
989 }
990
991 /* called from irq handler */
had_process_buffer_done(struct snd_intelhad * intelhaddata)992 static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
993 {
994 struct snd_pcm_substream *substream;
995
996 substream = had_substream_get(intelhaddata);
997 if (!substream)
998 return; /* no stream? - bail out */
999
1000 if (!intelhaddata->connected) {
1001 snd_pcm_stop_xrun(substream);
1002 goto out; /* disconnected? - bail out */
1003 }
1004
1005 /* process or stop the stream */
1006 if (had_process_ringbuf(substream, intelhaddata) < 0)
1007 snd_pcm_stop_xrun(substream);
1008 else
1009 snd_pcm_period_elapsed(substream);
1010
1011 out:
1012 had_substream_put(intelhaddata);
1013 }
1014
1015 /*
1016 * The interrupt status 'sticky' bits might not be cleared by
1017 * setting '1' to that bit once...
1018 */
wait_clear_underrun_bit(struct snd_intelhad * intelhaddata)1019 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
1020 {
1021 int i;
1022 u32 val;
1023
1024 for (i = 0; i < 100; i++) {
1025 /* clear bit30, 31 AUD_HDMI_STATUS */
1026 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
1027 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN))
1028 return;
1029 udelay(100);
1030 cond_resched();
1031 had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
1032 }
1033 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
1034 }
1035
1036 /* Perform some reset procedure but only when need_reset is set;
1037 * this is called from prepare or hw_free callbacks once after trigger STOP
1038 * or underrun has been processed in order to settle down the h/w state.
1039 */
had_do_reset(struct snd_intelhad * intelhaddata)1040 static void had_do_reset(struct snd_intelhad *intelhaddata)
1041 {
1042 if (!intelhaddata->need_reset || !intelhaddata->connected)
1043 return;
1044
1045 /* Reset buffer pointers */
1046 had_reset_audio(intelhaddata);
1047 wait_clear_underrun_bit(intelhaddata);
1048 intelhaddata->need_reset = false;
1049 }
1050
1051 /* called from irq handler */
had_process_buffer_underrun(struct snd_intelhad * intelhaddata)1052 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1053 {
1054 struct snd_pcm_substream *substream;
1055
1056 /* Report UNDERRUN error to above layers */
1057 substream = had_substream_get(intelhaddata);
1058 if (substream) {
1059 snd_pcm_stop_xrun(substream);
1060 had_substream_put(intelhaddata);
1061 }
1062 intelhaddata->need_reset = true;
1063 }
1064
1065 /*
1066 * ALSA PCM open callback
1067 */
had_pcm_open(struct snd_pcm_substream * substream)1068 static int had_pcm_open(struct snd_pcm_substream *substream)
1069 {
1070 struct snd_intelhad *intelhaddata;
1071 struct snd_pcm_runtime *runtime;
1072 int retval;
1073
1074 intelhaddata = snd_pcm_substream_chip(substream);
1075 runtime = substream->runtime;
1076
1077 pm_runtime_get_sync(intelhaddata->dev);
1078
1079 /* set the runtime hw parameter with local snd_pcm_hardware struct */
1080 runtime->hw = had_pcm_hardware;
1081
1082 retval = snd_pcm_hw_constraint_integer(runtime,
1083 SNDRV_PCM_HW_PARAM_PERIODS);
1084 if (retval < 0)
1085 goto error;
1086
1087 /* Make sure, that the period size is always aligned
1088 * 64byte boundary
1089 */
1090 retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1091 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1092 if (retval < 0)
1093 goto error;
1094
1095 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1096 if (retval < 0)
1097 goto error;
1098
1099 /* expose PCM substream */
1100 spin_lock_irq(&intelhaddata->had_spinlock);
1101 intelhaddata->stream_info.substream = substream;
1102 intelhaddata->stream_info.substream_refcount++;
1103 spin_unlock_irq(&intelhaddata->had_spinlock);
1104
1105 return retval;
1106 error:
1107 pm_runtime_mark_last_busy(intelhaddata->dev);
1108 pm_runtime_put_autosuspend(intelhaddata->dev);
1109 return retval;
1110 }
1111
1112 /*
1113 * ALSA PCM close callback
1114 */
had_pcm_close(struct snd_pcm_substream * substream)1115 static int had_pcm_close(struct snd_pcm_substream *substream)
1116 {
1117 struct snd_intelhad *intelhaddata;
1118
1119 intelhaddata = snd_pcm_substream_chip(substream);
1120
1121 /* unreference and sync with the pending PCM accesses */
1122 spin_lock_irq(&intelhaddata->had_spinlock);
1123 intelhaddata->stream_info.substream = NULL;
1124 intelhaddata->stream_info.substream_refcount--;
1125 while (intelhaddata->stream_info.substream_refcount > 0) {
1126 spin_unlock_irq(&intelhaddata->had_spinlock);
1127 cpu_relax();
1128 spin_lock_irq(&intelhaddata->had_spinlock);
1129 }
1130 spin_unlock_irq(&intelhaddata->had_spinlock);
1131
1132 pm_runtime_mark_last_busy(intelhaddata->dev);
1133 pm_runtime_put_autosuspend(intelhaddata->dev);
1134 return 0;
1135 }
1136
1137 /*
1138 * ALSA PCM hw_params callback
1139 */
had_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)1140 static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1141 struct snd_pcm_hw_params *hw_params)
1142 {
1143 struct snd_intelhad *intelhaddata;
1144 unsigned long addr;
1145 int pages, buf_size, retval;
1146
1147 intelhaddata = snd_pcm_substream_chip(substream);
1148 buf_size = params_buffer_bytes(hw_params);
1149 retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1150 if (retval < 0)
1151 return retval;
1152 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1153 __func__, buf_size);
1154 /* mark the pages as uncached region */
1155 addr = (unsigned long) substream->runtime->dma_area;
1156 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
1157 retval = set_memory_uc(addr, pages);
1158 if (retval) {
1159 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
1160 retval);
1161 return retval;
1162 }
1163 memset(substream->runtime->dma_area, 0, buf_size);
1164
1165 return retval;
1166 }
1167
1168 /*
1169 * ALSA PCM hw_free callback
1170 */
had_pcm_hw_free(struct snd_pcm_substream * substream)1171 static int had_pcm_hw_free(struct snd_pcm_substream *substream)
1172 {
1173 struct snd_intelhad *intelhaddata;
1174 unsigned long addr;
1175 u32 pages;
1176
1177 intelhaddata = snd_pcm_substream_chip(substream);
1178 had_do_reset(intelhaddata);
1179
1180 /* mark back the pages as cached/writeback region before the free */
1181 if (substream->runtime->dma_area != NULL) {
1182 addr = (unsigned long) substream->runtime->dma_area;
1183 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
1184 PAGE_SIZE;
1185 set_memory_wb(addr, pages);
1186 return snd_pcm_lib_free_pages(substream);
1187 }
1188 return 0;
1189 }
1190
1191 /*
1192 * ALSA PCM trigger callback
1193 */
had_pcm_trigger(struct snd_pcm_substream * substream,int cmd)1194 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1195 {
1196 int retval = 0;
1197 struct snd_intelhad *intelhaddata;
1198
1199 intelhaddata = snd_pcm_substream_chip(substream);
1200
1201 spin_lock(&intelhaddata->had_spinlock);
1202 switch (cmd) {
1203 case SNDRV_PCM_TRIGGER_START:
1204 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1205 case SNDRV_PCM_TRIGGER_RESUME:
1206 /* Enable Audio */
1207 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */
1208 had_enable_audio(intelhaddata, true);
1209 break;
1210
1211 case SNDRV_PCM_TRIGGER_STOP:
1212 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1213 /* Disable Audio */
1214 had_enable_audio(intelhaddata, false);
1215 intelhaddata->need_reset = true;
1216 break;
1217
1218 default:
1219 retval = -EINVAL;
1220 }
1221 spin_unlock(&intelhaddata->had_spinlock);
1222 return retval;
1223 }
1224
1225 /*
1226 * ALSA PCM prepare callback
1227 */
had_pcm_prepare(struct snd_pcm_substream * substream)1228 static int had_pcm_prepare(struct snd_pcm_substream *substream)
1229 {
1230 int retval;
1231 u32 disp_samp_freq, n_param;
1232 u32 link_rate = 0;
1233 struct snd_intelhad *intelhaddata;
1234 struct snd_pcm_runtime *runtime;
1235
1236 intelhaddata = snd_pcm_substream_chip(substream);
1237 runtime = substream->runtime;
1238
1239 dev_dbg(intelhaddata->dev, "period_size=%d\n",
1240 (int)frames_to_bytes(runtime, runtime->period_size));
1241 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1242 dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1243 (int)snd_pcm_lib_buffer_bytes(substream));
1244 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1245 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
1246
1247 had_do_reset(intelhaddata);
1248
1249 /* Get N value in KHz */
1250 disp_samp_freq = intelhaddata->tmds_clock_speed;
1251
1252 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1253 if (retval) {
1254 dev_err(intelhaddata->dev,
1255 "programming N value failed %#x\n", retval);
1256 goto prep_end;
1257 }
1258
1259 if (intelhaddata->dp_output)
1260 link_rate = intelhaddata->link_rate;
1261
1262 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1263 n_param, intelhaddata);
1264
1265 had_prog_dip(substream, intelhaddata);
1266
1267 retval = had_init_audio_ctrl(substream, intelhaddata);
1268
1269 /* Prog buffer address */
1270 had_init_ringbuf(substream, intelhaddata);
1271
1272 /*
1273 * Program channel mapping in following order:
1274 * FL, FR, C, LFE, RL, RR
1275 */
1276
1277 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
1278
1279 prep_end:
1280 return retval;
1281 }
1282
1283 /*
1284 * ALSA PCM pointer callback
1285 */
had_pcm_pointer(struct snd_pcm_substream * substream)1286 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
1287 {
1288 struct snd_intelhad *intelhaddata;
1289 int len;
1290
1291 intelhaddata = snd_pcm_substream_chip(substream);
1292
1293 if (!intelhaddata->connected)
1294 return SNDRV_PCM_POS_XRUN;
1295
1296 len = had_process_ringbuf(substream, intelhaddata);
1297 if (len < 0)
1298 return SNDRV_PCM_POS_XRUN;
1299 len = bytes_to_frames(substream->runtime, len);
1300 /* wrapping may happen when periods=1 */
1301 len %= substream->runtime->buffer_size;
1302 return len;
1303 }
1304
1305 /*
1306 * ALSA PCM mmap callback
1307 */
had_pcm_mmap(struct snd_pcm_substream * substream,struct vm_area_struct * vma)1308 static int had_pcm_mmap(struct snd_pcm_substream *substream,
1309 struct vm_area_struct *vma)
1310 {
1311 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1312 return remap_pfn_range(vma, vma->vm_start,
1313 substream->dma_buffer.addr >> PAGE_SHIFT,
1314 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1315 }
1316
1317 /*
1318 * ALSA PCM ops
1319 */
1320 static const struct snd_pcm_ops had_pcm_ops = {
1321 .open = had_pcm_open,
1322 .close = had_pcm_close,
1323 .ioctl = snd_pcm_lib_ioctl,
1324 .hw_params = had_pcm_hw_params,
1325 .hw_free = had_pcm_hw_free,
1326 .prepare = had_pcm_prepare,
1327 .trigger = had_pcm_trigger,
1328 .pointer = had_pcm_pointer,
1329 .mmap = had_pcm_mmap,
1330 };
1331
1332 /* process mode change of the running stream; called in mutex */
had_process_mode_change(struct snd_intelhad * intelhaddata)1333 static int had_process_mode_change(struct snd_intelhad *intelhaddata)
1334 {
1335 struct snd_pcm_substream *substream;
1336 int retval = 0;
1337 u32 disp_samp_freq, n_param;
1338 u32 link_rate = 0;
1339
1340 substream = had_substream_get(intelhaddata);
1341 if (!substream)
1342 return 0;
1343
1344 /* Disable Audio */
1345 had_enable_audio(intelhaddata, false);
1346
1347 /* Update CTS value */
1348 disp_samp_freq = intelhaddata->tmds_clock_speed;
1349
1350 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1351 if (retval) {
1352 dev_err(intelhaddata->dev,
1353 "programming N value failed %#x\n", retval);
1354 goto out;
1355 }
1356
1357 if (intelhaddata->dp_output)
1358 link_rate = intelhaddata->link_rate;
1359
1360 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1361 n_param, intelhaddata);
1362
1363 /* Enable Audio */
1364 had_enable_audio(intelhaddata, true);
1365
1366 out:
1367 had_substream_put(intelhaddata);
1368 return retval;
1369 }
1370
1371 /* process hot plug, called from wq with mutex locked */
had_process_hot_plug(struct snd_intelhad * intelhaddata)1372 static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
1373 {
1374 struct snd_pcm_substream *substream;
1375
1376 spin_lock_irq(&intelhaddata->had_spinlock);
1377 if (intelhaddata->connected) {
1378 dev_dbg(intelhaddata->dev, "Device already connected\n");
1379 spin_unlock_irq(&intelhaddata->had_spinlock);
1380 return;
1381 }
1382
1383 /* Disable Audio */
1384 had_enable_audio(intelhaddata, false);
1385
1386 intelhaddata->connected = true;
1387 dev_dbg(intelhaddata->dev,
1388 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1389 __func__, __LINE__);
1390 spin_unlock_irq(&intelhaddata->had_spinlock);
1391
1392 had_build_channel_allocation_map(intelhaddata);
1393
1394 /* Report to above ALSA layer */
1395 substream = had_substream_get(intelhaddata);
1396 if (substream) {
1397 snd_pcm_stop_xrun(substream);
1398 had_substream_put(intelhaddata);
1399 }
1400
1401 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT);
1402 }
1403
1404 /* process hot unplug, called from wq with mutex locked */
had_process_hot_unplug(struct snd_intelhad * intelhaddata)1405 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1406 {
1407 struct snd_pcm_substream *substream;
1408
1409 spin_lock_irq(&intelhaddata->had_spinlock);
1410 if (!intelhaddata->connected) {
1411 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
1412 spin_unlock_irq(&intelhaddata->had_spinlock);
1413 return;
1414
1415 }
1416
1417 /* Disable Audio */
1418 had_enable_audio(intelhaddata, false);
1419
1420 intelhaddata->connected = false;
1421 dev_dbg(intelhaddata->dev,
1422 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
1423 __func__, __LINE__);
1424 spin_unlock_irq(&intelhaddata->had_spinlock);
1425
1426 kfree(intelhaddata->chmap->chmap);
1427 intelhaddata->chmap->chmap = NULL;
1428
1429 /* Report to above ALSA layer */
1430 substream = had_substream_get(intelhaddata);
1431 if (substream) {
1432 snd_pcm_stop_xrun(substream);
1433 had_substream_put(intelhaddata);
1434 }
1435
1436 snd_jack_report(intelhaddata->jack, 0);
1437 }
1438
1439 /*
1440 * ALSA iec958 and ELD controls
1441 */
1442
had_iec958_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1443 static int had_iec958_info(struct snd_kcontrol *kcontrol,
1444 struct snd_ctl_elem_info *uinfo)
1445 {
1446 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1447 uinfo->count = 1;
1448 return 0;
1449 }
1450
had_iec958_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1451 static int had_iec958_get(struct snd_kcontrol *kcontrol,
1452 struct snd_ctl_elem_value *ucontrol)
1453 {
1454 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1455
1456 mutex_lock(&intelhaddata->mutex);
1457 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1458 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1459 ucontrol->value.iec958.status[2] =
1460 (intelhaddata->aes_bits >> 16) & 0xff;
1461 ucontrol->value.iec958.status[3] =
1462 (intelhaddata->aes_bits >> 24) & 0xff;
1463 mutex_unlock(&intelhaddata->mutex);
1464 return 0;
1465 }
1466
had_iec958_mask_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1467 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1468 struct snd_ctl_elem_value *ucontrol)
1469 {
1470 ucontrol->value.iec958.status[0] = 0xff;
1471 ucontrol->value.iec958.status[1] = 0xff;
1472 ucontrol->value.iec958.status[2] = 0xff;
1473 ucontrol->value.iec958.status[3] = 0xff;
1474 return 0;
1475 }
1476
had_iec958_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1477 static int had_iec958_put(struct snd_kcontrol *kcontrol,
1478 struct snd_ctl_elem_value *ucontrol)
1479 {
1480 unsigned int val;
1481 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1482 int changed = 0;
1483
1484 val = (ucontrol->value.iec958.status[0] << 0) |
1485 (ucontrol->value.iec958.status[1] << 8) |
1486 (ucontrol->value.iec958.status[2] << 16) |
1487 (ucontrol->value.iec958.status[3] << 24);
1488 mutex_lock(&intelhaddata->mutex);
1489 if (intelhaddata->aes_bits != val) {
1490 intelhaddata->aes_bits = val;
1491 changed = 1;
1492 }
1493 mutex_unlock(&intelhaddata->mutex);
1494 return changed;
1495 }
1496
had_ctl_eld_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1497 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1498 struct snd_ctl_elem_info *uinfo)
1499 {
1500 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1501 uinfo->count = HDMI_MAX_ELD_BYTES;
1502 return 0;
1503 }
1504
had_ctl_eld_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1505 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1506 struct snd_ctl_elem_value *ucontrol)
1507 {
1508 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1509
1510 mutex_lock(&intelhaddata->mutex);
1511 memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1512 HDMI_MAX_ELD_BYTES);
1513 mutex_unlock(&intelhaddata->mutex);
1514 return 0;
1515 }
1516
1517 static const struct snd_kcontrol_new had_controls[] = {
1518 {
1519 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1520 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1521 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1522 .info = had_iec958_info, /* shared */
1523 .get = had_iec958_mask_get,
1524 },
1525 {
1526 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1527 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1528 .info = had_iec958_info,
1529 .get = had_iec958_get,
1530 .put = had_iec958_put,
1531 },
1532 {
1533 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1534 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1535 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1536 .name = "ELD",
1537 .info = had_ctl_eld_info,
1538 .get = had_ctl_eld_get,
1539 },
1540 };
1541
1542 /*
1543 * audio interrupt handler
1544 */
display_pipe_interrupt_handler(int irq,void * dev_id)1545 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1546 {
1547 struct snd_intelhad_card *card_ctx = dev_id;
1548 u32 audio_stat[3] = {};
1549 int pipe, port;
1550
1551 for_each_pipe(card_ctx, pipe) {
1552 /* use raw register access to ack IRQs even while disconnected */
1553 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe,
1554 AUD_HDMI_STATUS) &
1555 (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE);
1556
1557 if (audio_stat[pipe])
1558 had_write_register_raw(card_ctx, pipe,
1559 AUD_HDMI_STATUS, audio_stat[pipe]);
1560 }
1561
1562 for_each_port(card_ctx, port) {
1563 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1564 int pipe = ctx->pipe;
1565
1566 if (pipe < 0)
1567 continue;
1568
1569 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE)
1570 had_process_buffer_done(ctx);
1571 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN)
1572 had_process_buffer_underrun(ctx);
1573 }
1574
1575 return IRQ_HANDLED;
1576 }
1577
1578 /*
1579 * monitor plug/unplug notification from i915; just kick off the work
1580 */
notify_audio_lpe(struct platform_device * pdev,int port)1581 static void notify_audio_lpe(struct platform_device *pdev, int port)
1582 {
1583 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1584 struct snd_intelhad *ctx;
1585
1586 ctx = &card_ctx->pcm_ctx[single_port ? 0 : port];
1587 if (single_port)
1588 ctx->port = port;
1589
1590 schedule_work(&ctx->hdmi_audio_wq);
1591 }
1592
1593 /* the work to handle monitor hot plug/unplug */
had_audio_wq(struct work_struct * work)1594 static void had_audio_wq(struct work_struct *work)
1595 {
1596 struct snd_intelhad *ctx =
1597 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1598 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
1599 struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port];
1600
1601 pm_runtime_get_sync(ctx->dev);
1602 mutex_lock(&ctx->mutex);
1603 if (ppdata->pipe < 0) {
1604 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n",
1605 __func__, ctx->port);
1606
1607 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
1608
1609 ctx->dp_output = false;
1610 ctx->tmds_clock_speed = 0;
1611 ctx->link_rate = 0;
1612
1613 /* Shut down the stream */
1614 had_process_hot_unplug(ctx);
1615
1616 ctx->pipe = -1;
1617 } else {
1618 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1619 __func__, ctx->port, ppdata->ls_clock);
1620
1621 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld));
1622
1623 ctx->dp_output = ppdata->dp_output;
1624 if (ctx->dp_output) {
1625 ctx->tmds_clock_speed = 0;
1626 ctx->link_rate = ppdata->ls_clock;
1627 } else {
1628 ctx->tmds_clock_speed = ppdata->ls_clock;
1629 ctx->link_rate = 0;
1630 }
1631
1632 /*
1633 * Shut down the stream before we change
1634 * the pipe assignment for this pcm device
1635 */
1636 had_process_hot_plug(ctx);
1637
1638 ctx->pipe = ppdata->pipe;
1639
1640 /* Restart the stream if necessary */
1641 had_process_mode_change(ctx);
1642 }
1643
1644 mutex_unlock(&ctx->mutex);
1645 pm_runtime_mark_last_busy(ctx->dev);
1646 pm_runtime_put_autosuspend(ctx->dev);
1647 }
1648
1649 /*
1650 * Jack interface
1651 */
had_create_jack(struct snd_intelhad * ctx,struct snd_pcm * pcm)1652 static int had_create_jack(struct snd_intelhad *ctx,
1653 struct snd_pcm *pcm)
1654 {
1655 char hdmi_str[32];
1656 int err;
1657
1658 snprintf(hdmi_str, sizeof(hdmi_str),
1659 "HDMI/DP,pcm=%d", pcm->device);
1660
1661 err = snd_jack_new(ctx->card_ctx->card, hdmi_str,
1662 SND_JACK_AVOUT, &ctx->jack,
1663 true, false);
1664 if (err < 0)
1665 return err;
1666 ctx->jack->private_data = ctx;
1667 return 0;
1668 }
1669
1670 /*
1671 * PM callbacks
1672 */
1673
hdmi_lpe_audio_runtime_suspend(struct device * dev)1674 static int hdmi_lpe_audio_runtime_suspend(struct device *dev)
1675 {
1676 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1677 int port;
1678
1679 for_each_port(card_ctx, port) {
1680 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1681 struct snd_pcm_substream *substream;
1682
1683 substream = had_substream_get(ctx);
1684 if (substream) {
1685 snd_pcm_suspend(substream);
1686 had_substream_put(ctx);
1687 }
1688 }
1689
1690 return 0;
1691 }
1692
hdmi_lpe_audio_suspend(struct device * dev)1693 static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev)
1694 {
1695 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1696 int err;
1697
1698 err = hdmi_lpe_audio_runtime_suspend(dev);
1699 if (!err)
1700 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot);
1701 return err;
1702 }
1703
hdmi_lpe_audio_runtime_resume(struct device * dev)1704 static int hdmi_lpe_audio_runtime_resume(struct device *dev)
1705 {
1706 pm_runtime_mark_last_busy(dev);
1707 return 0;
1708 }
1709
hdmi_lpe_audio_resume(struct device * dev)1710 static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev)
1711 {
1712 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1713
1714 hdmi_lpe_audio_runtime_resume(dev);
1715 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0);
1716 return 0;
1717 }
1718
1719 /* release resources */
hdmi_lpe_audio_free(struct snd_card * card)1720 static void hdmi_lpe_audio_free(struct snd_card *card)
1721 {
1722 struct snd_intelhad_card *card_ctx = card->private_data;
1723 struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data;
1724 int port;
1725
1726 spin_lock_irq(&pdata->lpe_audio_slock);
1727 pdata->notify_audio_lpe = NULL;
1728 spin_unlock_irq(&pdata->lpe_audio_slock);
1729
1730 for_each_port(card_ctx, port) {
1731 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1732
1733 cancel_work_sync(&ctx->hdmi_audio_wq);
1734 }
1735
1736 if (card_ctx->mmio_start)
1737 iounmap(card_ctx->mmio_start);
1738 if (card_ctx->irq >= 0)
1739 free_irq(card_ctx->irq, card_ctx);
1740 }
1741
1742 /*
1743 * hdmi_lpe_audio_probe - start bridge with i915
1744 *
1745 * This function is called when the i915 driver creates the
1746 * hdmi-lpe-audio platform device.
1747 */
hdmi_lpe_audio_probe(struct platform_device * pdev)1748 static int hdmi_lpe_audio_probe(struct platform_device *pdev)
1749 {
1750 struct snd_card *card;
1751 struct snd_intelhad_card *card_ctx;
1752 struct snd_intelhad *ctx;
1753 struct snd_pcm *pcm;
1754 struct intel_hdmi_lpe_audio_pdata *pdata;
1755 int irq;
1756 struct resource *res_mmio;
1757 int port, ret;
1758
1759 pdata = pdev->dev.platform_data;
1760 if (!pdata) {
1761 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1762 return -EINVAL;
1763 }
1764
1765 /* get resources */
1766 irq = platform_get_irq(pdev, 0);
1767 if (irq < 0) {
1768 dev_err(&pdev->dev, "Could not get irq resource: %d\n", irq);
1769 return irq;
1770 }
1771
1772 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1773 if (!res_mmio) {
1774 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1775 return -ENXIO;
1776 }
1777
1778 /* create a card instance with ALSA framework */
1779 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1780 THIS_MODULE, sizeof(*card_ctx), &card);
1781 if (ret)
1782 return ret;
1783
1784 card_ctx = card->private_data;
1785 card_ctx->dev = &pdev->dev;
1786 card_ctx->card = card;
1787 strcpy(card->driver, INTEL_HAD);
1788 strcpy(card->shortname, "Intel HDMI/DP LPE Audio");
1789 strcpy(card->longname, "Intel HDMI/DP LPE Audio");
1790
1791 card_ctx->irq = -1;
1792
1793 card->private_free = hdmi_lpe_audio_free;
1794
1795 platform_set_drvdata(pdev, card_ctx);
1796
1797 card_ctx->num_pipes = pdata->num_pipes;
1798 card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1799
1800 for_each_port(card_ctx, port) {
1801 ctx = &card_ctx->pcm_ctx[port];
1802 ctx->card_ctx = card_ctx;
1803 ctx->dev = card_ctx->dev;
1804 ctx->port = single_port ? -1 : port;
1805 ctx->pipe = -1;
1806
1807 spin_lock_init(&ctx->had_spinlock);
1808 mutex_init(&ctx->mutex);
1809 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
1810 }
1811
1812 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1813 __func__, (unsigned int)res_mmio->start,
1814 (unsigned int)res_mmio->end);
1815
1816 card_ctx->mmio_start = ioremap_nocache(res_mmio->start,
1817 (size_t)(resource_size(res_mmio)));
1818 if (!card_ctx->mmio_start) {
1819 dev_err(&pdev->dev, "Could not get ioremap\n");
1820 ret = -EACCES;
1821 goto err;
1822 }
1823
1824 /* setup interrupt handler */
1825 ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1826 pdev->name, card_ctx);
1827 if (ret < 0) {
1828 dev_err(&pdev->dev, "request_irq failed\n");
1829 goto err;
1830 }
1831
1832 card_ctx->irq = irq;
1833
1834 /* only 32bit addressable */
1835 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1836 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1837
1838 init_channel_allocations();
1839
1840 card_ctx->num_pipes = pdata->num_pipes;
1841 card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1842
1843 for_each_port(card_ctx, port) {
1844 int i;
1845
1846 ctx = &card_ctx->pcm_ctx[port];
1847 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS,
1848 MAX_CAP_STREAMS, &pcm);
1849 if (ret)
1850 goto err;
1851
1852 /* setup private data which can be retrieved when required */
1853 pcm->private_data = ctx;
1854 pcm->info_flags = 0;
1855 strlcpy(pcm->name, card->shortname, strlen(card->shortname));
1856 /* setup the ops for playabck */
1857 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
1858
1859 /* allocate dma pages;
1860 * try to allocate 600k buffer as default which is large enough
1861 */
1862 snd_pcm_lib_preallocate_pages_for_all(pcm,
1863 SNDRV_DMA_TYPE_DEV, NULL,
1864 HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER);
1865
1866 /* create controls */
1867 for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1868 struct snd_kcontrol *kctl;
1869
1870 kctl = snd_ctl_new1(&had_controls[i], ctx);
1871 if (!kctl) {
1872 ret = -ENOMEM;
1873 goto err;
1874 }
1875
1876 kctl->id.device = pcm->device;
1877
1878 ret = snd_ctl_add(card, kctl);
1879 if (ret < 0)
1880 goto err;
1881 }
1882
1883 /* Register channel map controls */
1884 ret = had_register_chmap_ctls(ctx, pcm);
1885 if (ret < 0)
1886 goto err;
1887
1888 ret = had_create_jack(ctx, pcm);
1889 if (ret < 0)
1890 goto err;
1891 }
1892
1893 ret = snd_card_register(card);
1894 if (ret)
1895 goto err;
1896
1897 spin_lock_irq(&pdata->lpe_audio_slock);
1898 pdata->notify_audio_lpe = notify_audio_lpe;
1899 spin_unlock_irq(&pdata->lpe_audio_slock);
1900
1901 pm_runtime_use_autosuspend(&pdev->dev);
1902 pm_runtime_mark_last_busy(&pdev->dev);
1903 pm_runtime_set_active(&pdev->dev);
1904
1905 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1906 for_each_port(card_ctx, port) {
1907 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1908
1909 schedule_work(&ctx->hdmi_audio_wq);
1910 }
1911
1912 return 0;
1913
1914 err:
1915 snd_card_free(card);
1916 return ret;
1917 }
1918
1919 /*
1920 * hdmi_lpe_audio_remove - stop bridge with i915
1921 *
1922 * This function is called when the platform device is destroyed.
1923 */
hdmi_lpe_audio_remove(struct platform_device * pdev)1924 static int hdmi_lpe_audio_remove(struct platform_device *pdev)
1925 {
1926 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1927
1928 snd_card_free(card_ctx->card);
1929 return 0;
1930 }
1931
1932 static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1933 SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1934 SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend,
1935 hdmi_lpe_audio_runtime_resume, NULL)
1936 };
1937
1938 static struct platform_driver hdmi_lpe_audio_driver = {
1939 .driver = {
1940 .name = "hdmi-lpe-audio",
1941 .pm = &hdmi_lpe_audio_pm,
1942 },
1943 .probe = hdmi_lpe_audio_probe,
1944 .remove = hdmi_lpe_audio_remove,
1945 };
1946
1947 module_platform_driver(hdmi_lpe_audio_driver);
1948 MODULE_ALIAS("platform:hdmi_lpe_audio");
1949
1950 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1951 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1952 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1953 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1954 MODULE_DESCRIPTION("Intel HDMI Audio driver");
1955 MODULE_LICENSE("GPL v2");
1956 MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");
1957
