1 /*
2 * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
3 *
4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
6 *
7 * License terms: GPL V2.0.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
16 * details.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/regmap.h>
25
26 #include <sound/asoundef.h>
27 #include <sound/core.h>
28 #include <sound/dmaengine_pcm.h>
29 #include <sound/pcm_params.h>
30
31 #include "stm32_sai.h"
32
33 #define SAI_FREE_PROTOCOL 0x0
34 #define SAI_SPDIF_PROTOCOL 0x1
35
36 #define SAI_SLOT_SIZE_AUTO 0x0
37 #define SAI_SLOT_SIZE_16 0x1
38 #define SAI_SLOT_SIZE_32 0x2
39
40 #define SAI_DATASIZE_8 0x2
41 #define SAI_DATASIZE_10 0x3
42 #define SAI_DATASIZE_16 0x4
43 #define SAI_DATASIZE_20 0x5
44 #define SAI_DATASIZE_24 0x6
45 #define SAI_DATASIZE_32 0x7
46
47 #define STM_SAI_FIFO_SIZE 8
48 #define STM_SAI_DAI_NAME_SIZE 15
49
50 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
51 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
52
53 #define STM_SAI_A_ID 0x0
54 #define STM_SAI_B_ID 0x1
55
56 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
57 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID)
58 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B")
59
60 #define SAI_SYNC_NONE 0x0
61 #define SAI_SYNC_INTERNAL 0x1
62 #define SAI_SYNC_EXTERNAL 0x2
63
64 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
65 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf->has_spdif)
66 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
67
68 #define SAI_IEC60958_BLOCK_FRAMES 192
69 #define SAI_IEC60958_STATUS_BYTES 24
70
71 /**
72 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
73 * @pdev: device data pointer
74 * @regmap: SAI register map pointer
75 * @regmap_config: SAI sub block register map configuration pointer
76 * @dma_params: dma configuration data for rx or tx channel
77 * @cpu_dai_drv: DAI driver data pointer
78 * @cpu_dai: DAI runtime data pointer
79 * @substream: PCM substream data pointer
80 * @pdata: SAI block parent data pointer
81 * @np_sync_provider: synchronization provider node
82 * @sai_ck: kernel clock feeding the SAI clock generator
83 * @phys_addr: SAI registers physical base address
84 * @mclk_rate: SAI block master clock frequency (Hz). set at init
85 * @id: SAI sub block id corresponding to sub-block A or B
86 * @dir: SAI block direction (playback or capture). set at init
87 * @master: SAI block mode flag. (true=master, false=slave) set at init
88 * @spdif: SAI S/PDIF iec60958 mode flag. set at init
89 * @fmt: SAI block format. relevant only for custom protocols. set at init
90 * @sync: SAI block synchronization mode. (none, internal or external)
91 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
92 * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
93 * @fs_length: frame synchronization length. depends on protocol settings
94 * @slots: rx or tx slot number
95 * @slot_width: rx or tx slot width in bits
96 * @slot_mask: rx or tx active slots mask. set at init or at runtime
97 * @data_size: PCM data width. corresponds to PCM substream width.
98 * @spdif_frm_cnt: S/PDIF playback frame counter
99 * @snd_aes_iec958: iec958 data
100 * @ctrl_lock: control lock
101 */
102 struct stm32_sai_sub_data {
103 struct platform_device *pdev;
104 struct regmap *regmap;
105 const struct regmap_config *regmap_config;
106 struct snd_dmaengine_dai_dma_data dma_params;
107 struct snd_soc_dai_driver *cpu_dai_drv;
108 struct snd_soc_dai *cpu_dai;
109 struct snd_pcm_substream *substream;
110 struct stm32_sai_data *pdata;
111 struct device_node *np_sync_provider;
112 struct clk *sai_ck;
113 dma_addr_t phys_addr;
114 unsigned int mclk_rate;
115 unsigned int id;
116 int dir;
117 bool master;
118 bool spdif;
119 int fmt;
120 int sync;
121 int synco;
122 int synci;
123 int fs_length;
124 int slots;
125 int slot_width;
126 int slot_mask;
127 int data_size;
128 unsigned int spdif_frm_cnt;
129 struct snd_aes_iec958 iec958;
130 struct mutex ctrl_lock; /* protect resources accessed by controls */
131 };
132
133 enum stm32_sai_fifo_th {
134 STM_SAI_FIFO_TH_EMPTY,
135 STM_SAI_FIFO_TH_QUARTER,
136 STM_SAI_FIFO_TH_HALF,
137 STM_SAI_FIFO_TH_3_QUARTER,
138 STM_SAI_FIFO_TH_FULL,
139 };
140
stm32_sai_sub_readable_reg(struct device * dev,unsigned int reg)141 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
142 {
143 switch (reg) {
144 case STM_SAI_CR1_REGX:
145 case STM_SAI_CR2_REGX:
146 case STM_SAI_FRCR_REGX:
147 case STM_SAI_SLOTR_REGX:
148 case STM_SAI_IMR_REGX:
149 case STM_SAI_SR_REGX:
150 case STM_SAI_CLRFR_REGX:
151 case STM_SAI_DR_REGX:
152 case STM_SAI_PDMCR_REGX:
153 case STM_SAI_PDMLY_REGX:
154 return true;
155 default:
156 return false;
157 }
158 }
159
stm32_sai_sub_volatile_reg(struct device * dev,unsigned int reg)160 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
161 {
162 switch (reg) {
163 case STM_SAI_DR_REGX:
164 return true;
165 default:
166 return false;
167 }
168 }
169
stm32_sai_sub_writeable_reg(struct device * dev,unsigned int reg)170 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
171 {
172 switch (reg) {
173 case STM_SAI_CR1_REGX:
174 case STM_SAI_CR2_REGX:
175 case STM_SAI_FRCR_REGX:
176 case STM_SAI_SLOTR_REGX:
177 case STM_SAI_IMR_REGX:
178 case STM_SAI_SR_REGX:
179 case STM_SAI_CLRFR_REGX:
180 case STM_SAI_DR_REGX:
181 case STM_SAI_PDMCR_REGX:
182 case STM_SAI_PDMLY_REGX:
183 return true;
184 default:
185 return false;
186 }
187 }
188
189 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
190 .reg_bits = 32,
191 .reg_stride = 4,
192 .val_bits = 32,
193 .max_register = STM_SAI_DR_REGX,
194 .readable_reg = stm32_sai_sub_readable_reg,
195 .volatile_reg = stm32_sai_sub_volatile_reg,
196 .writeable_reg = stm32_sai_sub_writeable_reg,
197 .fast_io = true,
198 };
199
200 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
201 .reg_bits = 32,
202 .reg_stride = 4,
203 .val_bits = 32,
204 .max_register = STM_SAI_PDMLY_REGX,
205 .readable_reg = stm32_sai_sub_readable_reg,
206 .volatile_reg = stm32_sai_sub_volatile_reg,
207 .writeable_reg = stm32_sai_sub_writeable_reg,
208 .fast_io = true,
209 };
210
snd_pcm_iec958_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)211 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
212 struct snd_ctl_elem_info *uinfo)
213 {
214 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
215 uinfo->count = 1;
216
217 return 0;
218 }
219
snd_pcm_iec958_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)220 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
221 struct snd_ctl_elem_value *uctl)
222 {
223 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
224
225 mutex_lock(&sai->ctrl_lock);
226 memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
227 mutex_unlock(&sai->ctrl_lock);
228
229 return 0;
230 }
231
snd_pcm_iec958_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)232 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
233 struct snd_ctl_elem_value *uctl)
234 {
235 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
236
237 mutex_lock(&sai->ctrl_lock);
238 memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
239 mutex_unlock(&sai->ctrl_lock);
240
241 return 0;
242 }
243
244 static const struct snd_kcontrol_new iec958_ctls = {
245 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
246 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
247 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
248 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
249 .info = snd_pcm_iec958_info,
250 .get = snd_pcm_iec958_get,
251 .put = snd_pcm_iec958_put,
252 };
253
stm32_sai_isr(int irq,void * devid)254 static irqreturn_t stm32_sai_isr(int irq, void *devid)
255 {
256 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
257 struct platform_device *pdev = sai->pdev;
258 unsigned int sr, imr, flags;
259 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
260
261 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr);
262 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr);
263
264 flags = sr & imr;
265 if (!flags)
266 return IRQ_NONE;
267
268 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
269 SAI_XCLRFR_MASK);
270
271 if (!sai->substream) {
272 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
273 return IRQ_NONE;
274 }
275
276 if (flags & SAI_XIMR_OVRUDRIE) {
277 dev_err(&pdev->dev, "IRQ %s\n",
278 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
279 status = SNDRV_PCM_STATE_XRUN;
280 }
281
282 if (flags & SAI_XIMR_MUTEDETIE)
283 dev_dbg(&pdev->dev, "IRQ mute detected\n");
284
285 if (flags & SAI_XIMR_WCKCFGIE) {
286 dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
287 status = SNDRV_PCM_STATE_DISCONNECTED;
288 }
289
290 if (flags & SAI_XIMR_CNRDYIE)
291 dev_err(&pdev->dev, "IRQ Codec not ready\n");
292
293 if (flags & SAI_XIMR_AFSDETIE) {
294 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
295 status = SNDRV_PCM_STATE_XRUN;
296 }
297
298 if (flags & SAI_XIMR_LFSDETIE) {
299 dev_err(&pdev->dev, "IRQ Late frame synchro\n");
300 status = SNDRV_PCM_STATE_XRUN;
301 }
302
303 if (status != SNDRV_PCM_STATE_RUNNING)
304 snd_pcm_stop_xrun(sai->substream);
305
306 return IRQ_HANDLED;
307 }
308
stm32_sai_set_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)309 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
310 int clk_id, unsigned int freq, int dir)
311 {
312 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
313 int ret;
314
315 if ((dir == SND_SOC_CLOCK_OUT) && sai->master) {
316 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
317 SAI_XCR1_NODIV,
318 (unsigned int)~SAI_XCR1_NODIV);
319 if (ret < 0)
320 return ret;
321
322 sai->mclk_rate = freq;
323 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
324 }
325
326 return 0;
327 }
328
stm32_sai_set_dai_tdm_slot(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)329 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
330 u32 rx_mask, int slots, int slot_width)
331 {
332 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
333 int slotr, slotr_mask, slot_size;
334
335 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
336 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
337 return 0;
338 }
339
340 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
341 tx_mask, rx_mask, slots, slot_width);
342
343 switch (slot_width) {
344 case 16:
345 slot_size = SAI_SLOT_SIZE_16;
346 break;
347 case 32:
348 slot_size = SAI_SLOT_SIZE_32;
349 break;
350 default:
351 slot_size = SAI_SLOT_SIZE_AUTO;
352 break;
353 }
354
355 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
356 SAI_XSLOTR_NBSLOT_SET(slots - 1);
357 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
358
359 /* tx/rx mask set in machine init, if slot number defined in DT */
360 if (STM_SAI_IS_PLAYBACK(sai)) {
361 sai->slot_mask = tx_mask;
362 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
363 }
364
365 if (STM_SAI_IS_CAPTURE(sai)) {
366 sai->slot_mask = rx_mask;
367 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
368 }
369
370 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
371
372 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
373
374 sai->slot_width = slot_width;
375 sai->slots = slots;
376
377 return 0;
378 }
379
stm32_sai_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)380 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
381 {
382 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
383 int cr1, frcr = 0;
384 int cr1_mask, frcr_mask = 0;
385 int ret;
386
387 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
388
389 /* Do not generate master by default */
390 cr1 = SAI_XCR1_NODIV;
391 cr1_mask = SAI_XCR1_NODIV;
392
393 cr1_mask |= SAI_XCR1_PRTCFG_MASK;
394 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
395 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
396 goto conf_update;
397 }
398
399 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
400
401 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
402 /* SCK active high for all protocols */
403 case SND_SOC_DAIFMT_I2S:
404 cr1 |= SAI_XCR1_CKSTR;
405 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
406 break;
407 /* Left justified */
408 case SND_SOC_DAIFMT_MSB:
409 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
410 break;
411 /* Right justified */
412 case SND_SOC_DAIFMT_LSB:
413 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
414 break;
415 case SND_SOC_DAIFMT_DSP_A:
416 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
417 break;
418 case SND_SOC_DAIFMT_DSP_B:
419 frcr |= SAI_XFRCR_FSPOL;
420 break;
421 default:
422 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
423 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
424 return -EINVAL;
425 }
426
427 cr1_mask |= SAI_XCR1_CKSTR;
428 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
429 SAI_XFRCR_FSDEF;
430
431 /* DAI clock strobing. Invert setting previously set */
432 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
433 case SND_SOC_DAIFMT_NB_NF:
434 break;
435 case SND_SOC_DAIFMT_IB_NF:
436 cr1 ^= SAI_XCR1_CKSTR;
437 break;
438 case SND_SOC_DAIFMT_NB_IF:
439 frcr ^= SAI_XFRCR_FSPOL;
440 break;
441 case SND_SOC_DAIFMT_IB_IF:
442 /* Invert fs & sck */
443 cr1 ^= SAI_XCR1_CKSTR;
444 frcr ^= SAI_XFRCR_FSPOL;
445 break;
446 default:
447 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
448 fmt & SND_SOC_DAIFMT_INV_MASK);
449 return -EINVAL;
450 }
451 cr1_mask |= SAI_XCR1_CKSTR;
452 frcr_mask |= SAI_XFRCR_FSPOL;
453
454 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
455
456 /* DAI clock master masks */
457 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
458 case SND_SOC_DAIFMT_CBM_CFM:
459 /* codec is master */
460 cr1 |= SAI_XCR1_SLAVE;
461 sai->master = false;
462 break;
463 case SND_SOC_DAIFMT_CBS_CFS:
464 sai->master = true;
465 break;
466 default:
467 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
468 fmt & SND_SOC_DAIFMT_MASTER_MASK);
469 return -EINVAL;
470 }
471
472 /* Set slave mode if sub-block is synchronized with another SAI */
473 if (sai->sync) {
474 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
475 cr1 |= SAI_XCR1_SLAVE;
476 sai->master = false;
477 }
478
479 cr1_mask |= SAI_XCR1_SLAVE;
480
481 conf_update:
482 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
483 if (ret < 0) {
484 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
485 return ret;
486 }
487
488 sai->fmt = fmt;
489
490 return 0;
491 }
492
stm32_sai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)493 static int stm32_sai_startup(struct snd_pcm_substream *substream,
494 struct snd_soc_dai *cpu_dai)
495 {
496 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
497 int imr, cr2, ret;
498
499 sai->substream = substream;
500
501 ret = clk_prepare_enable(sai->sai_ck);
502 if (ret < 0) {
503 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
504 return ret;
505 }
506
507 /* Enable ITs */
508
509 regmap_update_bits(sai->regmap, STM_SAI_CLRFR_REGX,
510 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
511
512 imr = SAI_XIMR_OVRUDRIE;
513 if (STM_SAI_IS_CAPTURE(sai)) {
514 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2);
515 if (cr2 & SAI_XCR2_MUTECNT_MASK)
516 imr |= SAI_XIMR_MUTEDETIE;
517 }
518
519 if (sai->master)
520 imr |= SAI_XIMR_WCKCFGIE;
521 else
522 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
523
524 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
525 SAI_XIMR_MASK, imr);
526
527 return 0;
528 }
529
stm32_sai_set_config(struct snd_soc_dai * cpu_dai,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)530 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
531 struct snd_pcm_substream *substream,
532 struct snd_pcm_hw_params *params)
533 {
534 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
535 int cr1, cr1_mask, ret;
536
537 /*
538 * DMA bursts increment is set to 4 words.
539 * SAI fifo threshold is set to half fifo, to keep enough space
540 * for DMA incoming bursts.
541 */
542 regmap_update_bits(sai->regmap, STM_SAI_CR2_REGX,
543 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
544 SAI_XCR2_FFLUSH |
545 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
546
547 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
548 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
549 sai->spdif_frm_cnt = 0;
550 return 0;
551 }
552
553 /* Mode, data format and channel config */
554 cr1_mask = SAI_XCR1_DS_MASK;
555 switch (params_format(params)) {
556 case SNDRV_PCM_FORMAT_S8:
557 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
558 break;
559 case SNDRV_PCM_FORMAT_S16_LE:
560 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
561 break;
562 case SNDRV_PCM_FORMAT_S32_LE:
563 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
564 break;
565 default:
566 dev_err(cpu_dai->dev, "Data format not supported");
567 return -EINVAL;
568 }
569
570 cr1_mask |= SAI_XCR1_MONO;
571 if ((sai->slots == 2) && (params_channels(params) == 1))
572 cr1 |= SAI_XCR1_MONO;
573
574 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
575 if (ret < 0) {
576 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
577 return ret;
578 }
579
580 return 0;
581 }
582
stm32_sai_set_slots(struct snd_soc_dai * cpu_dai)583 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
584 {
585 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
586 int slotr, slot_sz;
587
588 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr);
589
590 /*
591 * If SLOTSZ is set to auto in SLOTR, align slot width on data size
592 * By default slot width = data size, if not forced from DT
593 */
594 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
595 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
596 sai->slot_width = sai->data_size;
597
598 if (sai->slot_width < sai->data_size) {
599 dev_err(cpu_dai->dev,
600 "Data size %d larger than slot width\n",
601 sai->data_size);
602 return -EINVAL;
603 }
604
605 /* Slot number is set to 2, if not specified in DT */
606 if (!sai->slots)
607 sai->slots = 2;
608
609 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
610 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
611 SAI_XSLOTR_NBSLOT_MASK,
612 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
613
614 /* Set default slots mask if not already set from DT */
615 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
616 sai->slot_mask = (1 << sai->slots) - 1;
617 regmap_update_bits(sai->regmap,
618 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
619 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
620 }
621
622 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
623 sai->slots, sai->slot_width);
624
625 return 0;
626 }
627
stm32_sai_set_frame(struct snd_soc_dai * cpu_dai)628 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
629 {
630 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
631 int fs_active, offset, format;
632 int frcr, frcr_mask;
633
634 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
635 sai->fs_length = sai->slot_width * sai->slots;
636
637 fs_active = sai->fs_length / 2;
638 if ((format == SND_SOC_DAIFMT_DSP_A) ||
639 (format == SND_SOC_DAIFMT_DSP_B))
640 fs_active = 1;
641
642 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
643 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
644 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
645
646 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
647 sai->fs_length, fs_active);
648
649 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
650
651 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
652 offset = sai->slot_width - sai->data_size;
653
654 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
655 SAI_XSLOTR_FBOFF_MASK,
656 SAI_XSLOTR_FBOFF_SET(offset));
657 }
658 }
659
stm32_sai_init_iec958_status(struct stm32_sai_sub_data * sai)660 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
661 {
662 unsigned char *cs = sai->iec958.status;
663
664 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
665 cs[1] = IEC958_AES1_CON_GENERAL;
666 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
667 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
668 }
669
stm32_sai_set_iec958_status(struct stm32_sai_sub_data * sai,struct snd_pcm_runtime * runtime)670 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
671 struct snd_pcm_runtime *runtime)
672 {
673 if (!runtime)
674 return;
675
676 /* Force the sample rate according to runtime rate */
677 mutex_lock(&sai->ctrl_lock);
678 switch (runtime->rate) {
679 case 22050:
680 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
681 break;
682 case 44100:
683 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
684 break;
685 case 88200:
686 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
687 break;
688 case 176400:
689 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
690 break;
691 case 24000:
692 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
693 break;
694 case 48000:
695 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
696 break;
697 case 96000:
698 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
699 break;
700 case 192000:
701 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
702 break;
703 case 32000:
704 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
705 break;
706 default:
707 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
708 break;
709 }
710 mutex_unlock(&sai->ctrl_lock);
711 }
712
stm32_sai_configure_clock(struct snd_soc_dai * cpu_dai,struct snd_pcm_hw_params * params)713 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
714 struct snd_pcm_hw_params *params)
715 {
716 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
717 int cr1, mask, div = 0;
718 int sai_clk_rate, mclk_ratio, den, ret;
719 int version = sai->pdata->conf->version;
720 unsigned int rate = params_rate(params);
721
722 if (!sai->mclk_rate) {
723 dev_err(cpu_dai->dev, "Mclk rate is null\n");
724 return -EINVAL;
725 }
726
727 if (!(rate % 11025))
728 clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k);
729 else
730 clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k);
731 sai_clk_rate = clk_get_rate(sai->sai_ck);
732
733 if (STM_SAI_IS_F4(sai->pdata)) {
734 /*
735 * mclk_rate = 256 * fs
736 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
737 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise
738 */
739 if (2 * sai_clk_rate >= 3 * sai->mclk_rate)
740 div = DIV_ROUND_CLOSEST(sai_clk_rate,
741 2 * sai->mclk_rate);
742 } else {
743 /*
744 * TDM mode :
745 * mclk on
746 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
747 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
748 * mclk off
749 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
750 * Note: NOMCK/NODIV correspond to same bit.
751 */
752 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
753 div = DIV_ROUND_CLOSEST(sai_clk_rate,
754 (params_rate(params) * 128));
755 } else {
756 if (sai->mclk_rate) {
757 mclk_ratio = sai->mclk_rate / rate;
758 if (mclk_ratio == 512) {
759 mask = SAI_XCR1_OSR;
760 cr1 = SAI_XCR1_OSR;
761 } else if (mclk_ratio != 256) {
762 dev_err(cpu_dai->dev,
763 "Wrong mclk ratio %d\n",
764 mclk_ratio);
765 return -EINVAL;
766 }
767 div = DIV_ROUND_CLOSEST(sai_clk_rate,
768 sai->mclk_rate);
769 } else {
770 /* mclk-fs not set, master clock not active */
771 den = sai->fs_length * params_rate(params);
772 div = DIV_ROUND_CLOSEST(sai_clk_rate, den);
773 }
774 }
775 }
776
777 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
778 dev_err(cpu_dai->dev, "Divider %d out of range\n", div);
779 return -EINVAL;
780 }
781 dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div);
782
783 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
784 cr1 = SAI_XCR1_MCKDIV_SET(div);
785 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
786 if (ret < 0) {
787 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
788 return ret;
789 }
790
791 return 0;
792 }
793
stm32_sai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)794 static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
795 struct snd_pcm_hw_params *params,
796 struct snd_soc_dai *cpu_dai)
797 {
798 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
799 int ret;
800
801 sai->data_size = params_width(params);
802
803 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
804 /* Rate not already set in runtime structure */
805 substream->runtime->rate = params_rate(params);
806 stm32_sai_set_iec958_status(sai, substream->runtime);
807 } else {
808 ret = stm32_sai_set_slots(cpu_dai);
809 if (ret < 0)
810 return ret;
811 stm32_sai_set_frame(cpu_dai);
812 }
813
814 ret = stm32_sai_set_config(cpu_dai, substream, params);
815 if (ret)
816 return ret;
817
818 if (sai->master)
819 ret = stm32_sai_configure_clock(cpu_dai, params);
820
821 return ret;
822 }
823
stm32_sai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)824 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
825 struct snd_soc_dai *cpu_dai)
826 {
827 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
828 int ret;
829
830 switch (cmd) {
831 case SNDRV_PCM_TRIGGER_START:
832 case SNDRV_PCM_TRIGGER_RESUME:
833 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
834 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
835
836 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
837 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
838
839 /* Enable SAI */
840 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
841 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
842 if (ret < 0)
843 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
844 break;
845 case SNDRV_PCM_TRIGGER_SUSPEND:
846 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
847 case SNDRV_PCM_TRIGGER_STOP:
848 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
849
850 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
851 SAI_XIMR_MASK, 0);
852
853 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
854 SAI_XCR1_SAIEN,
855 (unsigned int)~SAI_XCR1_SAIEN);
856
857 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
858 SAI_XCR1_DMAEN,
859 (unsigned int)~SAI_XCR1_DMAEN);
860 if (ret < 0)
861 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
862
863 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
864 sai->spdif_frm_cnt = 0;
865 break;
866 default:
867 return -EINVAL;
868 }
869
870 return ret;
871 }
872
stm32_sai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)873 static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
874 struct snd_soc_dai *cpu_dai)
875 {
876 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
877
878 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
879
880 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_NODIV,
881 SAI_XCR1_NODIV);
882
883 clk_disable_unprepare(sai->sai_ck);
884 sai->substream = NULL;
885 }
886
stm32_sai_pcm_new(struct snd_soc_pcm_runtime * rtd,struct snd_soc_dai * cpu_dai)887 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
888 struct snd_soc_dai *cpu_dai)
889 {
890 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
891
892 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
893 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
894 return snd_ctl_add(rtd->pcm->card,
895 snd_ctl_new1(&iec958_ctls, sai));
896 }
897
898 return 0;
899 }
900
stm32_sai_dai_probe(struct snd_soc_dai * cpu_dai)901 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
902 {
903 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
904 int cr1 = 0, cr1_mask;
905
906 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
907 /*
908 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
909 * as it allows bytes, half-word and words transfers. (See DMA fifos
910 * constraints).
911 */
912 sai->dma_params.maxburst = 4;
913 /* Buswidth will be set by framework at runtime */
914 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
915
916 if (STM_SAI_IS_PLAYBACK(sai))
917 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
918 else
919 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
920
921 /* Next settings are not relevant for spdif mode */
922 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
923 return 0;
924
925 cr1_mask = SAI_XCR1_RX_TX;
926 if (STM_SAI_IS_CAPTURE(sai))
927 cr1 |= SAI_XCR1_RX_TX;
928
929 /* Configure synchronization */
930 if (sai->sync == SAI_SYNC_EXTERNAL) {
931 /* Configure synchro client and provider */
932 sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
933 sai->synco, sai->synci);
934 }
935
936 cr1_mask |= SAI_XCR1_SYNCEN_MASK;
937 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
938
939 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
940 }
941
942 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
943 .set_sysclk = stm32_sai_set_sysclk,
944 .set_fmt = stm32_sai_set_dai_fmt,
945 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
946 .startup = stm32_sai_startup,
947 .hw_params = stm32_sai_hw_params,
948 .trigger = stm32_sai_trigger,
949 .shutdown = stm32_sai_shutdown,
950 };
951
stm32_sai_pcm_process_spdif(struct snd_pcm_substream * substream,int channel,unsigned long hwoff,void * buf,unsigned long bytes)952 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
953 int channel, unsigned long hwoff,
954 void *buf, unsigned long bytes)
955 {
956 struct snd_pcm_runtime *runtime = substream->runtime;
957 struct snd_soc_pcm_runtime *rtd = substream->private_data;
958 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
959 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
960 int *ptr = (int *)(runtime->dma_area + hwoff +
961 channel * (runtime->dma_bytes / runtime->channels));
962 ssize_t cnt = bytes_to_samples(runtime, bytes);
963 unsigned int frm_cnt = sai->spdif_frm_cnt;
964 unsigned int byte;
965 unsigned int mask;
966
967 do {
968 *ptr = ((*ptr >> 8) & 0x00ffffff);
969
970 /* Set channel status bit */
971 byte = frm_cnt >> 3;
972 mask = 1 << (frm_cnt - (byte << 3));
973 if (sai->iec958.status[byte] & mask)
974 *ptr |= 0x04000000;
975 ptr++;
976
977 if (!(cnt % 2))
978 frm_cnt++;
979
980 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
981 frm_cnt = 0;
982 } while (--cnt);
983 sai->spdif_frm_cnt = frm_cnt;
984
985 return 0;
986 }
987
988 static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
989 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
990 .buffer_bytes_max = 8 * PAGE_SIZE,
991 .period_bytes_min = 1024, /* 5ms at 48kHz */
992 .period_bytes_max = PAGE_SIZE,
993 .periods_min = 2,
994 .periods_max = 8,
995 };
996
997 static struct snd_soc_dai_driver stm32_sai_playback_dai[] = {
998 {
999 .probe = stm32_sai_dai_probe,
1000 .pcm_new = stm32_sai_pcm_new,
1001 .id = 1, /* avoid call to fmt_single_name() */
1002 .playback = {
1003 .channels_min = 1,
1004 .channels_max = 2,
1005 .rate_min = 8000,
1006 .rate_max = 192000,
1007 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1008 /* DMA does not support 24 bits transfers */
1009 .formats =
1010 SNDRV_PCM_FMTBIT_S8 |
1011 SNDRV_PCM_FMTBIT_S16_LE |
1012 SNDRV_PCM_FMTBIT_S32_LE,
1013 },
1014 .ops = &stm32_sai_pcm_dai_ops,
1015 }
1016 };
1017
1018 static struct snd_soc_dai_driver stm32_sai_capture_dai[] = {
1019 {
1020 .probe = stm32_sai_dai_probe,
1021 .id = 1, /* avoid call to fmt_single_name() */
1022 .capture = {
1023 .channels_min = 1,
1024 .channels_max = 2,
1025 .rate_min = 8000,
1026 .rate_max = 192000,
1027 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1028 /* DMA does not support 24 bits transfers */
1029 .formats =
1030 SNDRV_PCM_FMTBIT_S8 |
1031 SNDRV_PCM_FMTBIT_S16_LE |
1032 SNDRV_PCM_FMTBIT_S32_LE,
1033 },
1034 .ops = &stm32_sai_pcm_dai_ops,
1035 }
1036 };
1037
1038 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
1039 .pcm_hardware = &stm32_sai_pcm_hw,
1040 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1041 };
1042
1043 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
1044 .pcm_hardware = &stm32_sai_pcm_hw,
1045 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1046 .process = stm32_sai_pcm_process_spdif,
1047 };
1048
1049 static const struct snd_soc_component_driver stm32_component = {
1050 .name = "stm32-sai",
1051 };
1052
1053 static const struct of_device_id stm32_sai_sub_ids[] = {
1054 { .compatible = "st,stm32-sai-sub-a",
1055 .data = (void *)STM_SAI_A_ID},
1056 { .compatible = "st,stm32-sai-sub-b",
1057 .data = (void *)STM_SAI_B_ID},
1058 {}
1059 };
1060 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
1061
stm32_sai_sub_parse_of(struct platform_device * pdev,struct stm32_sai_sub_data * sai)1062 static int stm32_sai_sub_parse_of(struct platform_device *pdev,
1063 struct stm32_sai_sub_data *sai)
1064 {
1065 struct device_node *np = pdev->dev.of_node;
1066 struct resource *res;
1067 void __iomem *base;
1068 struct of_phandle_args args;
1069 int ret;
1070
1071 if (!np)
1072 return -ENODEV;
1073
1074 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1075 base = devm_ioremap_resource(&pdev->dev, res);
1076 if (IS_ERR(base))
1077 return PTR_ERR(base);
1078
1079 sai->phys_addr = res->start;
1080
1081 sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
1082 /* Note: PDM registers not available for H7 sub-block B */
1083 if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai))
1084 sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
1085
1086 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck",
1087 base, sai->regmap_config);
1088 if (IS_ERR(sai->regmap)) {
1089 dev_err(&pdev->dev, "Failed to initialize MMIO\n");
1090 return PTR_ERR(sai->regmap);
1091 }
1092
1093 /* Get direction property */
1094 if (of_property_match_string(np, "dma-names", "tx") >= 0) {
1095 sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
1096 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
1097 sai->dir = SNDRV_PCM_STREAM_CAPTURE;
1098 } else {
1099 dev_err(&pdev->dev, "Unsupported direction\n");
1100 return -EINVAL;
1101 }
1102
1103 /* Get spdif iec60958 property */
1104 sai->spdif = false;
1105 if (of_get_property(np, "st,iec60958", NULL)) {
1106 if (!STM_SAI_HAS_SPDIF(sai) ||
1107 sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
1108 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
1109 return -EINVAL;
1110 }
1111 stm32_sai_init_iec958_status(sai);
1112 sai->spdif = true;
1113 sai->master = true;
1114 }
1115
1116 /* Get synchronization property */
1117 args.np = NULL;
1118 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
1119 if (ret < 0 && ret != -ENOENT) {
1120 dev_err(&pdev->dev, "Failed to get st,sync property\n");
1121 return ret;
1122 }
1123
1124 sai->sync = SAI_SYNC_NONE;
1125 if (args.np) {
1126 if (args.np == np) {
1127 dev_err(&pdev->dev, "%s sync own reference\n",
1128 np->name);
1129 of_node_put(args.np);
1130 return -EINVAL;
1131 }
1132
1133 sai->np_sync_provider = of_get_parent(args.np);
1134 if (!sai->np_sync_provider) {
1135 dev_err(&pdev->dev, "%s parent node not found\n",
1136 np->name);
1137 of_node_put(args.np);
1138 return -ENODEV;
1139 }
1140
1141 sai->sync = SAI_SYNC_INTERNAL;
1142 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
1143 if (!STM_SAI_HAS_EXT_SYNC(sai)) {
1144 dev_err(&pdev->dev,
1145 "External synchro not supported\n");
1146 of_node_put(args.np);
1147 return -EINVAL;
1148 }
1149 sai->sync = SAI_SYNC_EXTERNAL;
1150
1151 sai->synci = args.args[0];
1152 if (sai->synci < 1 ||
1153 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
1154 dev_err(&pdev->dev, "Wrong SAI index\n");
1155 of_node_put(args.np);
1156 return -EINVAL;
1157 }
1158
1159 if (of_property_match_string(args.np, "compatible",
1160 "st,stm32-sai-sub-a") >= 0)
1161 sai->synco = STM_SAI_SYNC_OUT_A;
1162
1163 if (of_property_match_string(args.np, "compatible",
1164 "st,stm32-sai-sub-b") >= 0)
1165 sai->synco = STM_SAI_SYNC_OUT_B;
1166
1167 if (!sai->synco) {
1168 dev_err(&pdev->dev, "Unknown SAI sub-block\n");
1169 of_node_put(args.np);
1170 return -EINVAL;
1171 }
1172 }
1173
1174 dev_dbg(&pdev->dev, "%s synchronized with %s\n",
1175 pdev->name, args.np->full_name);
1176 }
1177
1178 of_node_put(args.np);
1179 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1180 if (IS_ERR(sai->sai_ck)) {
1181 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n");
1182 return PTR_ERR(sai->sai_ck);
1183 }
1184
1185 return 0;
1186 }
1187
stm32_sai_sub_dais_init(struct platform_device * pdev,struct stm32_sai_sub_data * sai)1188 static int stm32_sai_sub_dais_init(struct platform_device *pdev,
1189 struct stm32_sai_sub_data *sai)
1190 {
1191 sai->cpu_dai_drv = devm_kzalloc(&pdev->dev,
1192 sizeof(struct snd_soc_dai_driver),
1193 GFP_KERNEL);
1194 if (!sai->cpu_dai_drv)
1195 return -ENOMEM;
1196
1197 sai->cpu_dai_drv->name = dev_name(&pdev->dev);
1198 if (STM_SAI_IS_PLAYBACK(sai)) {
1199 memcpy(sai->cpu_dai_drv, &stm32_sai_playback_dai,
1200 sizeof(stm32_sai_playback_dai));
1201 sai->cpu_dai_drv->playback.stream_name = sai->cpu_dai_drv->name;
1202 } else {
1203 memcpy(sai->cpu_dai_drv, &stm32_sai_capture_dai,
1204 sizeof(stm32_sai_capture_dai));
1205 sai->cpu_dai_drv->capture.stream_name = sai->cpu_dai_drv->name;
1206 }
1207
1208 return 0;
1209 }
1210
stm32_sai_sub_probe(struct platform_device * pdev)1211 static int stm32_sai_sub_probe(struct platform_device *pdev)
1212 {
1213 struct stm32_sai_sub_data *sai;
1214 const struct of_device_id *of_id;
1215 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
1216 int ret;
1217
1218 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1219 if (!sai)
1220 return -ENOMEM;
1221
1222 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
1223 if (!of_id)
1224 return -EINVAL;
1225 sai->id = (uintptr_t)of_id->data;
1226
1227 sai->pdev = pdev;
1228 mutex_init(&sai->ctrl_lock);
1229 platform_set_drvdata(pdev, sai);
1230
1231 sai->pdata = dev_get_drvdata(pdev->dev.parent);
1232 if (!sai->pdata) {
1233 dev_err(&pdev->dev, "Parent device data not available\n");
1234 return -EINVAL;
1235 }
1236
1237 ret = stm32_sai_sub_parse_of(pdev, sai);
1238 if (ret)
1239 return ret;
1240
1241 ret = stm32_sai_sub_dais_init(pdev, sai);
1242 if (ret)
1243 return ret;
1244
1245 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
1246 IRQF_SHARED, dev_name(&pdev->dev), sai);
1247 if (ret) {
1248 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
1249 return ret;
1250 }
1251
1252 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component,
1253 sai->cpu_dai_drv, 1);
1254 if (ret)
1255 return ret;
1256
1257 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1258 conf = &stm32_sai_pcm_config_spdif;
1259
1260 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
1261 if (ret) {
1262 dev_err(&pdev->dev, "Could not register pcm dma\n");
1263 return ret;
1264 }
1265
1266 return 0;
1267 }
1268
1269 static struct platform_driver stm32_sai_sub_driver = {
1270 .driver = {
1271 .name = "st,stm32-sai-sub",
1272 .of_match_table = stm32_sai_sub_ids,
1273 },
1274 .probe = stm32_sai_sub_probe,
1275 };
1276
1277 module_platform_driver(stm32_sai_sub_driver);
1278
1279 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1280 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
1281 MODULE_ALIAS("platform:st,stm32-sai-sub");
1282 MODULE_LICENSE("GPL v2");
1283
