1 /* 2 * arch/arm/mach-prima2/include/mach/sirfsoc_usp.h 3 * 4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 5 * 6 * Licensed under GPLv2 or later. 7 */ 8 9 #ifndef _SIRF_USP_H 10 #define _SIRF_USP_H 11 12 /* USP Registers */ 13 #define USP_MODE1 0x00 14 #define USP_MODE2 0x04 15 #define USP_TX_FRAME_CTRL 0x08 16 #define USP_RX_FRAME_CTRL 0x0C 17 #define USP_TX_RX_ENABLE 0x10 18 #define USP_INT_ENABLE 0x14 19 #define USP_INT_STATUS 0x18 20 #define USP_PIN_IO_DATA 0x1C 21 #define USP_RISC_DSP_MODE 0x20 22 #define USP_AYSNC_PARAM_REG 0x24 23 #define USP_IRDA_X_MODE_DIV 0x28 24 #define USP_SM_CFG 0x2C 25 #define USP_TX_DMA_IO_CTRL 0x100 26 #define USP_TX_DMA_IO_LEN 0x104 27 #define USP_TX_FIFO_CTRL 0x108 28 #define USP_TX_FIFO_LEVEL_CHK 0x10C 29 #define USP_TX_FIFO_OP 0x110 30 #define USP_TX_FIFO_STATUS 0x114 31 #define USP_TX_FIFO_DATA 0x118 32 #define USP_RX_DMA_IO_CTRL 0x120 33 #define USP_RX_DMA_IO_LEN 0x124 34 #define USP_RX_FIFO_CTRL 0x128 35 #define USP_RX_FIFO_LEVEL_CHK 0x12C 36 #define USP_RX_FIFO_OP 0x130 37 #define USP_RX_FIFO_STATUS 0x134 38 #define USP_RX_FIFO_DATA 0x138 39 40 /* USP MODE register-1 */ 41 #define USP_SYNC_MODE 0x00000001 42 #define USP_CLOCK_MODE_SLAVE 0x00000002 43 #define USP_LOOP_BACK_EN 0x00000004 44 #define USP_HPSIR_EN 0x00000008 45 #define USP_ENDIAN_CTRL_LSBF 0x00000010 46 #define USP_EN 0x00000020 47 #define USP_RXD_ACT_EDGE_FALLING 0x00000040 48 #define USP_TXD_ACT_EDGE_FALLING 0x00000080 49 #define USP_RFS_ACT_LEVEL_LOGIC1 0x00000100 50 #define USP_TFS_ACT_LEVEL_LOGIC1 0x00000200 51 #define USP_SCLK_IDLE_MODE_TOGGLE 0x00000400 52 #define USP_SCLK_IDLE_LEVEL_LOGIC1 0x00000800 53 #define USP_SCLK_PIN_MODE_IO 0x00001000 54 #define USP_RFS_PIN_MODE_IO 0x00002000 55 #define USP_TFS_PIN_MODE_IO 0x00004000 56 #define USP_RXD_PIN_MODE_IO 0x00008000 57 #define USP_TXD_PIN_MODE_IO 0x00010000 58 #define USP_SCLK_IO_MODE_INPUT 0x00020000 59 #define USP_RFS_IO_MODE_INPUT 0x00040000 60 #define USP_TFS_IO_MODE_INPUT 0x00080000 61 #define USP_RXD_IO_MODE_INPUT 0x00100000 62 #define USP_TXD_IO_MODE_INPUT 0x00200000 63 #define USP_IRDA_WIDTH_DIV_MASK 0x3FC00000 64 #define USP_IRDA_WIDTH_DIV_OFFSET 0 65 #define USP_IRDA_IDLE_LEVEL_HIGH 0x40000000 66 #define USP_TX_UFLOW_REPEAT_ZERO 0x80000000 67 #define USP_TX_ENDIAN_MODE 0x00000020 68 #define USP_RX_ENDIAN_MODE 0x00000020 69 70 /* USP Mode Register-2 */ 71 #define USP_RXD_DELAY_LEN_MASK 0x000000FF 72 #define USP_RXD_DELAY_LEN_OFFSET 0 73 74 #define USP_TXD_DELAY_LEN_MASK 0x0000FF00 75 #define USP_TXD_DELAY_LEN_OFFSET 8 76 77 #define USP_ENA_CTRL_MODE 0x00010000 78 #define USP_FRAME_CTRL_MODE 0x00020000 79 #define USP_TFS_SOURCE_MODE 0x00040000 80 #define USP_TFS_MS_MODE 0x00080000 81 #define USP_CLK_DIVISOR_MASK 0x7FE00000 82 #define USP_CLK_DIVISOR_OFFSET 21 83 84 #define USP_TFS_CLK_SLAVE_MODE (1<<20) 85 #define USP_RFS_CLK_SLAVE_MODE (1<<19) 86 87 #define USP_IRDA_DATA_WIDTH 0x80000000 88 89 /* USP Transmit Frame Control Register */ 90 91 #define USP_TXC_DATA_LEN_MASK 0x000000FF 92 #define USP_TXC_DATA_LEN_OFFSET 0 93 94 #define USP_TXC_SYNC_LEN_MASK 0x0000FF00 95 #define USP_TXC_SYNC_LEN_OFFSET 8 96 97 #define USP_TXC_FRAME_LEN_MASK 0x00FF0000 98 #define USP_TXC_FRAME_LEN_OFFSET 16 99 100 #define USP_TXC_SHIFTER_LEN_MASK 0x1F000000 101 #define USP_TXC_SHIFTER_LEN_OFFSET 24 102 103 #define USP_TXC_SLAVE_CLK_SAMPLE 0x20000000 104 105 #define USP_TXC_CLK_DIVISOR_MASK 0xC0000000 106 #define USP_TXC_CLK_DIVISOR_OFFSET 30 107 108 /* USP Receive Frame Control Register */ 109 110 #define USP_RXC_DATA_LEN_MASK 0x000000FF 111 #define USP_RXC_DATA_LEN_OFFSET 0 112 113 #define USP_RXC_FRAME_LEN_MASK 0x0000FF00 114 #define USP_RXC_FRAME_LEN_OFFSET 8 115 116 #define USP_RXC_SHIFTER_LEN_MASK 0x001F0000 117 #define USP_RXC_SHIFTER_LEN_OFFSET 16 118 119 #define USP_START_EDGE_MODE 0x00800000 120 #define USP_I2S_SYNC_CHG 0x00200000 121 122 #define USP_RXC_CLK_DIVISOR_MASK 0x0F000000 123 #define USP_RXC_CLK_DIVISOR_OFFSET 24 124 #define USP_SINGLE_SYNC_MODE 0x00400000 125 126 /* Tx - RX Enable Register */ 127 128 #define USP_RX_ENA 0x00000001 129 #define USP_TX_ENA 0x00000002 130 131 /* USP Interrupt Enable and status Register */ 132 #define USP_RX_DONE_INT 0x00000001 133 #define USP_TX_DONE_INT 0x00000002 134 #define USP_RX_OFLOW_INT 0x00000004 135 #define USP_TX_UFLOW_INT 0x00000008 136 #define USP_RX_IO_DMA_INT 0x00000010 137 #define USP_TX_IO_DMA_INT 0x00000020 138 #define USP_RXFIFO_FULL_INT 0x00000040 139 #define USP_TXFIFO_EMPTY_INT 0x00000080 140 #define USP_RXFIFO_THD_INT 0x00000100 141 #define USP_TXFIFO_THD_INT 0x00000200 142 #define USP_UART_FRM_ERR_INT 0x00000400 143 #define USP_RX_TIMEOUT_INT 0x00000800 144 #define USP_TX_ALLOUT_INT 0x00001000 145 #define USP_RXD_BREAK_INT 0x00008000 146 147 /* All possible TX interruots */ 148 #define USP_TX_INTERRUPT (USP_TX_DONE_INT|USP_TX_UFLOW_INT|\ 149 USP_TX_IO_DMA_INT|\ 150 USP_TXFIFO_EMPTY_INT|\ 151 USP_TXFIFO_THD_INT) 152 /* All possible RX interruots */ 153 #define USP_RX_INTERRUPT (USP_RX_DONE_INT|USP_RX_OFLOW_INT|\ 154 USP_RX_IO_DMA_INT|\ 155 USP_RXFIFO_FULL_INT|\ 156 USP_RXFIFO_THD_INT|\ 157 USP_RX_TIMEOUT_INT) 158 159 #define USP_INT_ALL 0x1FFF 160 161 /* USP Pin I/O Data Register */ 162 163 #define USP_RFS_PIN_VALUE_MASK 0x00000001 164 #define USP_TFS_PIN_VALUE_MASK 0x00000002 165 #define USP_RXD_PIN_VALUE_MASK 0x00000004 166 #define USP_TXD_PIN_VALUE_MASK 0x00000008 167 #define USP_SCLK_PIN_VALUE_MASK 0x00000010 168 169 /* USP RISC/DSP Mode Register */ 170 #define USP_RISC_DSP_SEL 0x00000001 171 172 /* USP ASYNC PARAMETER Register*/ 173 174 #define USP_ASYNC_TIMEOUT_MASK 0x0000FFFF 175 #define USP_ASYNC_TIMEOUT_OFFSET 0 176 #define USP_ASYNC_TIMEOUT(x) (((x)&USP_ASYNC_TIMEOUT_MASK) \ 177 <<USP_ASYNC_TIMEOUT_OFFSET) 178 179 #define USP_ASYNC_DIV2_MASK 0x003F0000 180 #define USP_ASYNC_DIV2_OFFSET 16 181 182 /* USP TX DMA I/O MODE Register */ 183 #define USP_TX_MODE_IO 0x00000001 184 185 /* USP TX DMA I/O Length Register */ 186 #define USP_TX_DATA_LEN_MASK 0xFFFFFFFF 187 #define USP_TX_DATA_LEN_OFFSET 0 188 189 /* USP TX FIFO Control Register */ 190 #define USP_TX_FIFO_WIDTH_MASK 0x00000003 191 #define USP_TX_FIFO_WIDTH_OFFSET 0 192 193 #define USP_TX_FIFO_THD_MASK 0x000001FC 194 #define USP_TX_FIFO_THD_OFFSET 2 195 196 /* USP TX FIFO Level Check Register */ 197 #define USP_TX_FIFO_LEVEL_CHECK_MASK 0x1F 198 #define USP_TX_FIFO_SC_OFFSET 0 199 #define USP_TX_FIFO_LC_OFFSET 10 200 #define USP_TX_FIFO_HC_OFFSET 20 201 202 #define TX_FIFO_SC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \ 203 << USP_TX_FIFO_SC_OFFSET) 204 #define TX_FIFO_LC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \ 205 << USP_TX_FIFO_LC_OFFSET) 206 #define TX_FIFO_HC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \ 207 << USP_TX_FIFO_HC_OFFSET) 208 209 /* USP TX FIFO Operation Register */ 210 #define USP_TX_FIFO_RESET 0x00000001 211 #define USP_TX_FIFO_START 0x00000002 212 213 /* USP TX FIFO Status Register */ 214 #define USP_TX_FIFO_LEVEL_MASK 0x0000007F 215 #define USP_TX_FIFO_LEVEL_OFFSET 0 216 217 #define USP_TX_FIFO_FULL 0x00000080 218 #define USP_TX_FIFO_EMPTY 0x00000100 219 220 /* USP TX FIFO Data Register */ 221 #define USP_TX_FIFO_DATA_MASK 0xFFFFFFFF 222 #define USP_TX_FIFO_DATA_OFFSET 0 223 224 /* USP RX DMA I/O MODE Register */ 225 #define USP_RX_MODE_IO 0x00000001 226 #define USP_RX_DMA_FLUSH 0x00000004 227 228 /* USP RX DMA I/O Length Register */ 229 #define USP_RX_DATA_LEN_MASK 0xFFFFFFFF 230 #define USP_RX_DATA_LEN_OFFSET 0 231 232 /* USP RX FIFO Control Register */ 233 #define USP_RX_FIFO_WIDTH_MASK 0x00000003 234 #define USP_RX_FIFO_WIDTH_OFFSET 0 235 236 #define USP_RX_FIFO_THD_MASK 0x000001FC 237 #define USP_RX_FIFO_THD_OFFSET 2 238 239 /* USP RX FIFO Level Check Register */ 240 241 #define USP_RX_FIFO_LEVEL_CHECK_MASK 0x1F 242 #define USP_RX_FIFO_SC_OFFSET 0 243 #define USP_RX_FIFO_LC_OFFSET 10 244 #define USP_RX_FIFO_HC_OFFSET 20 245 246 #define RX_FIFO_SC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \ 247 << USP_RX_FIFO_SC_OFFSET) 248 #define RX_FIFO_LC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \ 249 << USP_RX_FIFO_LC_OFFSET) 250 #define RX_FIFO_HC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \ 251 << USP_RX_FIFO_HC_OFFSET) 252 253 /* USP RX FIFO Operation Register */ 254 #define USP_RX_FIFO_RESET 0x00000001 255 #define USP_RX_FIFO_START 0x00000002 256 257 /* USP RX FIFO Status Register */ 258 259 #define USP_RX_FIFO_LEVEL_MASK 0x0000007F 260 #define USP_RX_FIFO_LEVEL_OFFSET 0 261 262 #define USP_RX_FIFO_FULL 0x00000080 263 #define USP_RX_FIFO_EMPTY 0x00000100 264 265 /* USP RX FIFO Data Register */ 266 267 #define USP_RX_FIFO_DATA_MASK 0xFFFFFFFF 268 #define USP_RX_FIFO_DATA_OFFSET 0 269 270 /* 271 * When rx thd irq occur, sender just disable tx empty irq, 272 * Remaining data in tx fifo wil also be sent out. 273 */ 274 #define USP_FIFO_SIZE 128 275 #define USP_TX_FIFO_THRESHOLD (USP_FIFO_SIZE/2) 276 #define USP_RX_FIFO_THRESHOLD (USP_FIFO_SIZE/2) 277 278 /* FIFO_WIDTH for the USP_TX_FIFO_CTRL and USP_RX_FIFO_CTRL registers */ 279 #define USP_FIFO_WIDTH_BYTE 0x00 280 #define USP_FIFO_WIDTH_WORD 0x01 281 #define USP_FIFO_WIDTH_DWORD 0x02 282 283 #define USP_ASYNC_DIV2 16 284 285 #define USP_PLUGOUT_RETRY_CNT 2 286 287 #define USP_TX_RX_FIFO_WIDTH_DWORD 2 288 289 #define SIRF_USP_DIV_MCLK 0 290 291 #define SIRF_USP_I2S_TFS_SYNC 0 292 #define SIRF_USP_I2S_RFS_SYNC 1 293 #endif 294
