1 /*
2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
19 *
20 */
21
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/delay.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include "skl.h"
28 #include "skl-topology.h"
29 #include "skl-sst-dsp.h"
30 #include "skl-sst-ipc.h"
31
32 #define HDA_MONO 1
33 #define HDA_STEREO 2
34 #define HDA_QUAD 4
35
36 static const struct snd_pcm_hardware azx_pcm_hw = {
37 .info = (SNDRV_PCM_INFO_MMAP |
38 SNDRV_PCM_INFO_INTERLEAVED |
39 SNDRV_PCM_INFO_BLOCK_TRANSFER |
40 SNDRV_PCM_INFO_MMAP_VALID |
41 SNDRV_PCM_INFO_PAUSE |
42 SNDRV_PCM_INFO_RESUME |
43 SNDRV_PCM_INFO_SYNC_START |
44 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
45 SNDRV_PCM_INFO_HAS_LINK_ATIME |
46 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
47 .formats = SNDRV_PCM_FMTBIT_S16_LE |
48 SNDRV_PCM_FMTBIT_S32_LE |
49 SNDRV_PCM_FMTBIT_S24_LE,
50 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
51 SNDRV_PCM_RATE_8000,
52 .rate_min = 8000,
53 .rate_max = 48000,
54 .channels_min = 1,
55 .channels_max = 8,
56 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
57 .period_bytes_min = 128,
58 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
59 .periods_min = 2,
60 .periods_max = AZX_MAX_FRAG,
61 .fifo_size = 0,
62 };
63
64 static inline
get_hdac_ext_stream(struct snd_pcm_substream * substream)65 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
66 {
67 return substream->runtime->private_data;
68 }
69
get_bus_ctx(struct snd_pcm_substream * substream)70 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
71 {
72 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
73 struct hdac_stream *hstream = hdac_stream(stream);
74 struct hdac_bus *bus = hstream->bus;
75 return bus;
76 }
77
skl_substream_alloc_pages(struct hdac_bus * bus,struct snd_pcm_substream * substream,size_t size)78 static int skl_substream_alloc_pages(struct hdac_bus *bus,
79 struct snd_pcm_substream *substream,
80 size_t size)
81 {
82 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
83
84 hdac_stream(stream)->bufsize = 0;
85 hdac_stream(stream)->period_bytes = 0;
86 hdac_stream(stream)->format_val = 0;
87
88 return snd_pcm_lib_malloc_pages(substream, size);
89 }
90
skl_substream_free_pages(struct hdac_bus * bus,struct snd_pcm_substream * substream)91 static int skl_substream_free_pages(struct hdac_bus *bus,
92 struct snd_pcm_substream *substream)
93 {
94 return snd_pcm_lib_free_pages(substream);
95 }
96
skl_set_pcm_constrains(struct hdac_bus * bus,struct snd_pcm_runtime * runtime)97 static void skl_set_pcm_constrains(struct hdac_bus *bus,
98 struct snd_pcm_runtime *runtime)
99 {
100 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
101
102 /* avoid wrap-around with wall-clock */
103 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
104 20, 178000000);
105 }
106
skl_get_host_stream_type(struct hdac_bus * bus)107 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
108 {
109 if (bus->ppcap)
110 return HDAC_EXT_STREAM_TYPE_HOST;
111 else
112 return HDAC_EXT_STREAM_TYPE_COUPLED;
113 }
114
115 /*
116 * check if the stream opened is marked as ignore_suspend by machine, if so
117 * then enable suspend_active refcount
118 *
119 * The count supend_active does not need lock as it is used in open/close
120 * and suspend context
121 */
skl_set_suspend_active(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,bool enable)122 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
123 struct snd_soc_dai *dai, bool enable)
124 {
125 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
126 struct snd_soc_dapm_widget *w;
127 struct skl *skl = bus_to_skl(bus);
128
129 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
130 w = dai->playback_widget;
131 else
132 w = dai->capture_widget;
133
134 if (w->ignore_suspend && enable)
135 skl->supend_active++;
136 else if (w->ignore_suspend && !enable)
137 skl->supend_active--;
138 }
139
skl_pcm_host_dma_prepare(struct device * dev,struct skl_pipe_params * params)140 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
141 {
142 struct hdac_bus *bus = dev_get_drvdata(dev);
143 unsigned int format_val;
144 struct hdac_stream *hstream;
145 struct hdac_ext_stream *stream;
146 int err;
147
148 hstream = snd_hdac_get_stream(bus, params->stream,
149 params->host_dma_id + 1);
150 if (!hstream)
151 return -EINVAL;
152
153 stream = stream_to_hdac_ext_stream(hstream);
154 snd_hdac_ext_stream_decouple(bus, stream, true);
155
156 format_val = snd_hdac_calc_stream_format(params->s_freq,
157 params->ch, params->format, params->host_bps, 0);
158
159 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
160 format_val, params->s_freq, params->ch, params->format);
161
162 snd_hdac_stream_reset(hdac_stream(stream));
163 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
164 if (err < 0)
165 return err;
166
167 err = snd_hdac_stream_setup(hdac_stream(stream));
168 if (err < 0)
169 return err;
170
171 hdac_stream(stream)->prepared = 1;
172
173 return 0;
174 }
175
skl_pcm_link_dma_prepare(struct device * dev,struct skl_pipe_params * params)176 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
177 {
178 struct hdac_bus *bus = dev_get_drvdata(dev);
179 unsigned int format_val;
180 struct hdac_stream *hstream;
181 struct hdac_ext_stream *stream;
182 struct hdac_ext_link *link;
183
184 hstream = snd_hdac_get_stream(bus, params->stream,
185 params->link_dma_id + 1);
186 if (!hstream)
187 return -EINVAL;
188
189 stream = stream_to_hdac_ext_stream(hstream);
190 snd_hdac_ext_stream_decouple(bus, stream, true);
191 format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
192 params->format, params->link_bps, 0);
193
194 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
195 format_val, params->s_freq, params->ch, params->format);
196
197 snd_hdac_ext_link_stream_reset(stream);
198
199 snd_hdac_ext_link_stream_setup(stream, format_val);
200
201 list_for_each_entry(link, &bus->hlink_list, list) {
202 if (link->index == params->link_index)
203 snd_hdac_ext_link_set_stream_id(link,
204 hstream->stream_tag);
205 }
206
207 stream->link_prepared = 1;
208
209 return 0;
210 }
211
skl_pcm_open(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)212 static int skl_pcm_open(struct snd_pcm_substream *substream,
213 struct snd_soc_dai *dai)
214 {
215 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
216 struct hdac_ext_stream *stream;
217 struct snd_pcm_runtime *runtime = substream->runtime;
218 struct skl_dma_params *dma_params;
219 struct skl *skl = get_skl_ctx(dai->dev);
220 struct skl_module_cfg *mconfig;
221
222 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
223
224 stream = snd_hdac_ext_stream_assign(bus, substream,
225 skl_get_host_stream_type(bus));
226 if (stream == NULL)
227 return -EBUSY;
228
229 skl_set_pcm_constrains(bus, runtime);
230
231 /*
232 * disable WALLCLOCK timestamps for capture streams
233 * until we figure out how to handle digital inputs
234 */
235 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
236 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
237 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
238 }
239
240 runtime->private_data = stream;
241
242 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
243 if (!dma_params)
244 return -ENOMEM;
245
246 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
247 snd_soc_dai_set_dma_data(dai, substream, dma_params);
248
249 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
250 dma_params->stream_tag);
251 skl_set_suspend_active(substream, dai, true);
252 snd_pcm_set_sync(substream);
253
254 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
255 if (!mconfig)
256 return -EINVAL;
257
258 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
259
260 return 0;
261 }
262
skl_pcm_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)263 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
264 struct snd_soc_dai *dai)
265 {
266 struct skl *skl = get_skl_ctx(dai->dev);
267 struct skl_module_cfg *mconfig;
268 int ret;
269
270 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
271
272 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
273
274 /*
275 * In case of XRUN recovery or in the case when the application
276 * calls prepare another time, reset the FW pipe to clean state
277 */
278 if (mconfig &&
279 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN ||
280 mconfig->pipe->state == SKL_PIPE_CREATED ||
281 mconfig->pipe->state == SKL_PIPE_PAUSED)) {
282
283 ret = skl_reset_pipe(skl->skl_sst, mconfig->pipe);
284
285 if (ret < 0)
286 return ret;
287
288 ret = skl_pcm_host_dma_prepare(dai->dev,
289 mconfig->pipe->p_params);
290 if (ret < 0)
291 return ret;
292 }
293
294 return 0;
295 }
296
skl_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)297 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
298 struct snd_pcm_hw_params *params,
299 struct snd_soc_dai *dai)
300 {
301 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
302 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
303 struct snd_pcm_runtime *runtime = substream->runtime;
304 struct skl_pipe_params p_params = {0};
305 struct skl_module_cfg *m_cfg;
306 int ret, dma_id;
307
308 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
309 ret = skl_substream_alloc_pages(bus, substream,
310 params_buffer_bytes(params));
311 if (ret < 0)
312 return ret;
313
314 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
315 runtime->rate, runtime->channels, runtime->format);
316
317 dma_id = hdac_stream(stream)->stream_tag - 1;
318 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
319
320 p_params.s_fmt = snd_pcm_format_width(params_format(params));
321 p_params.ch = params_channels(params);
322 p_params.s_freq = params_rate(params);
323 p_params.host_dma_id = dma_id;
324 p_params.stream = substream->stream;
325 p_params.format = params_format(params);
326 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
327 p_params.host_bps = dai->driver->playback.sig_bits;
328 else
329 p_params.host_bps = dai->driver->capture.sig_bits;
330
331
332 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
333 if (m_cfg)
334 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
335
336 return 0;
337 }
338
skl_pcm_close(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)339 static void skl_pcm_close(struct snd_pcm_substream *substream,
340 struct snd_soc_dai *dai)
341 {
342 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
343 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
344 struct skl_dma_params *dma_params = NULL;
345 struct skl *skl = bus_to_skl(bus);
346 struct skl_module_cfg *mconfig;
347
348 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
349
350 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
351
352 dma_params = snd_soc_dai_get_dma_data(dai, substream);
353 /*
354 * now we should set this to NULL as we are freeing by the
355 * dma_params
356 */
357 snd_soc_dai_set_dma_data(dai, substream, NULL);
358 skl_set_suspend_active(substream, dai, false);
359
360 /*
361 * check if close is for "Reference Pin" and set back the
362 * CGCTL.MISCBDCGE if disabled by driver
363 */
364 if (!strncmp(dai->name, "Reference Pin", 13) &&
365 skl->skl_sst->miscbdcg_disabled) {
366 skl->skl_sst->enable_miscbdcge(dai->dev, true);
367 skl->skl_sst->miscbdcg_disabled = false;
368 }
369
370 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
371 if (mconfig)
372 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
373
374 kfree(dma_params);
375 }
376
skl_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)377 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
378 struct snd_soc_dai *dai)
379 {
380 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
381 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
382 struct skl *skl = get_skl_ctx(dai->dev);
383 struct skl_module_cfg *mconfig;
384 int ret;
385
386 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
387
388 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
389
390 if (mconfig) {
391 ret = skl_reset_pipe(skl->skl_sst, mconfig->pipe);
392 if (ret < 0)
393 dev_err(dai->dev, "%s:Reset failed ret =%d",
394 __func__, ret);
395 }
396
397 snd_hdac_stream_cleanup(hdac_stream(stream));
398 hdac_stream(stream)->prepared = 0;
399
400 return skl_substream_free_pages(bus, substream);
401 }
402
skl_be_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)403 static int skl_be_hw_params(struct snd_pcm_substream *substream,
404 struct snd_pcm_hw_params *params,
405 struct snd_soc_dai *dai)
406 {
407 struct skl_pipe_params p_params = {0};
408
409 p_params.s_fmt = snd_pcm_format_width(params_format(params));
410 p_params.ch = params_channels(params);
411 p_params.s_freq = params_rate(params);
412 p_params.stream = substream->stream;
413
414 return skl_tplg_be_update_params(dai, &p_params);
415 }
416
skl_decoupled_trigger(struct snd_pcm_substream * substream,int cmd)417 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
418 int cmd)
419 {
420 struct hdac_bus *bus = get_bus_ctx(substream);
421 struct hdac_ext_stream *stream;
422 int start;
423 unsigned long cookie;
424 struct hdac_stream *hstr;
425
426 stream = get_hdac_ext_stream(substream);
427 hstr = hdac_stream(stream);
428
429 if (!hstr->prepared)
430 return -EPIPE;
431
432 switch (cmd) {
433 case SNDRV_PCM_TRIGGER_START:
434 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
435 case SNDRV_PCM_TRIGGER_RESUME:
436 start = 1;
437 break;
438
439 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
440 case SNDRV_PCM_TRIGGER_SUSPEND:
441 case SNDRV_PCM_TRIGGER_STOP:
442 start = 0;
443 break;
444
445 default:
446 return -EINVAL;
447 }
448
449 spin_lock_irqsave(&bus->reg_lock, cookie);
450
451 if (start) {
452 snd_hdac_stream_start(hdac_stream(stream), true);
453 snd_hdac_stream_timecounter_init(hstr, 0);
454 } else {
455 snd_hdac_stream_stop(hdac_stream(stream));
456 }
457
458 spin_unlock_irqrestore(&bus->reg_lock, cookie);
459
460 return 0;
461 }
462
skl_pcm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)463 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
464 struct snd_soc_dai *dai)
465 {
466 struct skl *skl = get_skl_ctx(dai->dev);
467 struct skl_sst *ctx = skl->skl_sst;
468 struct skl_module_cfg *mconfig;
469 struct hdac_bus *bus = get_bus_ctx(substream);
470 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
471 struct snd_soc_dapm_widget *w;
472 int ret;
473
474 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
475 if (!mconfig)
476 return -EIO;
477
478 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
479 w = dai->playback_widget;
480 else
481 w = dai->capture_widget;
482
483 switch (cmd) {
484 case SNDRV_PCM_TRIGGER_RESUME:
485 if (!w->ignore_suspend) {
486 /*
487 * enable DMA Resume enable bit for the stream, set the
488 * dpib & lpib position to resume before starting the
489 * DMA
490 */
491 snd_hdac_ext_stream_drsm_enable(bus, true,
492 hdac_stream(stream)->index);
493 snd_hdac_ext_stream_set_dpibr(bus, stream,
494 stream->lpib);
495 snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
496 }
497
498 case SNDRV_PCM_TRIGGER_START:
499 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
500 /*
501 * Start HOST DMA and Start FE Pipe.This is to make sure that
502 * there are no underrun/overrun in the case when the FE
503 * pipeline is started but there is a delay in starting the
504 * DMA channel on the host.
505 */
506 ret = skl_decoupled_trigger(substream, cmd);
507 if (ret < 0)
508 return ret;
509 return skl_run_pipe(ctx, mconfig->pipe);
510 break;
511
512 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
513 case SNDRV_PCM_TRIGGER_SUSPEND:
514 case SNDRV_PCM_TRIGGER_STOP:
515 /*
516 * Stop FE Pipe first and stop DMA. This is to make sure that
517 * there are no underrun/overrun in the case if there is a delay
518 * between the two operations.
519 */
520 ret = skl_stop_pipe(ctx, mconfig->pipe);
521 if (ret < 0)
522 return ret;
523
524 ret = skl_decoupled_trigger(substream, cmd);
525 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
526 /* save the dpib and lpib positions */
527 stream->dpib = readl(bus->remap_addr +
528 AZX_REG_VS_SDXDPIB_XBASE +
529 (AZX_REG_VS_SDXDPIB_XINTERVAL *
530 hdac_stream(stream)->index));
531
532 stream->lpib = snd_hdac_stream_get_pos_lpib(
533 hdac_stream(stream));
534 snd_hdac_ext_stream_decouple(bus, stream, false);
535 }
536 break;
537
538 default:
539 return -EINVAL;
540 }
541
542 return 0;
543 }
544
545
skl_link_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)546 static int skl_link_hw_params(struct snd_pcm_substream *substream,
547 struct snd_pcm_hw_params *params,
548 struct snd_soc_dai *dai)
549 {
550 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
551 struct hdac_ext_stream *link_dev;
552 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
553 struct snd_soc_dai *codec_dai = rtd->codec_dai;
554 struct skl_pipe_params p_params = {0};
555 struct hdac_ext_link *link;
556 int stream_tag;
557
558 link_dev = snd_hdac_ext_stream_assign(bus, substream,
559 HDAC_EXT_STREAM_TYPE_LINK);
560 if (!link_dev)
561 return -EBUSY;
562
563 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
564
565 link = snd_hdac_ext_bus_get_link(bus, codec_dai->component->name);
566 if (!link)
567 return -EINVAL;
568
569 stream_tag = hdac_stream(link_dev)->stream_tag;
570
571 /* set the stream tag in the codec dai dma params */
572 snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0);
573
574 p_params.s_fmt = snd_pcm_format_width(params_format(params));
575 p_params.ch = params_channels(params);
576 p_params.s_freq = params_rate(params);
577 p_params.stream = substream->stream;
578 p_params.link_dma_id = stream_tag - 1;
579 p_params.link_index = link->index;
580 p_params.format = params_format(params);
581
582 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
583 p_params.link_bps = codec_dai->driver->playback.sig_bits;
584 else
585 p_params.link_bps = codec_dai->driver->capture.sig_bits;
586
587 return skl_tplg_be_update_params(dai, &p_params);
588 }
589
skl_link_pcm_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)590 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
591 struct snd_soc_dai *dai)
592 {
593 struct skl *skl = get_skl_ctx(dai->dev);
594 struct skl_module_cfg *mconfig = NULL;
595
596 /* In case of XRUN recovery, reset the FW pipe to clean state */
597 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
598 if (mconfig && !mconfig->pipe->passthru &&
599 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN))
600 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
601
602 return 0;
603 }
604
skl_link_pcm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)605 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
606 int cmd, struct snd_soc_dai *dai)
607 {
608 struct hdac_ext_stream *link_dev =
609 snd_soc_dai_get_dma_data(dai, substream);
610 struct hdac_bus *bus = get_bus_ctx(substream);
611 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
612
613 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
614 switch (cmd) {
615 case SNDRV_PCM_TRIGGER_RESUME:
616 case SNDRV_PCM_TRIGGER_START:
617 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
618 snd_hdac_ext_link_stream_start(link_dev);
619 break;
620
621 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
622 case SNDRV_PCM_TRIGGER_SUSPEND:
623 case SNDRV_PCM_TRIGGER_STOP:
624 snd_hdac_ext_link_stream_clear(link_dev);
625 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
626 snd_hdac_ext_stream_decouple(bus, stream, false);
627 break;
628
629 default:
630 return -EINVAL;
631 }
632 return 0;
633 }
634
skl_link_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)635 static int skl_link_hw_free(struct snd_pcm_substream *substream,
636 struct snd_soc_dai *dai)
637 {
638 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
639 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
640 struct hdac_ext_stream *link_dev =
641 snd_soc_dai_get_dma_data(dai, substream);
642 struct hdac_ext_link *link;
643
644 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
645
646 link_dev->link_prepared = 0;
647
648 link = snd_hdac_ext_bus_get_link(bus, rtd->codec_dai->component->name);
649 if (!link)
650 return -EINVAL;
651
652 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
653 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
654 return 0;
655 }
656
657 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
658 .startup = skl_pcm_open,
659 .shutdown = skl_pcm_close,
660 .prepare = skl_pcm_prepare,
661 .hw_params = skl_pcm_hw_params,
662 .hw_free = skl_pcm_hw_free,
663 .trigger = skl_pcm_trigger,
664 };
665
666 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
667 .hw_params = skl_be_hw_params,
668 };
669
670 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
671 .hw_params = skl_be_hw_params,
672 };
673
674 static const struct snd_soc_dai_ops skl_link_dai_ops = {
675 .prepare = skl_link_pcm_prepare,
676 .hw_params = skl_link_hw_params,
677 .hw_free = skl_link_hw_free,
678 .trigger = skl_link_pcm_trigger,
679 };
680
681 static struct snd_soc_dai_driver skl_fe_dai[] = {
682 {
683 .name = "System Pin",
684 .ops = &skl_pcm_dai_ops,
685 .playback = {
686 .stream_name = "System Playback",
687 .channels_min = HDA_MONO,
688 .channels_max = HDA_STEREO,
689 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
690 .formats = SNDRV_PCM_FMTBIT_S16_LE |
691 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
692 .sig_bits = 32,
693 },
694 .capture = {
695 .stream_name = "System Capture",
696 .channels_min = HDA_MONO,
697 .channels_max = HDA_STEREO,
698 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
699 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
700 .sig_bits = 32,
701 },
702 },
703 {
704 .name = "System Pin2",
705 .ops = &skl_pcm_dai_ops,
706 .playback = {
707 .stream_name = "Headset Playback",
708 .channels_min = HDA_MONO,
709 .channels_max = HDA_STEREO,
710 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
711 SNDRV_PCM_RATE_8000,
712 .formats = SNDRV_PCM_FMTBIT_S16_LE |
713 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
714 },
715 },
716 {
717 .name = "Echoref Pin",
718 .ops = &skl_pcm_dai_ops,
719 .capture = {
720 .stream_name = "Echoreference Capture",
721 .channels_min = HDA_STEREO,
722 .channels_max = HDA_STEREO,
723 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
724 SNDRV_PCM_RATE_8000,
725 .formats = SNDRV_PCM_FMTBIT_S16_LE |
726 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
727 },
728 },
729 {
730 .name = "Reference Pin",
731 .ops = &skl_pcm_dai_ops,
732 .capture = {
733 .stream_name = "Reference Capture",
734 .channels_min = HDA_MONO,
735 .channels_max = HDA_QUAD,
736 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
737 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
738 .sig_bits = 32,
739 },
740 },
741 {
742 .name = "Deepbuffer Pin",
743 .ops = &skl_pcm_dai_ops,
744 .playback = {
745 .stream_name = "Deepbuffer Playback",
746 .channels_min = HDA_STEREO,
747 .channels_max = HDA_STEREO,
748 .rates = SNDRV_PCM_RATE_48000,
749 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
750 .sig_bits = 32,
751 },
752 },
753 {
754 .name = "LowLatency Pin",
755 .ops = &skl_pcm_dai_ops,
756 .playback = {
757 .stream_name = "Low Latency Playback",
758 .channels_min = HDA_STEREO,
759 .channels_max = HDA_STEREO,
760 .rates = SNDRV_PCM_RATE_48000,
761 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
762 .sig_bits = 32,
763 },
764 },
765 {
766 .name = "DMIC Pin",
767 .ops = &skl_pcm_dai_ops,
768 .capture = {
769 .stream_name = "DMIC Capture",
770 .channels_min = HDA_MONO,
771 .channels_max = HDA_QUAD,
772 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
773 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
774 .sig_bits = 32,
775 },
776 },
777 {
778 .name = "HDMI1 Pin",
779 .ops = &skl_pcm_dai_ops,
780 .playback = {
781 .stream_name = "HDMI1 Playback",
782 .channels_min = HDA_STEREO,
783 .channels_max = 8,
784 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
785 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
786 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
787 SNDRV_PCM_RATE_192000,
788 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
789 SNDRV_PCM_FMTBIT_S32_LE,
790 .sig_bits = 32,
791 },
792 },
793 {
794 .name = "HDMI2 Pin",
795 .ops = &skl_pcm_dai_ops,
796 .playback = {
797 .stream_name = "HDMI2 Playback",
798 .channels_min = HDA_STEREO,
799 .channels_max = 8,
800 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
801 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
802 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
803 SNDRV_PCM_RATE_192000,
804 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
805 SNDRV_PCM_FMTBIT_S32_LE,
806 .sig_bits = 32,
807 },
808 },
809 {
810 .name = "HDMI3 Pin",
811 .ops = &skl_pcm_dai_ops,
812 .playback = {
813 .stream_name = "HDMI3 Playback",
814 .channels_min = HDA_STEREO,
815 .channels_max = 8,
816 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
817 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
818 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
819 SNDRV_PCM_RATE_192000,
820 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
821 SNDRV_PCM_FMTBIT_S32_LE,
822 .sig_bits = 32,
823 },
824 },
825 };
826
827 /* BE CPU Dais */
828 static struct snd_soc_dai_driver skl_platform_dai[] = {
829 {
830 .name = "SSP0 Pin",
831 .ops = &skl_be_ssp_dai_ops,
832 .playback = {
833 .stream_name = "ssp0 Tx",
834 .channels_min = HDA_STEREO,
835 .channels_max = HDA_STEREO,
836 .rates = SNDRV_PCM_RATE_48000,
837 .formats = SNDRV_PCM_FMTBIT_S16_LE,
838 },
839 .capture = {
840 .stream_name = "ssp0 Rx",
841 .channels_min = HDA_STEREO,
842 .channels_max = HDA_STEREO,
843 .rates = SNDRV_PCM_RATE_48000,
844 .formats = SNDRV_PCM_FMTBIT_S16_LE,
845 },
846 },
847 {
848 .name = "SSP1 Pin",
849 .ops = &skl_be_ssp_dai_ops,
850 .playback = {
851 .stream_name = "ssp1 Tx",
852 .channels_min = HDA_STEREO,
853 .channels_max = HDA_STEREO,
854 .rates = SNDRV_PCM_RATE_48000,
855 .formats = SNDRV_PCM_FMTBIT_S16_LE,
856 },
857 .capture = {
858 .stream_name = "ssp1 Rx",
859 .channels_min = HDA_STEREO,
860 .channels_max = HDA_STEREO,
861 .rates = SNDRV_PCM_RATE_48000,
862 .formats = SNDRV_PCM_FMTBIT_S16_LE,
863 },
864 },
865 {
866 .name = "SSP2 Pin",
867 .ops = &skl_be_ssp_dai_ops,
868 .playback = {
869 .stream_name = "ssp2 Tx",
870 .channels_min = HDA_STEREO,
871 .channels_max = HDA_STEREO,
872 .rates = SNDRV_PCM_RATE_48000,
873 .formats = SNDRV_PCM_FMTBIT_S16_LE,
874 },
875 .capture = {
876 .stream_name = "ssp2 Rx",
877 .channels_min = HDA_STEREO,
878 .channels_max = HDA_STEREO,
879 .rates = SNDRV_PCM_RATE_48000,
880 .formats = SNDRV_PCM_FMTBIT_S16_LE,
881 },
882 },
883 {
884 .name = "SSP3 Pin",
885 .ops = &skl_be_ssp_dai_ops,
886 .playback = {
887 .stream_name = "ssp3 Tx",
888 .channels_min = HDA_STEREO,
889 .channels_max = HDA_STEREO,
890 .rates = SNDRV_PCM_RATE_48000,
891 .formats = SNDRV_PCM_FMTBIT_S16_LE,
892 },
893 .capture = {
894 .stream_name = "ssp3 Rx",
895 .channels_min = HDA_STEREO,
896 .channels_max = HDA_STEREO,
897 .rates = SNDRV_PCM_RATE_48000,
898 .formats = SNDRV_PCM_FMTBIT_S16_LE,
899 },
900 },
901 {
902 .name = "SSP4 Pin",
903 .ops = &skl_be_ssp_dai_ops,
904 .playback = {
905 .stream_name = "ssp4 Tx",
906 .channels_min = HDA_STEREO,
907 .channels_max = HDA_STEREO,
908 .rates = SNDRV_PCM_RATE_48000,
909 .formats = SNDRV_PCM_FMTBIT_S16_LE,
910 },
911 .capture = {
912 .stream_name = "ssp4 Rx",
913 .channels_min = HDA_STEREO,
914 .channels_max = HDA_STEREO,
915 .rates = SNDRV_PCM_RATE_48000,
916 .formats = SNDRV_PCM_FMTBIT_S16_LE,
917 },
918 },
919 {
920 .name = "SSP5 Pin",
921 .ops = &skl_be_ssp_dai_ops,
922 .playback = {
923 .stream_name = "ssp5 Tx",
924 .channels_min = HDA_STEREO,
925 .channels_max = HDA_STEREO,
926 .rates = SNDRV_PCM_RATE_48000,
927 .formats = SNDRV_PCM_FMTBIT_S16_LE,
928 },
929 .capture = {
930 .stream_name = "ssp5 Rx",
931 .channels_min = HDA_STEREO,
932 .channels_max = HDA_STEREO,
933 .rates = SNDRV_PCM_RATE_48000,
934 .formats = SNDRV_PCM_FMTBIT_S16_LE,
935 },
936 },
937 {
938 .name = "iDisp1 Pin",
939 .ops = &skl_link_dai_ops,
940 .playback = {
941 .stream_name = "iDisp1 Tx",
942 .channels_min = HDA_STEREO,
943 .channels_max = 8,
944 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
945 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
946 SNDRV_PCM_FMTBIT_S24_LE,
947 },
948 },
949 {
950 .name = "iDisp2 Pin",
951 .ops = &skl_link_dai_ops,
952 .playback = {
953 .stream_name = "iDisp2 Tx",
954 .channels_min = HDA_STEREO,
955 .channels_max = 8,
956 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
957 SNDRV_PCM_RATE_48000,
958 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
959 SNDRV_PCM_FMTBIT_S24_LE,
960 },
961 },
962 {
963 .name = "iDisp3 Pin",
964 .ops = &skl_link_dai_ops,
965 .playback = {
966 .stream_name = "iDisp3 Tx",
967 .channels_min = HDA_STEREO,
968 .channels_max = 8,
969 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
970 SNDRV_PCM_RATE_48000,
971 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
972 SNDRV_PCM_FMTBIT_S24_LE,
973 },
974 },
975 {
976 .name = "DMIC01 Pin",
977 .ops = &skl_dmic_dai_ops,
978 .capture = {
979 .stream_name = "DMIC01 Rx",
980 .channels_min = HDA_MONO,
981 .channels_max = HDA_QUAD,
982 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
983 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
984 },
985 },
986 {
987 .name = "DMIC16k Pin",
988 .ops = &skl_dmic_dai_ops,
989 .capture = {
990 .stream_name = "DMIC16k Rx",
991 .channels_min = HDA_MONO,
992 .channels_max = HDA_QUAD,
993 .rates = SNDRV_PCM_RATE_16000,
994 .formats = SNDRV_PCM_FMTBIT_S16_LE,
995 },
996 },
997 {
998 .name = "HD-Codec Pin",
999 .ops = &skl_link_dai_ops,
1000 .playback = {
1001 .stream_name = "HD-Codec Tx",
1002 .channels_min = HDA_STEREO,
1003 .channels_max = HDA_STEREO,
1004 .rates = SNDRV_PCM_RATE_48000,
1005 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1006 },
1007 .capture = {
1008 .stream_name = "HD-Codec Rx",
1009 .channels_min = HDA_STEREO,
1010 .channels_max = HDA_STEREO,
1011 .rates = SNDRV_PCM_RATE_48000,
1012 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1013 },
1014 },
1015 };
1016
skl_dai_load(struct snd_soc_component * cmp,int index,struct snd_soc_dai_driver * dai_drv,struct snd_soc_tplg_pcm * pcm,struct snd_soc_dai * dai)1017 int skl_dai_load(struct snd_soc_component *cmp, int index,
1018 struct snd_soc_dai_driver *dai_drv,
1019 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1020 {
1021 dai_drv->ops = &skl_pcm_dai_ops;
1022
1023 return 0;
1024 }
1025
skl_platform_open(struct snd_pcm_substream * substream)1026 static int skl_platform_open(struct snd_pcm_substream *substream)
1027 {
1028 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1029 struct snd_soc_dai_link *dai_link = rtd->dai_link;
1030
1031 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
1032 dai_link->cpu_dai_name);
1033
1034 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1035
1036 return 0;
1037 }
1038
skl_coupled_trigger(struct snd_pcm_substream * substream,int cmd)1039 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1040 int cmd)
1041 {
1042 struct hdac_bus *bus = get_bus_ctx(substream);
1043 struct hdac_ext_stream *stream;
1044 struct snd_pcm_substream *s;
1045 bool start;
1046 int sbits = 0;
1047 unsigned long cookie;
1048 struct hdac_stream *hstr;
1049
1050 stream = get_hdac_ext_stream(substream);
1051 hstr = hdac_stream(stream);
1052
1053 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1054
1055 if (!hstr->prepared)
1056 return -EPIPE;
1057
1058 switch (cmd) {
1059 case SNDRV_PCM_TRIGGER_START:
1060 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1061 case SNDRV_PCM_TRIGGER_RESUME:
1062 start = true;
1063 break;
1064
1065 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1066 case SNDRV_PCM_TRIGGER_SUSPEND:
1067 case SNDRV_PCM_TRIGGER_STOP:
1068 start = false;
1069 break;
1070
1071 default:
1072 return -EINVAL;
1073 }
1074
1075 snd_pcm_group_for_each_entry(s, substream) {
1076 if (s->pcm->card != substream->pcm->card)
1077 continue;
1078 stream = get_hdac_ext_stream(s);
1079 sbits |= 1 << hdac_stream(stream)->index;
1080 snd_pcm_trigger_done(s, substream);
1081 }
1082
1083 spin_lock_irqsave(&bus->reg_lock, cookie);
1084
1085 /* first, set SYNC bits of corresponding streams */
1086 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1087
1088 snd_pcm_group_for_each_entry(s, substream) {
1089 if (s->pcm->card != substream->pcm->card)
1090 continue;
1091 stream = get_hdac_ext_stream(s);
1092 if (start)
1093 snd_hdac_stream_start(hdac_stream(stream), true);
1094 else
1095 snd_hdac_stream_stop(hdac_stream(stream));
1096 }
1097 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1098
1099 snd_hdac_stream_sync(hstr, start, sbits);
1100
1101 spin_lock_irqsave(&bus->reg_lock, cookie);
1102
1103 /* reset SYNC bits */
1104 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1105 if (start)
1106 snd_hdac_stream_timecounter_init(hstr, sbits);
1107 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1108
1109 return 0;
1110 }
1111
skl_platform_pcm_trigger(struct snd_pcm_substream * substream,int cmd)1112 static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
1113 int cmd)
1114 {
1115 struct hdac_bus *bus = get_bus_ctx(substream);
1116
1117 if (!bus->ppcap)
1118 return skl_coupled_trigger(substream, cmd);
1119
1120 return 0;
1121 }
1122
skl_platform_pcm_pointer(struct snd_pcm_substream * substream)1123 static snd_pcm_uframes_t skl_platform_pcm_pointer
1124 (struct snd_pcm_substream *substream)
1125 {
1126 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1127 struct hdac_bus *bus = get_bus_ctx(substream);
1128 unsigned int pos;
1129
1130 /*
1131 * Use DPIB for Playback stream as the periodic DMA Position-in-
1132 * Buffer Writes may be scheduled at the same time or later than
1133 * the MSI and does not guarantee to reflect the Position of the
1134 * last buffer that was transferred. Whereas DPIB register in
1135 * HAD space reflects the actual data that is transferred.
1136 * Use the position buffer for capture, as DPIB write gets
1137 * completed earlier than the actual data written to the DDR.
1138 *
1139 * For capture stream following workaround is required to fix the
1140 * incorrect position reporting.
1141 *
1142 * 1. Wait for 20us before reading the DMA position in buffer once
1143 * the interrupt is generated for stream completion as update happens
1144 * on the HDA frame boundary i.e. 20.833uSec.
1145 * 2. Read DPIB register to flush the DMA position value. This dummy
1146 * read is required to flush DMA position value.
1147 * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1148 * or greater than period boundary.
1149 */
1150
1151 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1152 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1153 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1154 hdac_stream(hstream)->index));
1155 } else {
1156 udelay(20);
1157 readl(bus->remap_addr +
1158 AZX_REG_VS_SDXDPIB_XBASE +
1159 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1160 hdac_stream(hstream)->index));
1161 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1162 }
1163
1164 if (pos >= hdac_stream(hstream)->bufsize)
1165 pos = 0;
1166
1167 return bytes_to_frames(substream->runtime, pos);
1168 }
1169
skl_adjust_codec_delay(struct snd_pcm_substream * substream,u64 nsec)1170 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1171 u64 nsec)
1172 {
1173 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
1174 struct snd_soc_dai *codec_dai = rtd->codec_dai;
1175 u64 codec_frames, codec_nsecs;
1176
1177 if (!codec_dai->driver->ops->delay)
1178 return nsec;
1179
1180 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1181 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1182 substream->runtime->rate);
1183
1184 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1185 return nsec + codec_nsecs;
1186
1187 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1188 }
1189
skl_get_time_info(struct snd_pcm_substream * substream,struct timespec * system_ts,struct timespec * audio_ts,struct snd_pcm_audio_tstamp_config * audio_tstamp_config,struct snd_pcm_audio_tstamp_report * audio_tstamp_report)1190 static int skl_get_time_info(struct snd_pcm_substream *substream,
1191 struct timespec *system_ts, struct timespec *audio_ts,
1192 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1193 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1194 {
1195 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1196 struct hdac_stream *hstr = hdac_stream(sstream);
1197 u64 nsec;
1198
1199 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1200 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1201
1202 snd_pcm_gettime(substream->runtime, system_ts);
1203
1204 nsec = timecounter_read(&hstr->tc);
1205 nsec = div_u64(nsec, 3); /* can be optimized */
1206 if (audio_tstamp_config->report_delay)
1207 nsec = skl_adjust_codec_delay(substream, nsec);
1208
1209 *audio_ts = ns_to_timespec(nsec);
1210
1211 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1212 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1213 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1214
1215 } else {
1216 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1217 }
1218
1219 return 0;
1220 }
1221
1222 static const struct snd_pcm_ops skl_platform_ops = {
1223 .open = skl_platform_open,
1224 .ioctl = snd_pcm_lib_ioctl,
1225 .trigger = skl_platform_pcm_trigger,
1226 .pointer = skl_platform_pcm_pointer,
1227 .get_time_info = skl_get_time_info,
1228 .mmap = snd_pcm_lib_default_mmap,
1229 .page = snd_pcm_sgbuf_ops_page,
1230 };
1231
skl_pcm_free(struct snd_pcm * pcm)1232 static void skl_pcm_free(struct snd_pcm *pcm)
1233 {
1234 snd_pcm_lib_preallocate_free_for_all(pcm);
1235 }
1236
1237 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
1238
skl_pcm_new(struct snd_soc_pcm_runtime * rtd)1239 static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
1240 {
1241 struct snd_soc_dai *dai = rtd->cpu_dai;
1242 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1243 struct snd_pcm *pcm = rtd->pcm;
1244 unsigned int size;
1245 int retval = 0;
1246 struct skl *skl = bus_to_skl(bus);
1247
1248 if (dai->driver->playback.channels_min ||
1249 dai->driver->capture.channels_min) {
1250 /* buffer pre-allocation */
1251 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1252 if (size > MAX_PREALLOC_SIZE)
1253 size = MAX_PREALLOC_SIZE;
1254 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
1255 SNDRV_DMA_TYPE_DEV_SG,
1256 snd_dma_pci_data(skl->pci),
1257 size, MAX_PREALLOC_SIZE);
1258 if (retval) {
1259 dev_err(dai->dev, "dma buffer allocation fail\n");
1260 return retval;
1261 }
1262 }
1263
1264 return retval;
1265 }
1266
skl_get_module_info(struct skl * skl,struct skl_module_cfg * mconfig)1267 static int skl_get_module_info(struct skl *skl, struct skl_module_cfg *mconfig)
1268 {
1269 struct skl_sst *ctx = skl->skl_sst;
1270 struct skl_module_inst_id *pin_id;
1271 uuid_le *uuid_mod, *uuid_tplg;
1272 struct skl_module *skl_module;
1273 struct uuid_module *module;
1274 int i, ret = -EIO;
1275
1276 uuid_mod = (uuid_le *)mconfig->guid;
1277
1278 if (list_empty(&ctx->uuid_list)) {
1279 dev_err(ctx->dev, "Module list is empty\n");
1280 return -EIO;
1281 }
1282
1283 list_for_each_entry(module, &ctx->uuid_list, list) {
1284 if (uuid_le_cmp(*uuid_mod, module->uuid) == 0) {
1285 mconfig->id.module_id = module->id;
1286 if (mconfig->module)
1287 mconfig->module->loadable = module->is_loadable;
1288 ret = 0;
1289 break;
1290 }
1291 }
1292
1293 if (ret)
1294 return ret;
1295
1296 uuid_mod = &module->uuid;
1297 ret = -EIO;
1298 for (i = 0; i < skl->nr_modules; i++) {
1299 skl_module = skl->modules[i];
1300 uuid_tplg = &skl_module->uuid;
1301 if (!uuid_le_cmp(*uuid_mod, *uuid_tplg)) {
1302 mconfig->module = skl_module;
1303 ret = 0;
1304 break;
1305 }
1306 }
1307 if (skl->nr_modules && ret)
1308 return ret;
1309
1310 list_for_each_entry(module, &ctx->uuid_list, list) {
1311 for (i = 0; i < MAX_IN_QUEUE; i++) {
1312 pin_id = &mconfig->m_in_pin[i].id;
1313 if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid))
1314 pin_id->module_id = module->id;
1315 }
1316
1317 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1318 pin_id = &mconfig->m_out_pin[i].id;
1319 if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid))
1320 pin_id->module_id = module->id;
1321 }
1322 }
1323
1324 return 0;
1325 }
1326
skl_populate_modules(struct skl * skl)1327 static int skl_populate_modules(struct skl *skl)
1328 {
1329 struct skl_pipeline *p;
1330 struct skl_pipe_module *m;
1331 struct snd_soc_dapm_widget *w;
1332 struct skl_module_cfg *mconfig;
1333 int ret = 0;
1334
1335 list_for_each_entry(p, &skl->ppl_list, node) {
1336 list_for_each_entry(m, &p->pipe->w_list, node) {
1337 w = m->w;
1338 mconfig = w->priv;
1339
1340 ret = skl_get_module_info(skl, mconfig);
1341 if (ret < 0) {
1342 dev_err(skl->skl_sst->dev,
1343 "query module info failed\n");
1344 return ret;
1345 }
1346
1347 skl_tplg_add_moduleid_in_bind_params(skl, w);
1348 }
1349 }
1350
1351 return ret;
1352 }
1353
skl_platform_soc_probe(struct snd_soc_component * component)1354 static int skl_platform_soc_probe(struct snd_soc_component *component)
1355 {
1356 struct hdac_bus *bus = dev_get_drvdata(component->dev);
1357 struct skl *skl = bus_to_skl(bus);
1358 const struct skl_dsp_ops *ops;
1359 int ret;
1360
1361 pm_runtime_get_sync(component->dev);
1362 if (bus->ppcap) {
1363 skl->component = component;
1364
1365 /* init debugfs */
1366 skl->debugfs = skl_debugfs_init(skl);
1367
1368 ret = skl_tplg_init(component, bus);
1369 if (ret < 0) {
1370 dev_err(component->dev, "Failed to init topology!\n");
1371 return ret;
1372 }
1373
1374 /* load the firmwares, since all is set */
1375 ops = skl_get_dsp_ops(skl->pci->device);
1376 if (!ops)
1377 return -EIO;
1378
1379 if (skl->skl_sst->is_first_boot == false) {
1380 dev_err(component->dev, "DSP reports first boot done!!!\n");
1381 return -EIO;
1382 }
1383
1384 /*
1385 * Disable dynamic clock and power gating during firmware
1386 * and library download
1387 */
1388 skl->skl_sst->enable_miscbdcge(component->dev, false);
1389 skl->skl_sst->clock_power_gating(component->dev, false);
1390
1391 ret = ops->init_fw(component->dev, skl->skl_sst);
1392 skl->skl_sst->enable_miscbdcge(component->dev, true);
1393 skl->skl_sst->clock_power_gating(component->dev, true);
1394 if (ret < 0) {
1395 dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1396 return ret;
1397 }
1398 skl_populate_modules(skl);
1399 skl->skl_sst->update_d0i3c = skl_update_d0i3c;
1400 skl_dsp_enable_notification(skl->skl_sst, false);
1401
1402 if (skl->cfg.astate_cfg != NULL) {
1403 skl_dsp_set_astate_cfg(skl->skl_sst,
1404 skl->cfg.astate_cfg->count,
1405 skl->cfg.astate_cfg);
1406 }
1407 }
1408 pm_runtime_mark_last_busy(component->dev);
1409 pm_runtime_put_autosuspend(component->dev);
1410
1411 return 0;
1412 }
1413
1414 static const struct snd_soc_component_driver skl_component = {
1415 .name = "pcm",
1416 .probe = skl_platform_soc_probe,
1417 .ops = &skl_platform_ops,
1418 .pcm_new = skl_pcm_new,
1419 .pcm_free = skl_pcm_free,
1420 };
1421
skl_platform_register(struct device * dev)1422 int skl_platform_register(struct device *dev)
1423 {
1424 int ret;
1425 struct snd_soc_dai_driver *dais;
1426 int num_dais = ARRAY_SIZE(skl_platform_dai);
1427 struct hdac_bus *bus = dev_get_drvdata(dev);
1428 struct skl *skl = bus_to_skl(bus);
1429
1430 INIT_LIST_HEAD(&skl->ppl_list);
1431 INIT_LIST_HEAD(&skl->bind_list);
1432
1433 skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1434 GFP_KERNEL);
1435 if (!skl->dais) {
1436 ret = -ENOMEM;
1437 goto err;
1438 }
1439
1440 if (!skl->use_tplg_pcm) {
1441 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1442 sizeof(skl_platform_dai), GFP_KERNEL);
1443 if (!dais) {
1444 ret = -ENOMEM;
1445 goto err;
1446 }
1447
1448 skl->dais = dais;
1449 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1450 sizeof(skl_fe_dai));
1451 num_dais += ARRAY_SIZE(skl_fe_dai);
1452 }
1453
1454 ret = devm_snd_soc_register_component(dev, &skl_component,
1455 skl->dais, num_dais);
1456 if (ret)
1457 dev_err(dev, "soc component registration failed %d\n", ret);
1458 err:
1459 return ret;
1460 }
1461
skl_platform_unregister(struct device * dev)1462 int skl_platform_unregister(struct device *dev)
1463 {
1464 struct hdac_bus *bus = dev_get_drvdata(dev);
1465 struct skl *skl = bus_to_skl(bus);
1466 struct skl_module_deferred_bind *modules, *tmp;
1467
1468 if (!list_empty(&skl->bind_list)) {
1469 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1470 list_del(&modules->node);
1471 kfree(modules);
1472 }
1473 }
1474
1475 kfree(skl->dais);
1476
1477 return 0;
1478 }
1479
