1 /*
2 * NAU88L24 ALSA SoC audio driver
3 *
4 * Copyright 2016 Nuvoton Technology Corp.
5 * Author: John Hsu <KCHSU0@nuvoton.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/acpi.h>
20 #include <linux/math64.h>
21 #include <linux/semaphore.h>
22
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30
31 #include "nau8824.h"
32
33
34 static int nau8824_config_sysclk(struct nau8824 *nau8824,
35 int clk_id, unsigned int freq);
36 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);
37
38 /* the ADC threshold of headset */
39 #define DMIC_CLK 3072000
40
41 /* the ADC threshold of headset */
42 #define HEADSET_SARADC_THD 0x80
43
44 /* the parameter threshold of FLL */
45 #define NAU_FREF_MAX 13500000
46 #define NAU_FVCO_MAX 100000000
47 #define NAU_FVCO_MIN 90000000
48
49 /* scaling for mclk from sysclk_src output */
50 static const struct nau8824_fll_attr mclk_src_scaling[] = {
51 { 1, 0x0 },
52 { 2, 0x2 },
53 { 4, 0x3 },
54 { 8, 0x4 },
55 { 16, 0x5 },
56 { 32, 0x6 },
57 { 3, 0x7 },
58 { 6, 0xa },
59 { 12, 0xb },
60 { 24, 0xc },
61 };
62
63 /* ratio for input clk freq */
64 static const struct nau8824_fll_attr fll_ratio[] = {
65 { 512000, 0x01 },
66 { 256000, 0x02 },
67 { 128000, 0x04 },
68 { 64000, 0x08 },
69 { 32000, 0x10 },
70 { 8000, 0x20 },
71 { 4000, 0x40 },
72 };
73
74 static const struct nau8824_fll_attr fll_pre_scalar[] = {
75 { 1, 0x0 },
76 { 2, 0x1 },
77 { 4, 0x2 },
78 { 8, 0x3 },
79 };
80
81 /* the maximum frequency of CLK_ADC and CLK_DAC */
82 #define CLK_DA_AD_MAX 6144000
83
84 /* over sampling rate */
85 static const struct nau8824_osr_attr osr_dac_sel[] = {
86 { 64, 2 }, /* OSR 64, SRC 1/4 */
87 { 256, 0 }, /* OSR 256, SRC 1 */
88 { 128, 1 }, /* OSR 128, SRC 1/2 */
89 { 0, 0 },
90 { 32, 3 }, /* OSR 32, SRC 1/8 */
91 };
92
93 static const struct nau8824_osr_attr osr_adc_sel[] = {
94 { 32, 3 }, /* OSR 32, SRC 1/8 */
95 { 64, 2 }, /* OSR 64, SRC 1/4 */
96 { 128, 1 }, /* OSR 128, SRC 1/2 */
97 { 256, 0 }, /* OSR 256, SRC 1 */
98 };
99
100 static const struct reg_default nau8824_reg_defaults[] = {
101 { NAU8824_REG_ENA_CTRL, 0x0000 },
102 { NAU8824_REG_CLK_GATING_ENA, 0x0000 },
103 { NAU8824_REG_CLK_DIVIDER, 0x0000 },
104 { NAU8824_REG_FLL1, 0x0000 },
105 { NAU8824_REG_FLL2, 0x3126 },
106 { NAU8824_REG_FLL3, 0x0008 },
107 { NAU8824_REG_FLL4, 0x0010 },
108 { NAU8824_REG_FLL5, 0xC000 },
109 { NAU8824_REG_FLL6, 0x6000 },
110 { NAU8824_REG_FLL_VCO_RSV, 0xF13C },
111 { NAU8824_REG_JACK_DET_CTRL, 0x0000 },
112 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 },
113 { NAU8824_REG_IRQ, 0x0000 },
114 { NAU8824_REG_CLEAR_INT_REG, 0x0000 },
115 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 },
116 { NAU8824_REG_SAR_ADC, 0x0015 },
117 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 },
118 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 },
119 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 },
120 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 },
121 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 },
122 { NAU8824_REG_GPIO_SEL, 0x0000 },
123 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B },
124 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 },
125 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 },
126 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 },
127 { NAU8824_REG_TDM_CTRL, 0x0000 },
128 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 },
129 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 },
130 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 },
131 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 },
132 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 },
133 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 },
134 { NAU8824_REG_EQ1_LOW, 0x112C },
135 { NAU8824_REG_EQ2_EQ3, 0x2C2C },
136 { NAU8824_REG_EQ4_EQ5, 0x2C2C },
137 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 },
138 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 },
139 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 },
140 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 },
141 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 },
142 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 },
143 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 },
144 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 },
145 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 },
146 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 },
147 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF },
148 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 },
149 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 },
150 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 },
151 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF },
152 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 },
153 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 },
154 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 },
155 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 },
156 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 },
157 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 },
158 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 },
159 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 },
160 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 },
161 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 },
162 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 },
163 { NAU8824_REG_MODE, 0x0000 },
164 { NAU8824_REG_MODE1, 0x0000 },
165 { NAU8824_REG_MODE2, 0x0000 },
166 { NAU8824_REG_CLASSG, 0x0000 },
167 { NAU8824_REG_OTP_EFUSE, 0x0000 },
168 { NAU8824_REG_OTPDOUT_1, 0x0000 },
169 { NAU8824_REG_OTPDOUT_2, 0x0000 },
170 { NAU8824_REG_MISC_CTRL, 0x0000 },
171 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF },
172 { NAU8824_REG_TEST_MODE, 0x0000 },
173 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 },
174 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF },
175 { NAU8824_REG_BIAS_ADJ, 0x0000 },
176 { NAU8824_REG_PGA_GAIN, 0x0000 },
177 { NAU8824_REG_TRIM_SETTINGS, 0x0000 },
178 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 },
179 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 },
180 { NAU8824_REG_ENABLE_LO, 0x0000 },
181 { NAU8824_REG_GAIN_LO, 0x0000 },
182 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 },
183 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 },
184 { NAU8824_REG_ANALOG_ADC_1, 0x0011 },
185 { NAU8824_REG_ANALOG_ADC_2, 0x0020 },
186 { NAU8824_REG_RDAC, 0x0008 },
187 { NAU8824_REG_MIC_BIAS, 0x0006 },
188 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 },
189 { NAU8824_REG_BOOST, 0x0000 },
190 { NAU8824_REG_FEPGA, 0x0000 },
191 { NAU8824_REG_FEPGA_II, 0x0000 },
192 { NAU8824_REG_FEPGA_SE, 0x0000 },
193 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 },
194 { NAU8824_REG_ATT_PORT0, 0x0000 },
195 { NAU8824_REG_ATT_PORT1, 0x0000 },
196 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 },
197 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 },
198 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 },
199 };
200
nau8824_sema_acquire(struct nau8824 * nau8824,long timeout)201 static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout)
202 {
203 int ret;
204
205 if (timeout) {
206 ret = down_timeout(&nau8824->jd_sem, timeout);
207 if (ret < 0)
208 dev_warn(nau8824->dev, "Acquire semaphore timeout\n");
209 } else {
210 ret = down_interruptible(&nau8824->jd_sem);
211 if (ret < 0)
212 dev_warn(nau8824->dev, "Acquire semaphore fail\n");
213 }
214
215 return ret;
216 }
217
nau8824_sema_release(struct nau8824 * nau8824)218 static inline void nau8824_sema_release(struct nau8824 *nau8824)
219 {
220 up(&nau8824->jd_sem);
221 }
222
nau8824_readable_reg(struct device * dev,unsigned int reg)223 static bool nau8824_readable_reg(struct device *dev, unsigned int reg)
224 {
225 switch (reg) {
226 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV:
227 case NAU8824_REG_JACK_DET_CTRL:
228 case NAU8824_REG_INTERRUPT_SETTING_1:
229 case NAU8824_REG_IRQ:
230 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
231 case NAU8824_REG_GPIO_SEL:
232 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
233 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
234 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
235 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3:
236 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1:
237 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
238 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
239 case NAU8824_REG_I2C_TIMEOUT:
240 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
241 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
242 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
243 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT:
244 return true;
245 default:
246 return false;
247 }
248
249 }
250
nau8824_writeable_reg(struct device * dev,unsigned int reg)251 static bool nau8824_writeable_reg(struct device *dev, unsigned int reg)
252 {
253 switch (reg) {
254 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV:
255 case NAU8824_REG_JACK_DET_CTRL:
256 case NAU8824_REG_INTERRUPT_SETTING_1:
257 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
258 case NAU8824_REG_GPIO_SEL:
259 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
260 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
261 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
262 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01:
263 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01:
264 case NAU8824_REG_DRC_SLOPE_ADC_CH01:
265 case NAU8824_REG_DRC_ATKDCY_ADC_CH01:
266 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23:
267 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23:
268 case NAU8824_REG_DRC_SLOPE_ADC_CH23:
269 case NAU8824_REG_DRC_ATKDCY_ADC_CH23:
270 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC:
271 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
272 case NAU8824_REG_I2C_TIMEOUT:
273 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
274 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
275 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL:
276 return true;
277 default:
278 return false;
279 }
280 }
281
nau8824_volatile_reg(struct device * dev,unsigned int reg)282 static bool nau8824_volatile_reg(struct device *dev, unsigned int reg)
283 {
284 switch (reg) {
285 case NAU8824_REG_RESET:
286 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG:
287 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3:
288 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1:
289 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
290 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
291 case NAU8824_REG_CHARGE_PUMP_INPUT:
292 return true;
293 default:
294 return false;
295 }
296 }
297
298 static const char * const nau8824_companding[] = {
299 "Off", "NC", "u-law", "A-law" };
300
301 static const struct soc_enum nau8824_companding_adc_enum =
302 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12,
303 ARRAY_SIZE(nau8824_companding), nau8824_companding);
304
305 static const struct soc_enum nau8824_companding_dac_enum =
306 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14,
307 ARRAY_SIZE(nau8824_companding), nau8824_companding);
308
309 static const char * const nau8824_adc_decimation[] = {
310 "32", "64", "128", "256" };
311
312 static const struct soc_enum nau8824_adc_decimation_enum =
313 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0,
314 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation);
315
316 static const char * const nau8824_dac_oversampl[] = {
317 "64", "256", "128", "", "32" };
318
319 static const struct soc_enum nau8824_dac_oversampl_enum =
320 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0,
321 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl);
322
323 static const char * const nau8824_input_channel[] = {
324 "Input CH0", "Input CH1", "Input CH2", "Input CH3" };
325
326 static const struct soc_enum nau8824_adc_ch0_enum =
327 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9,
328 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
329
330 static const struct soc_enum nau8824_adc_ch1_enum =
331 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9,
332 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
333
334 static const struct soc_enum nau8824_adc_ch2_enum =
335 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9,
336 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
337
338 static const struct soc_enum nau8824_adc_ch3_enum =
339 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9,
340 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
341
342 static const char * const nau8824_tdm_slot[] = {
343 "Slot 0", "Slot 1", "Slot 2", "Slot 3" };
344
345 static const struct soc_enum nau8824_dac_left_sel_enum =
346 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6,
347 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
348
349 static const struct soc_enum nau8824_dac_right_sel_enum =
350 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4,
351 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
352
353 static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400);
354 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0);
355 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0);
356 static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0);
357
358 static const struct snd_kcontrol_new nau8824_snd_controls[] = {
359 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum),
360 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum),
361
362 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum),
363 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum),
364
365 SOC_SINGLE_TLV("Speaker Right DACR Volume",
366 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv),
367 SOC_SINGLE_TLV("Speaker Left DACL Volume",
368 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv),
369 SOC_SINGLE_TLV("Speaker Left DACR Volume",
370 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv),
371 SOC_SINGLE_TLV("Speaker Right DACL Volume",
372 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv),
373
374 SOC_SINGLE_TLV("Headphone Right DACR Volume",
375 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv),
376 SOC_SINGLE_TLV("Headphone Left DACL Volume",
377 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv),
378 SOC_SINGLE_TLV("Headphone Right DACL Volume",
379 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv),
380 SOC_SINGLE_TLV("Headphone Left DACR Volume",
381 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv),
382
383 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II,
384 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv),
385 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II,
386 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv),
387
388 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL,
389 0, 0x164, 0, dmic_vol_tlv),
390 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL,
391 0, 0x164, 0, dmic_vol_tlv),
392 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL,
393 0, 0x164, 0, dmic_vol_tlv),
394 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL,
395 0, 0x164, 0, dmic_vol_tlv),
396
397 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum),
398 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum),
399 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum),
400 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum),
401
402 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0),
403 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0),
404 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0),
405 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0),
406
407 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum),
408 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum),
409
410 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0),
411 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0),
412
413 SOC_SINGLE("THD for key media",
414 NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0),
415 SOC_SINGLE("THD for key voice command",
416 NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0),
417 SOC_SINGLE("THD for key volume up",
418 NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0),
419 SOC_SINGLE("THD for key volume down",
420 NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0),
421 };
422
nau8824_output_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)423 static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w,
424 struct snd_kcontrol *kcontrol, int event)
425 {
426 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
427 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
428
429 switch (event) {
430 case SND_SOC_DAPM_PRE_PMU:
431 /* Disables the TESTDAC to let DAC signal pass through. */
432 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
433 NAU8824_TEST_DAC_EN, 0);
434 break;
435 case SND_SOC_DAPM_POST_PMD:
436 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
437 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
438 break;
439 default:
440 return -EINVAL;
441 }
442
443 return 0;
444 }
445
nau8824_spk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)446 static int nau8824_spk_event(struct snd_soc_dapm_widget *w,
447 struct snd_kcontrol *kcontrol, int event)
448 {
449 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
450 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
451
452 switch (event) {
453 case SND_SOC_DAPM_PRE_PMU:
454 regmap_update_bits(nau8824->regmap,
455 NAU8824_REG_ANALOG_CONTROL_2,
456 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS);
457 break;
458 case SND_SOC_DAPM_POST_PMD:
459 regmap_update_bits(nau8824->regmap,
460 NAU8824_REG_ANALOG_CONTROL_2,
461 NAU8824_CLASSD_CLAMP_DIS, 0);
462 break;
463 default:
464 return -EINVAL;
465 }
466
467 return 0;
468 }
469
nau8824_pump_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)470 static int nau8824_pump_event(struct snd_soc_dapm_widget *w,
471 struct snd_kcontrol *kcontrol, int event)
472 {
473 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
474 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
475
476 switch (event) {
477 case SND_SOC_DAPM_POST_PMU:
478 /* Prevent startup click by letting charge pump to ramp up */
479 msleep(10);
480 regmap_update_bits(nau8824->regmap,
481 NAU8824_REG_CHARGE_PUMP_CONTROL,
482 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW);
483 break;
484 case SND_SOC_DAPM_PRE_PMD:
485 regmap_update_bits(nau8824->regmap,
486 NAU8824_REG_CHARGE_PUMP_CONTROL,
487 NAU8824_JAMNODCLOW, 0);
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 return 0;
494 }
495
system_clock_control(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)496 static int system_clock_control(struct snd_soc_dapm_widget *w,
497 struct snd_kcontrol *k, int event)
498 {
499 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
500 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
501 struct regmap *regmap = nau8824->regmap;
502 unsigned int value;
503 bool clk_fll, error;
504
505 if (SND_SOC_DAPM_EVENT_OFF(event)) {
506 dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");
507 /* Set clock source to disable or internal clock before the
508 * playback or capture end. Codec needs clock for Jack
509 * detection and button press if jack inserted; otherwise,
510 * the clock should be closed.
511 */
512 if (nau8824_is_jack_inserted(nau8824)) {
513 nau8824_config_sysclk(nau8824,
514 NAU8824_CLK_INTERNAL, 0);
515 } else {
516 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
517 }
518 } else {
519 dev_dbg(nau8824->dev, "system clock control : POWER ON\n");
520 /* Check the clock source setting is proper or not
521 * no matter the source is from FLL or MCLK.
522 */
523 regmap_read(regmap, NAU8824_REG_FLL1, &value);
524 clk_fll = value & NAU8824_FLL_RATIO_MASK;
525 /* It's error to use internal clock when playback */
526 regmap_read(regmap, NAU8824_REG_FLL6, &value);
527 error = value & NAU8824_DCO_EN;
528 if (!error) {
529 /* Check error depending on source is FLL or MCLK. */
530 regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value);
531 if (clk_fll)
532 error = !(value & NAU8824_CLK_SRC_VCO);
533 else
534 error = value & NAU8824_CLK_SRC_VCO;
535 }
536 /* Recover the clock source setting if error. */
537 if (error) {
538 if (clk_fll) {
539 regmap_update_bits(regmap,
540 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
541 regmap_update_bits(regmap,
542 NAU8824_REG_CLK_DIVIDER,
543 NAU8824_CLK_SRC_MASK,
544 NAU8824_CLK_SRC_VCO);
545 } else {
546 nau8824_config_sysclk(nau8824,
547 NAU8824_CLK_MCLK, 0);
548 }
549 }
550 }
551
552 return 0;
553 }
554
dmic_clock_control(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)555 static int dmic_clock_control(struct snd_soc_dapm_widget *w,
556 struct snd_kcontrol *k, int event)
557 {
558 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
559 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
560 int src;
561
562 /* The DMIC clock is gotten from system clock (256fs) divided by
563 * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or
564 * less than 3.072 MHz.
565 */
566 for (src = 0; src < 5; src++) {
567 if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK)
568 break;
569 }
570 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256);
571 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
572 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT));
573
574 return 0;
575 }
576
577 static const struct snd_kcontrol_new nau8824_adc_ch0_dmic =
578 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
579 NAU8824_ADC_CH0_DMIC_SFT, 1, 0);
580
581 static const struct snd_kcontrol_new nau8824_adc_ch1_dmic =
582 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
583 NAU8824_ADC_CH1_DMIC_SFT, 1, 0);
584
585 static const struct snd_kcontrol_new nau8824_adc_ch2_dmic =
586 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
587 NAU8824_ADC_CH2_DMIC_SFT, 1, 0);
588
589 static const struct snd_kcontrol_new nau8824_adc_ch3_dmic =
590 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
591 NAU8824_ADC_CH3_DMIC_SFT, 1, 0);
592
593 static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = {
594 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
595 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0),
596 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
597 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0),
598 };
599
600 static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = {
601 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
602 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0),
603 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
604 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0),
605 };
606
607 static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = {
608 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
609 NAU8824_DACR_HPL_EN_SFT, 1, 0),
610 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
611 NAU8824_DACL_HPL_EN_SFT, 1, 0),
612 };
613
614 static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = {
615 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
616 NAU8824_DACL_HPR_EN_SFT, 1, 0),
617 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
618 NAU8824_DACR_HPR_EN_SFT, 1, 0),
619 };
620
621 static const char * const nau8824_dac_src[] = { "DACL", "DACR" };
622
623 static SOC_ENUM_SINGLE_DECL(
624 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
625 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src);
626
627 static SOC_ENUM_SINGLE_DECL(
628 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
629 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src);
630
631 static const struct snd_kcontrol_new nau8824_dacl_mux =
632 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum);
633
634 static const struct snd_kcontrol_new nau8824_dacr_mux =
635 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum);
636
637
638 static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = {
639 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
640 system_clock_control, SND_SOC_DAPM_POST_PMD |
641 SND_SOC_DAPM_POST_PMU),
642
643 SND_SOC_DAPM_INPUT("HSMIC1"),
644 SND_SOC_DAPM_INPUT("HSMIC2"),
645 SND_SOC_DAPM_INPUT("MIC1"),
646 SND_SOC_DAPM_INPUT("MIC2"),
647 SND_SOC_DAPM_INPUT("DMIC1"),
648 SND_SOC_DAPM_INPUT("DMIC2"),
649 SND_SOC_DAPM_INPUT("DMIC3"),
650 SND_SOC_DAPM_INPUT("DMIC4"),
651
652 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC,
653 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0),
654 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS,
655 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0),
656 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ,
657 NAU8824_DMIC1_EN_SFT, 0, NULL, 0),
658 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ,
659 NAU8824_DMIC2_EN_SFT, 0, NULL, 0),
660 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
661 dmic_clock_control, SND_SOC_DAPM_POST_PMU),
662
663 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM,
664 0, 0, &nau8824_adc_ch0_dmic),
665 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM,
666 0, 0, &nau8824_adc_ch1_dmic),
667 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM,
668 0, 0, &nau8824_adc_ch2_dmic),
669 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM,
670 0, 0, &nau8824_adc_ch3_dmic),
671
672 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL,
673 12, 0, nau8824_adc_left_mixer,
674 ARRAY_SIZE(nau8824_adc_left_mixer)),
675 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL,
676 13, 0, nau8824_adc_right_mixer,
677 ARRAY_SIZE(nau8824_adc_right_mixer)),
678
679 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2,
680 NAU8824_ADCL_EN_SFT, 0),
681 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2,
682 NAU8824_ADCR_EN_SFT, 0),
683
684 SND_SOC_DAPM_AIF_OUT("AIFTX", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
685 SND_SOC_DAPM_AIF_IN("AIFRX", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
686
687 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC,
688 NAU8824_DACL_EN_SFT, 0),
689 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC,
690 NAU8824_DACL_CLK_SFT, 0, NULL, 0),
691 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC,
692 NAU8824_DACR_EN_SFT, 0),
693 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC,
694 NAU8824_DACR_CLK_SFT, 0, NULL, 0),
695
696 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux),
697 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux),
698
699 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
700 8, 1, nau8824_output_dac_event,
701 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
702 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
703 9, 1, nau8824_output_dac_event,
704 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
705
706 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1,
707 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event,
708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
709
710 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG,
711 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer,
712 ARRAY_SIZE(nau8824_hp_left_mixer)),
713 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG,
714 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer,
715 ARRAY_SIZE(nau8824_hp_right_mixer)),
716 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL,
717 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event,
718 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
719 SND_SOC_DAPM_PGA("Output Driver L",
720 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
721 SND_SOC_DAPM_PGA("Output Driver R",
722 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
723 SND_SOC_DAPM_PGA("Main Driver L",
724 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
725 SND_SOC_DAPM_PGA("Main Driver R",
726 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
727 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST,
728 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0),
729 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG,
730 NAU8824_CLASSG_EN_SFT, 0, NULL, 0),
731
732 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
733 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
734 SND_SOC_DAPM_OUTPUT("HPOL"),
735 SND_SOC_DAPM_OUTPUT("HPOR"),
736 };
737
738 static const struct snd_soc_dapm_route nau8824_dapm_routes[] = {
739 {"DMIC1 Enable", "Switch", "DMIC1"},
740 {"DMIC2 Enable", "Switch", "DMIC2"},
741 {"DMIC3 Enable", "Switch", "DMIC3"},
742 {"DMIC4 Enable", "Switch", "DMIC4"},
743
744 {"DMIC1", NULL, "DMIC12 Power"},
745 {"DMIC2", NULL, "DMIC12 Power"},
746 {"DMIC3", NULL, "DMIC34 Power"},
747 {"DMIC4", NULL, "DMIC34 Power"},
748 {"DMIC12 Power", NULL, "DMIC Clock"},
749 {"DMIC34 Power", NULL, "DMIC Clock"},
750
751 {"Left ADC", "MIC Switch", "MIC1"},
752 {"Left ADC", "HSMIC Switch", "HSMIC1"},
753 {"Right ADC", "MIC Switch", "MIC2"},
754 {"Right ADC", "HSMIC Switch", "HSMIC2"},
755
756 {"ADCL", NULL, "Left ADC"},
757 {"ADCR", NULL, "Right ADC"},
758
759 {"AIFTX", NULL, "MICBIAS"},
760 {"AIFTX", NULL, "ADCL"},
761 {"AIFTX", NULL, "ADCR"},
762 {"AIFTX", NULL, "DMIC1 Enable"},
763 {"AIFTX", NULL, "DMIC2 Enable"},
764 {"AIFTX", NULL, "DMIC3 Enable"},
765 {"AIFTX", NULL, "DMIC4 Enable"},
766
767 {"AIFTX", NULL, "System Clock"},
768 {"AIFRX", NULL, "System Clock"},
769
770 {"DACL", NULL, "AIFRX"},
771 {"DACL", NULL, "DACL Clock"},
772 {"DACR", NULL, "AIFRX"},
773 {"DACR", NULL, "DACR Clock"},
774
775 {"DACL Mux", "DACL", "DACL"},
776 {"DACL Mux", "DACR", "DACR"},
777 {"DACR Mux", "DACL", "DACL"},
778 {"DACR Mux", "DACR", "DACR"},
779
780 {"Output DACL", NULL, "DACL Mux"},
781 {"Output DACR", NULL, "DACR Mux"},
782
783 {"ClassD", NULL, "Output DACL"},
784 {"ClassD", NULL, "Output DACR"},
785
786 {"Left Headphone", "DAC Left Switch", "Output DACL"},
787 {"Left Headphone", "DAC Right Switch", "Output DACR"},
788 {"Right Headphone", "DAC Left Switch", "Output DACL"},
789 {"Right Headphone", "DAC Right Switch", "Output DACR"},
790
791 {"Charge Pump", NULL, "Left Headphone"},
792 {"Charge Pump", NULL, "Right Headphone"},
793 {"Output Driver L", NULL, "Charge Pump"},
794 {"Output Driver R", NULL, "Charge Pump"},
795 {"Main Driver L", NULL, "Output Driver L"},
796 {"Main Driver R", NULL, "Output Driver R"},
797 {"Class G", NULL, "Main Driver L"},
798 {"Class G", NULL, "Main Driver R"},
799 {"HP Boost Driver", NULL, "Class G"},
800
801 {"SPKOUTL", NULL, "ClassD"},
802 {"SPKOUTR", NULL, "ClassD"},
803 {"HPOL", NULL, "HP Boost Driver"},
804 {"HPOR", NULL, "HP Boost Driver"},
805 };
806
nau8824_is_jack_inserted(struct nau8824 * nau8824)807 static bool nau8824_is_jack_inserted(struct nau8824 *nau8824)
808 {
809 struct snd_soc_jack *jack = nau8824->jack;
810 bool insert = FALSE;
811
812 if (nau8824->irq && jack)
813 insert = jack->status & SND_JACK_HEADPHONE;
814
815 return insert;
816 }
817
nau8824_int_status_clear_all(struct regmap * regmap)818 static void nau8824_int_status_clear_all(struct regmap *regmap)
819 {
820 int active_irq, clear_irq, i;
821
822 /* Reset the intrruption status from rightmost bit if the corres-
823 * ponding irq event occurs.
824 */
825 regmap_read(regmap, NAU8824_REG_IRQ, &active_irq);
826 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) {
827 clear_irq = (0x1 << i);
828 if (active_irq & clear_irq)
829 regmap_write(regmap,
830 NAU8824_REG_CLEAR_INT_REG, clear_irq);
831 }
832 }
833
nau8824_eject_jack(struct nau8824 * nau8824)834 static void nau8824_eject_jack(struct nau8824 *nau8824)
835 {
836 struct snd_soc_dapm_context *dapm = nau8824->dapm;
837 struct regmap *regmap = nau8824->regmap;
838
839 /* Clear all interruption status */
840 nau8824_int_status_clear_all(regmap);
841
842 snd_soc_dapm_disable_pin(dapm, "SAR");
843 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
844 snd_soc_dapm_sync(dapm);
845
846 /* Enable the insertion interruption, disable the ejection
847 * interruption, and then bypass de-bounce circuit.
848 */
849 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
850 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
851 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS,
852 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
853 NAU8824_IRQ_EJECT_DIS);
854 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
855 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
856 NAU8824_IRQ_INSERT_EN);
857 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
858 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
859
860 /* Close clock for jack type detection at manual mode */
861 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
862 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
863 }
864
nau8824_jdet_work(struct work_struct * work)865 static void nau8824_jdet_work(struct work_struct *work)
866 {
867 struct nau8824 *nau8824 = container_of(
868 work, struct nau8824, jdet_work);
869 struct snd_soc_dapm_context *dapm = nau8824->dapm;
870 struct regmap *regmap = nau8824->regmap;
871 int adc_value, event = 0, event_mask = 0;
872
873 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
874 snd_soc_dapm_force_enable_pin(dapm, "SAR");
875 snd_soc_dapm_sync(dapm);
876
877 msleep(100);
878
879 regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value);
880 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK;
881 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value);
882 if (adc_value < HEADSET_SARADC_THD) {
883 event |= SND_JACK_HEADPHONE;
884
885 snd_soc_dapm_disable_pin(dapm, "SAR");
886 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
887 snd_soc_dapm_sync(dapm);
888 } else {
889 event |= SND_JACK_HEADSET;
890 }
891 event_mask |= SND_JACK_HEADSET;
892 snd_soc_jack_report(nau8824->jack, event, event_mask);
893
894 /* Enable short key press and release interruption. */
895 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
896 NAU8824_IRQ_KEY_RELEASE_DIS |
897 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
898
899 nau8824_sema_release(nau8824);
900 }
901
nau8824_setup_auto_irq(struct nau8824 * nau8824)902 static void nau8824_setup_auto_irq(struct nau8824 *nau8824)
903 {
904 struct regmap *regmap = nau8824->regmap;
905
906 /* Enable jack ejection interruption. */
907 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
908 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
909 NAU8824_IRQ_EJECT_EN);
910 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
911 NAU8824_IRQ_EJECT_DIS, 0);
912 /* Enable internal VCO needed for interruptions */
913 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
914 nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);
915 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
916 NAU8824_JD_SLEEP_MODE, 0);
917 }
918
nau8824_button_decode(int value)919 static int nau8824_button_decode(int value)
920 {
921 int buttons = 0;
922
923 /* The chip supports up to 8 buttons, but ALSA defines
924 * only 6 buttons.
925 */
926 if (value & BIT(0))
927 buttons |= SND_JACK_BTN_0;
928 if (value & BIT(1))
929 buttons |= SND_JACK_BTN_1;
930 if (value & BIT(2))
931 buttons |= SND_JACK_BTN_2;
932 if (value & BIT(3))
933 buttons |= SND_JACK_BTN_3;
934 if (value & BIT(4))
935 buttons |= SND_JACK_BTN_4;
936 if (value & BIT(5))
937 buttons |= SND_JACK_BTN_5;
938
939 return buttons;
940 }
941
942 #define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
943 SND_JACK_BTN_2 | SND_JACK_BTN_3)
944
nau8824_interrupt(int irq,void * data)945 static irqreturn_t nau8824_interrupt(int irq, void *data)
946 {
947 struct nau8824 *nau8824 = (struct nau8824 *)data;
948 struct regmap *regmap = nau8824->regmap;
949 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
950
951 if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) {
952 dev_err(nau8824->dev, "failed to read irq status\n");
953 return IRQ_NONE;
954 }
955 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq);
956
957 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) {
958 nau8824_eject_jack(nau8824);
959 event_mask |= SND_JACK_HEADSET;
960 clear_irq = NAU8824_JACK_EJECTION_DETECTED;
961 /* release semaphore held after resume,
962 * and cancel jack detection
963 */
964 nau8824_sema_release(nau8824);
965 cancel_work_sync(&nau8824->jdet_work);
966 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) {
967 int key_status, button_pressed;
968
969 regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG,
970 &key_status);
971
972 /* lower 8 bits of the register are for pressed keys */
973 button_pressed = nau8824_button_decode(key_status);
974
975 event |= button_pressed;
976 dev_dbg(nau8824->dev, "button %x pressed\n", event);
977 event_mask |= NAU8824_BUTTONS;
978 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ;
979 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) {
980 event_mask = NAU8824_BUTTONS;
981 clear_irq = NAU8824_KEY_RELEASE_IRQ;
982 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) {
983 /* Turn off insertion interruption at manual mode */
984 regmap_update_bits(regmap,
985 NAU8824_REG_INTERRUPT_SETTING,
986 NAU8824_IRQ_INSERT_DIS,
987 NAU8824_IRQ_INSERT_DIS);
988 regmap_update_bits(regmap,
989 NAU8824_REG_INTERRUPT_SETTING_1,
990 NAU8824_IRQ_INSERT_EN, 0);
991 /* detect microphone and jack type */
992 cancel_work_sync(&nau8824->jdet_work);
993 schedule_work(&nau8824->jdet_work);
994
995 /* Enable interruption for jack type detection at audo
996 * mode which can detect microphone and jack type.
997 */
998 nau8824_setup_auto_irq(nau8824);
999 }
1000
1001 if (!clear_irq)
1002 clear_irq = active_irq;
1003 /* clears the rightmost interruption */
1004 regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq);
1005
1006 if (event_mask)
1007 snd_soc_jack_report(nau8824->jack, event, event_mask);
1008
1009 return IRQ_HANDLED;
1010 }
1011
nau8824_clock_check(struct nau8824 * nau8824,int stream,int rate,int osr)1012 static int nau8824_clock_check(struct nau8824 *nau8824,
1013 int stream, int rate, int osr)
1014 {
1015 int osrate;
1016
1017 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1018 if (osr >= ARRAY_SIZE(osr_dac_sel))
1019 return -EINVAL;
1020 osrate = osr_dac_sel[osr].osr;
1021 } else {
1022 if (osr >= ARRAY_SIZE(osr_adc_sel))
1023 return -EINVAL;
1024 osrate = osr_adc_sel[osr].osr;
1025 }
1026
1027 if (!osrate || rate * osr > CLK_DA_AD_MAX) {
1028 dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
1029 return -EINVAL;
1030 }
1031
1032 return 0;
1033 }
1034
nau8824_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1035 static int nau8824_hw_params(struct snd_pcm_substream *substream,
1036 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1037 {
1038 struct snd_soc_component *component = dai->component;
1039 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1040 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div;
1041
1042 nau8824_sema_acquire(nau8824, HZ);
1043
1044 /* CLK_DAC or CLK_ADC = OSR * FS
1045 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
1046 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
1047 * values must be selected such that the maximum frequency is less
1048 * than 6.144 MHz.
1049 */
1050 nau8824->fs = params_rate(params);
1051 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1052 regmap_read(nau8824->regmap,
1053 NAU8824_REG_DAC_FILTER_CTRL_1, &osr);
1054 osr &= NAU8824_DAC_OVERSAMPLE_MASK;
1055 if (nau8824_clock_check(nau8824, substream->stream,
1056 nau8824->fs, osr))
1057 return -EINVAL;
1058 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1059 NAU8824_CLK_DAC_SRC_MASK,
1060 osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT);
1061 } else {
1062 regmap_read(nau8824->regmap,
1063 NAU8824_REG_ADC_FILTER_CTRL, &osr);
1064 osr &= NAU8824_ADC_SYNC_DOWN_MASK;
1065 if (nau8824_clock_check(nau8824, substream->stream,
1066 nau8824->fs, osr))
1067 return -EINVAL;
1068 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1069 NAU8824_CLK_ADC_SRC_MASK,
1070 osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT);
1071 }
1072
1073 /* make BCLK and LRC divde configuration if the codec as master. */
1074 regmap_read(nau8824->regmap,
1075 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val);
1076 if (ctrl_val & NAU8824_I2S_MS_MASTER) {
1077 /* get the bclk and fs ratio */
1078 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs;
1079 if (bclk_fs <= 32)
1080 bclk_div = 0x3;
1081 else if (bclk_fs <= 64)
1082 bclk_div = 0x2;
1083 else if (bclk_fs <= 128)
1084 bclk_div = 0x1;
1085 else if (bclk_fs <= 256)
1086 bclk_div = 0;
1087 else
1088 return -EINVAL;
1089 regmap_update_bits(nau8824->regmap,
1090 NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1091 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK,
1092 (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div);
1093 }
1094
1095 switch (params_width(params)) {
1096 case 16:
1097 val_len |= NAU8824_I2S_DL_16;
1098 break;
1099 case 20:
1100 val_len |= NAU8824_I2S_DL_20;
1101 break;
1102 case 24:
1103 val_len |= NAU8824_I2S_DL_24;
1104 break;
1105 case 32:
1106 val_len |= NAU8824_I2S_DL_32;
1107 break;
1108 default:
1109 return -EINVAL;
1110 }
1111
1112 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1113 NAU8824_I2S_DL_MASK, val_len);
1114
1115 nau8824_sema_release(nau8824);
1116
1117 return 0;
1118 }
1119
nau8824_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)1120 static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1121 {
1122 struct snd_soc_component *component = dai->component;
1123 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1124 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1125
1126 nau8824_sema_acquire(nau8824, HZ);
1127
1128 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1129 case SND_SOC_DAIFMT_CBM_CFM:
1130 ctrl2_val |= NAU8824_I2S_MS_MASTER;
1131 break;
1132 case SND_SOC_DAIFMT_CBS_CFS:
1133 break;
1134 default:
1135 return -EINVAL;
1136 }
1137
1138 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1139 case SND_SOC_DAIFMT_NB_NF:
1140 break;
1141 case SND_SOC_DAIFMT_IB_NF:
1142 ctrl1_val |= NAU8824_I2S_BP_INV;
1143 break;
1144 default:
1145 return -EINVAL;
1146 }
1147
1148 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1149 case SND_SOC_DAIFMT_I2S:
1150 ctrl1_val |= NAU8824_I2S_DF_I2S;
1151 break;
1152 case SND_SOC_DAIFMT_LEFT_J:
1153 ctrl1_val |= NAU8824_I2S_DF_LEFT;
1154 break;
1155 case SND_SOC_DAIFMT_RIGHT_J:
1156 ctrl1_val |= NAU8824_I2S_DF_RIGTH;
1157 break;
1158 case SND_SOC_DAIFMT_DSP_A:
1159 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
1160 break;
1161 case SND_SOC_DAIFMT_DSP_B:
1162 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
1163 ctrl1_val |= NAU8824_I2S_PCMB_EN;
1164 break;
1165 default:
1166 return -EINVAL;
1167 }
1168
1169 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1170 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK |
1171 NAU8824_I2S_PCMB_EN, ctrl1_val);
1172 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1173 NAU8824_I2S_MS_MASK, ctrl2_val);
1174
1175 nau8824_sema_release(nau8824);
1176
1177 return 0;
1178 }
1179
1180 /**
1181 * nau8824_set_tdm_slot - configure DAI TDM.
1182 * @dai: DAI
1183 * @tx_mask: Bitmask representing active TX slots. Ex.
1184 * 0xf for normal 4 channel TDM.
1185 * 0xf0 for shifted 4 channel TDM
1186 * @rx_mask: Bitmask [0:1] representing active DACR RX slots.
1187 * Bitmask [2:3] representing active DACL RX slots.
1188 * 00=CH0,01=CH1,10=CH2,11=CH3. Ex.
1189 * 0xf for DACL/R selecting TDM CH3.
1190 * 0xf0 for DACL/R selecting shifted TDM CH3.
1191 * @slots: Number of slots in use.
1192 * @slot_width: Width in bits for each slot.
1193 *
1194 * Configures a DAI for TDM operation. Only support 4 slots TDM.
1195 */
nau8824_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1196 static int nau8824_set_tdm_slot(struct snd_soc_dai *dai,
1197 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1198 {
1199 struct snd_soc_component *component = dai->component;
1200 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1201 unsigned int tslot_l = 0, ctrl_val = 0;
1202
1203 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) ||
1204 ((rx_mask & 0xf0) && (rx_mask & 0xf)) ||
1205 ((rx_mask & 0xf0) && (tx_mask & 0xf)) ||
1206 ((rx_mask & 0xf) && (tx_mask & 0xf0)))
1207 return -EINVAL;
1208
1209 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN);
1210 if (tx_mask & 0xf0) {
1211 tslot_l = 4 * slot_width;
1212 ctrl_val |= (tx_mask >> 4);
1213 } else {
1214 ctrl_val |= tx_mask;
1215 }
1216 if (rx_mask & 0xf0)
1217 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT);
1218 else
1219 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT);
1220
1221 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL,
1222 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN |
1223 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK |
1224 NAU8824_TDM_TX_MASK, ctrl_val);
1225 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT,
1226 NAU8824_TSLOT_L_MASK, tslot_l);
1227
1228 return 0;
1229 }
1230
1231 /**
1232 * nau8824_calc_fll_param - Calculate FLL parameters.
1233 * @fll_in: external clock provided to codec.
1234 * @fs: sampling rate.
1235 * @fll_param: Pointer to structure of FLL parameters.
1236 *
1237 * Calculate FLL parameters to configure codec.
1238 *
1239 * Returns 0 for success or negative error code.
1240 */
nau8824_calc_fll_param(unsigned int fll_in,unsigned int fs,struct nau8824_fll * fll_param)1241 static int nau8824_calc_fll_param(unsigned int fll_in,
1242 unsigned int fs, struct nau8824_fll *fll_param)
1243 {
1244 u64 fvco, fvco_max;
1245 unsigned int fref, i, fvco_sel;
1246
1247 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1248 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1249 * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK
1250 */
1251 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1252 fref = fll_in / fll_pre_scalar[i].param;
1253 if (fref <= NAU_FREF_MAX)
1254 break;
1255 }
1256 if (i == ARRAY_SIZE(fll_pre_scalar))
1257 return -EINVAL;
1258 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1259
1260 /* Choose the FLL ratio based on FREF */
1261 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1262 if (fref >= fll_ratio[i].param)
1263 break;
1264 }
1265 if (i == ARRAY_SIZE(fll_ratio))
1266 return -EINVAL;
1267 fll_param->ratio = fll_ratio[i].val;
1268
1269 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1270 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1271 * guaranteed across the full range of operation.
1272 * FDCO = freq_out * 2 * mclk_src_scaling
1273 */
1274 fvco_max = 0;
1275 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1276 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1277 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1278 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1279 fvco_max < fvco) {
1280 fvco_max = fvco;
1281 fvco_sel = i;
1282 }
1283 }
1284 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1285 return -EINVAL;
1286 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1287
1288 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1289 * input based on FDCO, FREF and FLL ratio.
1290 */
1291 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
1292 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1293 fll_param->fll_frac = fvco & 0xFFFF;
1294 return 0;
1295 }
1296
nau8824_fll_apply(struct regmap * regmap,struct nau8824_fll * fll_param)1297 static void nau8824_fll_apply(struct regmap *regmap,
1298 struct nau8824_fll *fll_param)
1299 {
1300 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1301 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK,
1302 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src);
1303 regmap_update_bits(regmap, NAU8824_REG_FLL1,
1304 NAU8824_FLL_RATIO_MASK, fll_param->ratio);
1305 /* FLL 16-bit fractional input */
1306 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac);
1307 /* FLL 10-bit integer input */
1308 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1309 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int);
1310 /* FLL pre-scaler */
1311 regmap_update_bits(regmap, NAU8824_REG_FLL4,
1312 NAU8824_FLL_REF_DIV_MASK,
1313 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT);
1314 /* select divided VCO input */
1315 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1316 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF);
1317 /* Disable free-running mode */
1318 regmap_update_bits(regmap,
1319 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
1320 if (fll_param->fll_frac) {
1321 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1322 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1323 NAU8824_FLL_FTR_SW_MASK,
1324 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1325 NAU8824_FLL_FTR_SW_FILTER);
1326 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1327 NAU8824_SDM_EN, NAU8824_SDM_EN);
1328 } else {
1329 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1330 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1331 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU);
1332 regmap_update_bits(regmap,
1333 NAU8824_REG_FLL6, NAU8824_SDM_EN, 0);
1334 }
1335 }
1336
1337 /* freq_out must be 256*Fs in order to achieve the best performance */
nau8824_set_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)1338 static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source,
1339 unsigned int freq_in, unsigned int freq_out)
1340 {
1341 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1342 struct nau8824_fll fll_param;
1343 int ret, fs;
1344
1345 fs = freq_out / 256;
1346 ret = nau8824_calc_fll_param(freq_in, fs, &fll_param);
1347 if (ret < 0) {
1348 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in);
1349 return ret;
1350 }
1351 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1352 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1353 fll_param.fll_int, fll_param.clk_ref_div);
1354
1355 nau8824_fll_apply(nau8824->regmap, &fll_param);
1356 mdelay(2);
1357 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1358 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
1359
1360 return 0;
1361 }
1362
nau8824_config_sysclk(struct nau8824 * nau8824,int clk_id,unsigned int freq)1363 static int nau8824_config_sysclk(struct nau8824 *nau8824,
1364 int clk_id, unsigned int freq)
1365 {
1366 struct regmap *regmap = nau8824->regmap;
1367
1368 switch (clk_id) {
1369 case NAU8824_CLK_DIS:
1370 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1371 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
1372 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1373 NAU8824_DCO_EN, 0);
1374 break;
1375
1376 case NAU8824_CLK_MCLK:
1377 nau8824_sema_acquire(nau8824, HZ);
1378 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1379 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
1380 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1381 NAU8824_DCO_EN, 0);
1382 nau8824_sema_release(nau8824);
1383 break;
1384
1385 case NAU8824_CLK_INTERNAL:
1386 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1387 NAU8824_DCO_EN, NAU8824_DCO_EN);
1388 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1389 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
1390 break;
1391
1392 case NAU8824_CLK_FLL_MCLK:
1393 nau8824_sema_acquire(nau8824, HZ);
1394 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1395 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK);
1396 nau8824_sema_release(nau8824);
1397 break;
1398
1399 case NAU8824_CLK_FLL_BLK:
1400 nau8824_sema_acquire(nau8824, HZ);
1401 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1402 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK);
1403 nau8824_sema_release(nau8824);
1404 break;
1405
1406 case NAU8824_CLK_FLL_FS:
1407 nau8824_sema_acquire(nau8824, HZ);
1408 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1409 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS);
1410 nau8824_sema_release(nau8824);
1411 break;
1412
1413 default:
1414 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id);
1415 return -EINVAL;
1416 }
1417
1418 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1419 clk_id);
1420
1421 return 0;
1422 }
1423
nau8824_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)1424 static int nau8824_set_sysclk(struct snd_soc_component *component,
1425 int clk_id, int source, unsigned int freq, int dir)
1426 {
1427 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1428
1429 return nau8824_config_sysclk(nau8824, clk_id, freq);
1430 }
1431
nau8824_resume_setup(struct nau8824 * nau8824)1432 static void nau8824_resume_setup(struct nau8824 *nau8824)
1433 {
1434 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
1435 if (nau8824->irq) {
1436 /* Clear all interruption status */
1437 nau8824_int_status_clear_all(nau8824->regmap);
1438 /* Enable jack detection at sleep mode, insertion detection,
1439 * and ejection detection.
1440 */
1441 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
1442 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
1443 regmap_update_bits(nau8824->regmap,
1444 NAU8824_REG_INTERRUPT_SETTING_1,
1445 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN,
1446 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN);
1447 regmap_update_bits(nau8824->regmap,
1448 NAU8824_REG_INTERRUPT_SETTING,
1449 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0);
1450 }
1451 }
1452
nau8824_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1453 static int nau8824_set_bias_level(struct snd_soc_component *component,
1454 enum snd_soc_bias_level level)
1455 {
1456 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1457
1458 switch (level) {
1459 case SND_SOC_BIAS_ON:
1460 break;
1461
1462 case SND_SOC_BIAS_PREPARE:
1463 break;
1464
1465 case SND_SOC_BIAS_STANDBY:
1466 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1467 /* Setup codec configuration after resume */
1468 nau8824_resume_setup(nau8824);
1469 }
1470 break;
1471
1472 case SND_SOC_BIAS_OFF:
1473 regmap_update_bits(nau8824->regmap,
1474 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
1475 regmap_update_bits(nau8824->regmap,
1476 NAU8824_REG_INTERRUPT_SETTING_1,
1477 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
1478 break;
1479 }
1480
1481 return 0;
1482 }
1483
nau8824_component_probe(struct snd_soc_component * component)1484 static int nau8824_component_probe(struct snd_soc_component *component)
1485 {
1486 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1487 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1488
1489 nau8824->dapm = dapm;
1490
1491 return 0;
1492 }
1493
nau8824_suspend(struct snd_soc_component * component)1494 static int __maybe_unused nau8824_suspend(struct snd_soc_component *component)
1495 {
1496 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1497
1498 if (nau8824->irq) {
1499 disable_irq(nau8824->irq);
1500 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1501 }
1502 regcache_cache_only(nau8824->regmap, true);
1503 regcache_mark_dirty(nau8824->regmap);
1504
1505 return 0;
1506 }
1507
nau8824_resume(struct snd_soc_component * component)1508 static int __maybe_unused nau8824_resume(struct snd_soc_component *component)
1509 {
1510 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1511
1512 regcache_cache_only(nau8824->regmap, false);
1513 regcache_sync(nau8824->regmap);
1514 if (nau8824->irq) {
1515 /* Hold semaphore to postpone playback happening
1516 * until jack detection done.
1517 */
1518 nau8824_sema_acquire(nau8824, 0);
1519 enable_irq(nau8824->irq);
1520 }
1521
1522 return 0;
1523 }
1524
1525 static const struct snd_soc_component_driver nau8824_component_driver = {
1526 .probe = nau8824_component_probe,
1527 .set_sysclk = nau8824_set_sysclk,
1528 .set_pll = nau8824_set_pll,
1529 .set_bias_level = nau8824_set_bias_level,
1530 .suspend = nau8824_suspend,
1531 .resume = nau8824_resume,
1532 .controls = nau8824_snd_controls,
1533 .num_controls = ARRAY_SIZE(nau8824_snd_controls),
1534 .dapm_widgets = nau8824_dapm_widgets,
1535 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets),
1536 .dapm_routes = nau8824_dapm_routes,
1537 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes),
1538 .suspend_bias_off = 1,
1539 .idle_bias_on = 1,
1540 .use_pmdown_time = 1,
1541 .endianness = 1,
1542 .non_legacy_dai_naming = 1,
1543 };
1544
1545 static const struct snd_soc_dai_ops nau8824_dai_ops = {
1546 .hw_params = nau8824_hw_params,
1547 .set_fmt = nau8824_set_fmt,
1548 .set_tdm_slot = nau8824_set_tdm_slot,
1549 };
1550
1551 #define NAU8824_RATES SNDRV_PCM_RATE_8000_192000
1552 #define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1553 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1554
1555 static struct snd_soc_dai_driver nau8824_dai = {
1556 .name = NAU8824_CODEC_DAI,
1557 .playback = {
1558 .stream_name = "Playback",
1559 .channels_min = 1,
1560 .channels_max = 2,
1561 .rates = NAU8824_RATES,
1562 .formats = NAU8824_FORMATS,
1563 },
1564 .capture = {
1565 .stream_name = "Capture",
1566 .channels_min = 1,
1567 .channels_max = 2,
1568 .rates = NAU8824_RATES,
1569 .formats = NAU8824_FORMATS,
1570 },
1571 .ops = &nau8824_dai_ops,
1572 };
1573
1574 static const struct regmap_config nau8824_regmap_config = {
1575 .val_bits = NAU8824_REG_ADDR_LEN,
1576 .reg_bits = NAU8824_REG_DATA_LEN,
1577
1578 .max_register = NAU8824_REG_MAX,
1579 .readable_reg = nau8824_readable_reg,
1580 .writeable_reg = nau8824_writeable_reg,
1581 .volatile_reg = nau8824_volatile_reg,
1582
1583 .cache_type = REGCACHE_RBTREE,
1584 .reg_defaults = nau8824_reg_defaults,
1585 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults),
1586 };
1587
1588 /**
1589 * nau8824_enable_jack_detect - Specify a jack for event reporting
1590 *
1591 * @component: component to register the jack with
1592 * @jack: jack to use to report headset and button events on
1593 *
1594 * After this function has been called the headset insert/remove and button
1595 * events will be routed to the given jack. Jack can be null to stop
1596 * reporting.
1597 */
nau8824_enable_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * jack)1598 int nau8824_enable_jack_detect(struct snd_soc_component *component,
1599 struct snd_soc_jack *jack)
1600 {
1601 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1602 int ret;
1603
1604 nau8824->jack = jack;
1605 /* Initiate jack detection work queue */
1606 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work);
1607 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL,
1608 nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1609 "nau8824", nau8824);
1610 if (ret) {
1611 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n",
1612 nau8824->irq, ret);
1613 }
1614
1615 return ret;
1616 }
1617 EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect);
1618
nau8824_reset_chip(struct regmap * regmap)1619 static void nau8824_reset_chip(struct regmap *regmap)
1620 {
1621 regmap_write(regmap, NAU8824_REG_RESET, 0x00);
1622 regmap_write(regmap, NAU8824_REG_RESET, 0x00);
1623 }
1624
nau8824_setup_buttons(struct nau8824 * nau8824)1625 static void nau8824_setup_buttons(struct nau8824 *nau8824)
1626 {
1627 struct regmap *regmap = nau8824->regmap;
1628
1629 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1630 NAU8824_SAR_TRACKING_GAIN_MASK,
1631 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT);
1632 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1633 NAU8824_SAR_COMPARE_TIME_MASK,
1634 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT);
1635 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1636 NAU8824_SAR_SAMPLING_TIME_MASK,
1637 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT);
1638
1639 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1640 NAU8824_LEVELS_NR_MASK,
1641 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT);
1642 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1643 NAU8824_HYSTERESIS_MASK,
1644 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT);
1645 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1646 NAU8824_SHORTKEY_DEBOUNCE_MASK,
1647 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT);
1648
1649 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1,
1650 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]);
1651 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2,
1652 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]);
1653 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3,
1654 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]);
1655 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4,
1656 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]);
1657 }
1658
nau8824_init_regs(struct nau8824 * nau8824)1659 static void nau8824_init_regs(struct nau8824 *nau8824)
1660 {
1661 struct regmap *regmap = nau8824->regmap;
1662
1663 /* Enable Bias/VMID/VMID Tieoff */
1664 regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ,
1665 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID |
1666 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT));
1667 regmap_update_bits(regmap, NAU8824_REG_BOOST,
1668 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN);
1669 mdelay(2);
1670 regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS,
1671 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage);
1672 /* Disable Boost Driver, Automatic Short circuit protection enable */
1673 regmap_update_bits(regmap, NAU8824_REG_BOOST,
1674 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
1675 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN,
1676 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
1677 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN);
1678 /* Scaling for ADC and DAC clock */
1679 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1680 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK,
1681 (0x1 << NAU8824_CLK_ADC_SRC_SFT) |
1682 (0x1 << NAU8824_CLK_DAC_SRC_SFT));
1683 regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL,
1684 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN);
1685 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
1686 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
1687 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
1688 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN,
1689 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
1690 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
1691 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN);
1692 regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA,
1693 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
1694 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
1695 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
1696 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN,
1697 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
1698 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
1699 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
1700 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN);
1701 /* Class G timer 64ms */
1702 regmap_update_bits(regmap, NAU8824_REG_CLASSG,
1703 NAU8824_CLASSG_TIMER_MASK,
1704 0x20 << NAU8824_CLASSG_TIMER_SFT);
1705 regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS,
1706 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC);
1707 /* Disable DACR/L power */
1708 regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL,
1709 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
1710 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL,
1711 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
1712 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL);
1713 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1714 * signal to avoid any glitches due to power up transients in both
1715 * the analog and digital DAC circuit.
1716 */
1717 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
1718 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
1719 /* Config L/R channel */
1720 regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
1721 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0);
1722 regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
1723 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1);
1724 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
1725 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN,
1726 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN);
1727 /* Default oversampling/decimations settings are unusable
1728 * (audible hiss). Set it to something better.
1729 */
1730 regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL,
1731 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64);
1732 regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1,
1733 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK,
1734 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64);
1735 /* DAC clock delay 2ns, VREF */
1736 regmap_update_bits(regmap, NAU8824_REG_RDAC,
1737 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK,
1738 (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) |
1739 (0x3 << NAU8824_RDAC_VREF_SFT));
1740 /* PGA input mode selection */
1741 regmap_update_bits(regmap, NAU8824_REG_FEPGA,
1742 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN,
1743 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN);
1744 /* Digital microphone control */
1745 regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1,
1746 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST,
1747 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST);
1748 regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL,
1749 NAU8824_JACK_LOGIC,
1750 /* jkdet_polarity - 1 is for active-low */
1751 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC);
1752 regmap_update_bits(regmap,
1753 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK,
1754 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT));
1755 if (nau8824->sar_threshold_num)
1756 nau8824_setup_buttons(nau8824);
1757 }
1758
nau8824_setup_irq(struct nau8824 * nau8824)1759 static int nau8824_setup_irq(struct nau8824 *nau8824)
1760 {
1761 /* Disable interruption before codec initiation done */
1762 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
1763 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
1764 regmap_update_bits(nau8824->regmap,
1765 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
1766 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1,
1767 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
1768
1769 return 0;
1770 }
1771
nau8824_print_device_properties(struct nau8824 * nau8824)1772 static void nau8824_print_device_properties(struct nau8824 *nau8824)
1773 {
1774 struct device *dev = nau8824->dev;
1775 int i;
1776
1777 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity);
1778 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage);
1779 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance);
1780
1781 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num);
1782 for (i = 0; i < nau8824->sar_threshold_num; i++)
1783 dev_dbg(dev, "sar-threshold[%d]=%x\n", i,
1784 nau8824->sar_threshold[i]);
1785
1786 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis);
1787 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage);
1788 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time);
1789 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time);
1790 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce);
1791 dev_dbg(dev, "jack-eject-debounce: %d\n",
1792 nau8824->jack_eject_debounce);
1793 }
1794
nau8824_read_device_properties(struct device * dev,struct nau8824 * nau8824)1795 static int nau8824_read_device_properties(struct device *dev,
1796 struct nau8824 *nau8824) {
1797 int ret;
1798
1799 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1800 &nau8824->jkdet_polarity);
1801 if (ret)
1802 nau8824->jkdet_polarity = 1;
1803 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1804 &nau8824->micbias_voltage);
1805 if (ret)
1806 nau8824->micbias_voltage = 6;
1807 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1808 &nau8824->vref_impedance);
1809 if (ret)
1810 nau8824->vref_impedance = 2;
1811 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
1812 &nau8824->sar_threshold_num);
1813 if (ret)
1814 nau8824->sar_threshold_num = 4;
1815 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
1816 nau8824->sar_threshold, nau8824->sar_threshold_num);
1817 if (ret) {
1818 nau8824->sar_threshold[0] = 0x0a;
1819 nau8824->sar_threshold[1] = 0x14;
1820 nau8824->sar_threshold[2] = 0x26;
1821 nau8824->sar_threshold[3] = 0x73;
1822 }
1823 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
1824 &nau8824->sar_hysteresis);
1825 if (ret)
1826 nau8824->sar_hysteresis = 0;
1827 ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
1828 &nau8824->sar_voltage);
1829 if (ret)
1830 nau8824->sar_voltage = 6;
1831 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
1832 &nau8824->sar_compare_time);
1833 if (ret)
1834 nau8824->sar_compare_time = 1;
1835 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
1836 &nau8824->sar_sampling_time);
1837 if (ret)
1838 nau8824->sar_sampling_time = 1;
1839 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
1840 &nau8824->key_debounce);
1841 if (ret)
1842 nau8824->key_debounce = 0;
1843 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1844 &nau8824->jack_eject_debounce);
1845 if (ret)
1846 nau8824->jack_eject_debounce = 1;
1847
1848 return 0;
1849 }
1850
nau8824_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1851 static int nau8824_i2c_probe(struct i2c_client *i2c,
1852 const struct i2c_device_id *id)
1853 {
1854 struct device *dev = &i2c->dev;
1855 struct nau8824 *nau8824 = dev_get_platdata(dev);
1856 int ret, value;
1857
1858 if (!nau8824) {
1859 nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL);
1860 if (!nau8824)
1861 return -ENOMEM;
1862 ret = nau8824_read_device_properties(dev, nau8824);
1863 if (ret)
1864 return ret;
1865 }
1866 i2c_set_clientdata(i2c, nau8824);
1867
1868 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config);
1869 if (IS_ERR(nau8824->regmap))
1870 return PTR_ERR(nau8824->regmap);
1871 nau8824->dev = dev;
1872 nau8824->irq = i2c->irq;
1873 sema_init(&nau8824->jd_sem, 1);
1874
1875 nau8824_print_device_properties(nau8824);
1876
1877 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value);
1878 if (ret < 0) {
1879 dev_err(dev, "Failed to read device id from the NAU8824: %d\n",
1880 ret);
1881 return ret;
1882 }
1883 nau8824_reset_chip(nau8824->regmap);
1884 nau8824_init_regs(nau8824);
1885
1886 if (i2c->irq)
1887 nau8824_setup_irq(nau8824);
1888
1889 return devm_snd_soc_register_component(dev,
1890 &nau8824_component_driver, &nau8824_dai, 1);
1891 }
1892
1893 static const struct i2c_device_id nau8824_i2c_ids[] = {
1894 { "nau8824", 0 },
1895 { }
1896 };
1897 MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids);
1898
1899 #ifdef CONFIG_OF
1900 static const struct of_device_id nau8824_of_ids[] = {
1901 { .compatible = "nuvoton,nau8824", },
1902 {}
1903 };
1904 MODULE_DEVICE_TABLE(of, nau8824_of_ids);
1905 #endif
1906
1907 #ifdef CONFIG_ACPI
1908 static const struct acpi_device_id nau8824_acpi_match[] = {
1909 { "10508824", 0 },
1910 {},
1911 };
1912 MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match);
1913 #endif
1914
1915 static struct i2c_driver nau8824_i2c_driver = {
1916 .driver = {
1917 .name = "nau8824",
1918 .of_match_table = of_match_ptr(nau8824_of_ids),
1919 .acpi_match_table = ACPI_PTR(nau8824_acpi_match),
1920 },
1921 .probe = nau8824_i2c_probe,
1922 .id_table = nau8824_i2c_ids,
1923 };
1924 module_i2c_driver(nau8824_i2c_driver);
1925
1926
1927 MODULE_DESCRIPTION("ASoC NAU88L24 driver");
1928 MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
1929 MODULE_LICENSE("GPL v2");
1930
