1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
42
43 #include <linux/refcount.h>
44
45 #include <linux/timecounter.h>
46
47 #define DEFAULT_UAR_PAGE_SHIFT 12
48
49 #define MAX_MSIX_P_PORT 17
50 #define MAX_MSIX 64
51 #define MIN_MSIX_P_PORT 5
52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
53 (dev_cap).num_ports * MIN_MSIX_P_PORT)
54
55 #define MLX4_MAX_100M_UNITS_VAL 255 /*
56 * work around: can't set values
57 * greater then this value when
58 * using 100 Mbps units.
59 */
60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
62 #define MLX4_RATELIMIT_DEFAULT 0x00ff
63
64 #define MLX4_ROCE_MAX_GIDS 128
65 #define MLX4_ROCE_PF_GIDS 16
66
67 enum {
68 MLX4_FLAG_MSI_X = 1 << 0,
69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
70 MLX4_FLAG_MASTER = 1 << 2,
71 MLX4_FLAG_SLAVE = 1 << 3,
72 MLX4_FLAG_SRIOV = 1 << 4,
73 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
74 MLX4_FLAG_BONDED = 1 << 7,
75 MLX4_FLAG_SECURE_HOST = 1 << 8,
76 };
77
78 enum {
79 MLX4_PORT_CAP_IS_SM = 1 << 1,
80 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
81 };
82
83 enum {
84 MLX4_MAX_PORTS = 2,
85 MLX4_MAX_PORT_PKEYS = 128,
86 MLX4_MAX_PORT_GIDS = 128
87 };
88
89 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
90 * These qkeys must not be allowed for general use. This is a 64k range,
91 * and to test for violation, we use the mask (protect against future chg).
92 */
93 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
94 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
95
96 enum {
97 MLX4_BOARD_ID_LEN = 64
98 };
99
100 enum {
101 MLX4_MAX_NUM_PF = 16,
102 MLX4_MAX_NUM_VF = 126,
103 MLX4_MAX_NUM_VF_P_PORT = 64,
104 MLX4_MFUNC_MAX = 128,
105 MLX4_MAX_EQ_NUM = 1024,
106 MLX4_MFUNC_EQ_NUM = 4,
107 MLX4_MFUNC_MAX_EQES = 8,
108 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
109 };
110
111 /* Driver supports 3 different device methods to manage traffic steering:
112 * -device managed - High level API for ib and eth flow steering. FW is
113 * managing flow steering tables.
114 * - B0 steering mode - Common low level API for ib and (if supported) eth.
115 * - A0 steering mode - Limited low level API for eth. In case of IB,
116 * B0 mode is in use.
117 */
118 enum {
119 MLX4_STEERING_MODE_A0,
120 MLX4_STEERING_MODE_B0,
121 MLX4_STEERING_MODE_DEVICE_MANAGED
122 };
123
124 enum {
125 MLX4_STEERING_DMFS_A0_DEFAULT,
126 MLX4_STEERING_DMFS_A0_DYNAMIC,
127 MLX4_STEERING_DMFS_A0_STATIC,
128 MLX4_STEERING_DMFS_A0_DISABLE,
129 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
130 };
131
mlx4_steering_mode_str(int steering_mode)132 static inline const char *mlx4_steering_mode_str(int steering_mode)
133 {
134 switch (steering_mode) {
135 case MLX4_STEERING_MODE_A0:
136 return "A0 steering";
137
138 case MLX4_STEERING_MODE_B0:
139 return "B0 steering";
140
141 case MLX4_STEERING_MODE_DEVICE_MANAGED:
142 return "Device managed flow steering";
143
144 default:
145 return "Unrecognize steering mode";
146 }
147 }
148
149 enum {
150 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
151 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
152 };
153
154 enum {
155 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
156 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
157 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
158 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
159 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
160 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
161 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
162 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
163 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
164 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
165 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
166 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
167 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
168 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
169 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
170 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
171 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
172 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
173 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
174 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
175 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
176 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
177 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
178 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
179 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
180 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
181 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
182 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
183 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
184 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
185 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
186 };
187
188 enum {
189 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
190 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
191 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
192 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
193 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
194 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
195 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
196 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
197 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
198 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
199 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
200 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
201 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
202 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
203 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
204 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
205 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
206 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
207 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
208 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
209 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
210 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
211 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
212 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
213 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
214 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
215 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
216 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
217 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
218 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
219 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
220 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
221 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
222 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
223 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34,
224 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35,
225 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36,
226 MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37,
227 MLX4_DEV_CAP_FLAG2_USER_MAC_EN = 1ULL << 38,
228 MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1ULL << 39,
229 };
230
231 enum {
232 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
233 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
234 };
235
236 enum {
237 MLX4_VF_CAP_FLAG_RESET = 1 << 0
238 };
239
240 /* bit enums for an 8-bit flags field indicating special use
241 * QPs which require special handling in qp_reserve_range.
242 * Currently, this only includes QPs used by the ETH interface,
243 * where we expect to use blueflame. These QPs must not have
244 * bits 6 and 7 set in their qp number.
245 *
246 * This enum may use only bits 0..7.
247 */
248 enum {
249 MLX4_RESERVE_A0_QP = 1 << 6,
250 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
251 };
252
253 enum {
254 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
255 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
256 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
257 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
258 };
259
260 enum {
261 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
262 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
263 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
264 };
265
266
267 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
268
269 enum {
270 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
271 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
272 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
273 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
274 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
275 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
276 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
277 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
278 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
279 };
280
281 enum {
282 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
283 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
284 };
285
286 enum mlx4_event {
287 MLX4_EVENT_TYPE_COMP = 0x00,
288 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
289 MLX4_EVENT_TYPE_COMM_EST = 0x02,
290 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
291 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
292 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
293 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
294 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
295 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
296 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
297 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
298 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
299 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
300 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
301 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
302 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
303 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
304 MLX4_EVENT_TYPE_CMD = 0x0a,
305 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
306 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
307 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
308 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
309 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
310 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
311 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
312 MLX4_EVENT_TYPE_NONE = 0xff,
313 };
314
315 enum {
316 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
317 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
318 };
319
320 enum {
321 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
322 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
323 };
324
325 enum {
326 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
327 };
328
329 enum slave_port_state {
330 SLAVE_PORT_DOWN = 0,
331 SLAVE_PENDING_UP,
332 SLAVE_PORT_UP,
333 };
334
335 enum slave_port_gen_event {
336 SLAVE_PORT_GEN_EVENT_DOWN = 0,
337 SLAVE_PORT_GEN_EVENT_UP,
338 SLAVE_PORT_GEN_EVENT_NONE,
339 };
340
341 enum slave_port_state_event {
342 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
343 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
344 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
345 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
346 };
347
348 enum {
349 MLX4_PERM_LOCAL_READ = 1 << 10,
350 MLX4_PERM_LOCAL_WRITE = 1 << 11,
351 MLX4_PERM_REMOTE_READ = 1 << 12,
352 MLX4_PERM_REMOTE_WRITE = 1 << 13,
353 MLX4_PERM_ATOMIC = 1 << 14,
354 MLX4_PERM_BIND_MW = 1 << 15,
355 MLX4_PERM_MASK = 0xFC00
356 };
357
358 enum {
359 MLX4_OPCODE_NOP = 0x00,
360 MLX4_OPCODE_SEND_INVAL = 0x01,
361 MLX4_OPCODE_RDMA_WRITE = 0x08,
362 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
363 MLX4_OPCODE_SEND = 0x0a,
364 MLX4_OPCODE_SEND_IMM = 0x0b,
365 MLX4_OPCODE_LSO = 0x0e,
366 MLX4_OPCODE_RDMA_READ = 0x10,
367 MLX4_OPCODE_ATOMIC_CS = 0x11,
368 MLX4_OPCODE_ATOMIC_FA = 0x12,
369 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
370 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
371 MLX4_OPCODE_BIND_MW = 0x18,
372 MLX4_OPCODE_FMR = 0x19,
373 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
374 MLX4_OPCODE_CONFIG_CMD = 0x1f,
375
376 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
377 MLX4_RECV_OPCODE_SEND = 0x01,
378 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
379 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
380
381 MLX4_CQE_OPCODE_ERROR = 0x1e,
382 MLX4_CQE_OPCODE_RESIZE = 0x16,
383 };
384
385 enum {
386 MLX4_STAT_RATE_OFFSET = 5
387 };
388
389 enum mlx4_protocol {
390 MLX4_PROT_IB_IPV6 = 0,
391 MLX4_PROT_ETH,
392 MLX4_PROT_IB_IPV4,
393 MLX4_PROT_FCOE
394 };
395
396 enum {
397 MLX4_MTT_FLAG_PRESENT = 1
398 };
399
400 enum mlx4_qp_region {
401 MLX4_QP_REGION_FW = 0,
402 MLX4_QP_REGION_RSS_RAW_ETH,
403 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
404 MLX4_QP_REGION_ETH_ADDR,
405 MLX4_QP_REGION_FC_ADDR,
406 MLX4_QP_REGION_FC_EXCH,
407 MLX4_NUM_QP_REGION
408 };
409
410 enum mlx4_port_type {
411 MLX4_PORT_TYPE_NONE = 0,
412 MLX4_PORT_TYPE_IB = 1,
413 MLX4_PORT_TYPE_ETH = 2,
414 MLX4_PORT_TYPE_AUTO = 3
415 };
416
417 enum mlx4_special_vlan_idx {
418 MLX4_NO_VLAN_IDX = 0,
419 MLX4_VLAN_MISS_IDX,
420 MLX4_VLAN_REGULAR
421 };
422
423 enum mlx4_steer_type {
424 MLX4_MC_STEER = 0,
425 MLX4_UC_STEER,
426 MLX4_NUM_STEERS
427 };
428
429 enum mlx4_resource_usage {
430 MLX4_RES_USAGE_NONE,
431 MLX4_RES_USAGE_DRIVER,
432 MLX4_RES_USAGE_USER_VERBS,
433 };
434
435 enum {
436 MLX4_NUM_FEXCH = 64 * 1024,
437 };
438
439 enum {
440 MLX4_MAX_FAST_REG_PAGES = 511,
441 };
442
443 enum {
444 /*
445 * Max wqe size for rdma read is 512 bytes, so this
446 * limits our max_sge_rd as the wqe needs to fit:
447 * - ctrl segment (16 bytes)
448 * - rdma segment (16 bytes)
449 * - scatter elements (16 bytes each)
450 */
451 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
452 };
453
454 enum {
455 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
456 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
457 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
458 MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17,
459 };
460
461 /* Port mgmt change event handling */
462 enum {
463 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
464 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
465 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
466 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
467 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
468 };
469
470 union sl2vl_tbl_to_u64 {
471 u8 sl8[8];
472 u64 sl64;
473 };
474
475 enum {
476 MLX4_DEVICE_STATE_UP = 1 << 0,
477 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
478 };
479
480 enum {
481 MLX4_INTERFACE_STATE_UP = 1 << 0,
482 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
483 MLX4_INTERFACE_STATE_NOWAIT = 1 << 2,
484 };
485
486 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
487 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
488
489 enum mlx4_module_id {
490 MLX4_MODULE_ID_SFP = 0x3,
491 MLX4_MODULE_ID_QSFP = 0xC,
492 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
493 MLX4_MODULE_ID_QSFP28 = 0x11,
494 };
495
496 enum { /* rl */
497 MLX4_QP_RATE_LIMIT_NONE = 0,
498 MLX4_QP_RATE_LIMIT_KBS = 1,
499 MLX4_QP_RATE_LIMIT_MBS = 2,
500 MLX4_QP_RATE_LIMIT_GBS = 3
501 };
502
503 struct mlx4_rate_limit_caps {
504 u16 num_rates; /* Number of different rates */
505 u8 min_unit;
506 u16 min_val;
507 u8 max_unit;
508 u16 max_val;
509 };
510
mlx4_fw_ver(u64 major,u64 minor,u64 subminor)511 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
512 {
513 return (major << 32) | (minor << 16) | subminor;
514 }
515
516 struct mlx4_phys_caps {
517 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
518 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
519 u32 num_phys_eqs;
520 u32 base_sqpn;
521 u32 base_proxy_sqpn;
522 u32 base_tunnel_sqpn;
523 };
524
525 struct mlx4_spec_qps {
526 u32 qp0_qkey;
527 u32 qp0_proxy;
528 u32 qp0_tunnel;
529 u32 qp1_proxy;
530 u32 qp1_tunnel;
531 };
532
533 struct mlx4_caps {
534 u64 fw_ver;
535 u32 function;
536 int num_ports;
537 int vl_cap[MLX4_MAX_PORTS + 1];
538 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
539 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
540 u64 def_mac[MLX4_MAX_PORTS + 1];
541 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
542 int gid_table_len[MLX4_MAX_PORTS + 1];
543 int pkey_table_len[MLX4_MAX_PORTS + 1];
544 int trans_type[MLX4_MAX_PORTS + 1];
545 int vendor_oui[MLX4_MAX_PORTS + 1];
546 int wavelength[MLX4_MAX_PORTS + 1];
547 u64 trans_code[MLX4_MAX_PORTS + 1];
548 int local_ca_ack_delay;
549 int num_uars;
550 u32 uar_page_size;
551 int bf_reg_size;
552 int bf_regs_per_page;
553 int max_sq_sg;
554 int max_rq_sg;
555 int num_qps;
556 int max_wqes;
557 int max_sq_desc_sz;
558 int max_rq_desc_sz;
559 int max_qp_init_rdma;
560 int max_qp_dest_rdma;
561 int max_tc_eth;
562 struct mlx4_spec_qps *spec_qps;
563 int num_srqs;
564 int max_srq_wqes;
565 int max_srq_sge;
566 int reserved_srqs;
567 int num_cqs;
568 int max_cqes;
569 int reserved_cqs;
570 int num_sys_eqs;
571 int num_eqs;
572 int reserved_eqs;
573 int num_comp_vectors;
574 int num_mpts;
575 int max_fmr_maps;
576 int num_mtts;
577 int fmr_reserved_mtts;
578 int reserved_mtts;
579 int reserved_mrws;
580 int reserved_uars;
581 int num_mgms;
582 int num_amgms;
583 int reserved_mcgs;
584 int num_qp_per_mgm;
585 int steering_mode;
586 int dmfs_high_steer_mode;
587 int fs_log_max_ucast_qp_range_size;
588 int num_pds;
589 int reserved_pds;
590 int max_xrcds;
591 int reserved_xrcds;
592 int mtt_entry_sz;
593 u32 max_msg_sz;
594 u32 page_size_cap;
595 u64 flags;
596 u64 flags2;
597 u32 bmme_flags;
598 u32 reserved_lkey;
599 u16 stat_rate_support;
600 u8 port_width_cap[MLX4_MAX_PORTS + 1];
601 int max_gso_sz;
602 int max_rss_tbl_sz;
603 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
604 int reserved_qps;
605 int reserved_qps_base[MLX4_NUM_QP_REGION];
606 int log_num_macs;
607 int log_num_vlans;
608 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
609 u8 supported_type[MLX4_MAX_PORTS + 1];
610 u8 suggested_type[MLX4_MAX_PORTS + 1];
611 u8 default_sense[MLX4_MAX_PORTS + 1];
612 u32 port_mask[MLX4_MAX_PORTS + 1];
613 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
614 u32 max_counters;
615 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
616 u16 sqp_demux;
617 u32 eqe_size;
618 u32 cqe_size;
619 u8 eqe_factor;
620 u32 userspace_caps; /* userspace must be aware of these */
621 u32 function_caps; /* VFs must be aware of these */
622 u16 hca_core_clock;
623 u64 phys_port_id[MLX4_MAX_PORTS + 1];
624 int tunnel_offload_mode;
625 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
626 u8 phv_bit[MLX4_MAX_PORTS + 1];
627 u8 alloc_res_qp_mask;
628 u32 dmfs_high_rate_qpn_base;
629 u32 dmfs_high_rate_qpn_range;
630 u32 vf_caps;
631 bool wol_port[MLX4_MAX_PORTS + 1];
632 struct mlx4_rate_limit_caps rl_caps;
633 u32 health_buffer_addrs;
634 };
635
636 struct mlx4_buf_list {
637 void *buf;
638 dma_addr_t map;
639 };
640
641 struct mlx4_buf {
642 struct mlx4_buf_list direct;
643 struct mlx4_buf_list *page_list;
644 int nbufs;
645 int npages;
646 int page_shift;
647 };
648
649 struct mlx4_mtt {
650 u32 offset;
651 int order;
652 int page_shift;
653 };
654
655 enum {
656 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
657 };
658
659 struct mlx4_db_pgdir {
660 struct list_head list;
661 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
662 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
663 unsigned long *bits[2];
664 __be32 *db_page;
665 dma_addr_t db_dma;
666 };
667
668 struct mlx4_ib_user_db_page;
669
670 struct mlx4_db {
671 __be32 *db;
672 union {
673 struct mlx4_db_pgdir *pgdir;
674 struct mlx4_ib_user_db_page *user_page;
675 } u;
676 dma_addr_t dma;
677 int index;
678 int order;
679 };
680
681 struct mlx4_hwq_resources {
682 struct mlx4_db db;
683 struct mlx4_mtt mtt;
684 struct mlx4_buf buf;
685 };
686
687 struct mlx4_mr {
688 struct mlx4_mtt mtt;
689 u64 iova;
690 u64 size;
691 u32 key;
692 u32 pd;
693 u32 access;
694 int enabled;
695 };
696
697 enum mlx4_mw_type {
698 MLX4_MW_TYPE_1 = 1,
699 MLX4_MW_TYPE_2 = 2,
700 };
701
702 struct mlx4_mw {
703 u32 key;
704 u32 pd;
705 enum mlx4_mw_type type;
706 int enabled;
707 };
708
709 struct mlx4_fmr {
710 struct mlx4_mr mr;
711 struct mlx4_mpt_entry *mpt;
712 __be64 *mtts;
713 dma_addr_t dma_handle;
714 int max_pages;
715 int max_maps;
716 int maps;
717 u8 page_shift;
718 };
719
720 struct mlx4_uar {
721 unsigned long pfn;
722 int index;
723 struct list_head bf_list;
724 unsigned free_bf_bmap;
725 void __iomem *map;
726 void __iomem *bf_map;
727 };
728
729 struct mlx4_bf {
730 unsigned int offset;
731 int buf_size;
732 struct mlx4_uar *uar;
733 void __iomem *reg;
734 };
735
736 struct mlx4_cq {
737 void (*comp) (struct mlx4_cq *);
738 void (*event) (struct mlx4_cq *, enum mlx4_event);
739
740 struct mlx4_uar *uar;
741
742 u32 cons_index;
743
744 u16 irq;
745 __be32 *set_ci_db;
746 __be32 *arm_db;
747 int arm_sn;
748
749 int cqn;
750 unsigned vector;
751
752 refcount_t refcount;
753 struct completion free;
754 struct {
755 struct list_head list;
756 void (*comp)(struct mlx4_cq *);
757 void *priv;
758 } tasklet_ctx;
759 int reset_notify_added;
760 struct list_head reset_notify;
761 u8 usage;
762 };
763
764 struct mlx4_qp {
765 void (*event) (struct mlx4_qp *, enum mlx4_event);
766
767 int qpn;
768
769 refcount_t refcount;
770 struct completion free;
771 u8 usage;
772 };
773
774 struct mlx4_srq {
775 void (*event) (struct mlx4_srq *, enum mlx4_event);
776
777 int srqn;
778 int max;
779 int max_gs;
780 int wqe_shift;
781
782 refcount_t refcount;
783 struct completion free;
784 };
785
786 struct mlx4_av {
787 __be32 port_pd;
788 u8 reserved1;
789 u8 g_slid;
790 __be16 dlid;
791 u8 reserved2;
792 u8 gid_index;
793 u8 stat_rate;
794 u8 hop_limit;
795 __be32 sl_tclass_flowlabel;
796 u8 dgid[16];
797 };
798
799 struct mlx4_eth_av {
800 __be32 port_pd;
801 u8 reserved1;
802 u8 smac_idx;
803 u16 reserved2;
804 u8 reserved3;
805 u8 gid_index;
806 u8 stat_rate;
807 u8 hop_limit;
808 __be32 sl_tclass_flowlabel;
809 u8 dgid[16];
810 u8 s_mac[6];
811 u8 reserved4[2];
812 __be16 vlan;
813 u8 mac[ETH_ALEN];
814 };
815
816 union mlx4_ext_av {
817 struct mlx4_av ib;
818 struct mlx4_eth_av eth;
819 };
820
821 /* Counters should be saturate once they reach their maximum value */
822 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
823 if ((value) > U32_MAX) \
824 counter = cpu_to_be32(U32_MAX); \
825 else \
826 counter = cpu_to_be32(value); \
827 } while (0)
828
829 struct mlx4_counter {
830 u8 reserved1[3];
831 u8 counter_mode;
832 __be32 num_ifc;
833 u32 reserved2[2];
834 __be64 rx_frames;
835 __be64 rx_bytes;
836 __be64 tx_frames;
837 __be64 tx_bytes;
838 };
839
840 struct mlx4_quotas {
841 int qp;
842 int cq;
843 int srq;
844 int mpt;
845 int mtt;
846 int counter;
847 int xrcd;
848 };
849
850 struct mlx4_vf_dev {
851 u8 min_port;
852 u8 n_ports;
853 };
854
855 struct mlx4_fw_crdump {
856 bool snapshot_enable;
857 struct devlink_region *region_crspace;
858 struct devlink_region *region_fw_health;
859 };
860
861 enum mlx4_pci_status {
862 MLX4_PCI_STATUS_DISABLED,
863 MLX4_PCI_STATUS_ENABLED,
864 };
865
866 struct mlx4_dev_persistent {
867 struct pci_dev *pdev;
868 struct mlx4_dev *dev;
869 int nvfs[MLX4_MAX_PORTS + 1];
870 int num_vfs;
871 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
872 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
873 struct work_struct catas_work;
874 struct workqueue_struct *catas_wq;
875 struct mutex device_state_mutex; /* protect HW state */
876 u8 state;
877 struct mutex interface_state_mutex; /* protect SW state */
878 u8 interface_state;
879 struct mutex pci_status_mutex; /* sync pci state */
880 enum mlx4_pci_status pci_status;
881 struct mlx4_fw_crdump crdump;
882 };
883
884 struct mlx4_dev {
885 struct mlx4_dev_persistent *persist;
886 unsigned long flags;
887 unsigned long num_slaves;
888 struct mlx4_caps caps;
889 struct mlx4_phys_caps phys_caps;
890 struct mlx4_quotas quotas;
891 struct radix_tree_root qp_table_tree;
892 u8 rev_id;
893 u8 port_random_macs;
894 char board_id[MLX4_BOARD_ID_LEN];
895 int numa_node;
896 int oper_log_mgm_entry_size;
897 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
898 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
899 struct mlx4_vf_dev *dev_vfs;
900 u8 uar_page_shift;
901 };
902
903 struct mlx4_clock_params {
904 u64 offset;
905 u8 bar;
906 u8 size;
907 };
908
909 struct mlx4_eqe {
910 u8 reserved1;
911 u8 type;
912 u8 reserved2;
913 u8 subtype;
914 union {
915 u32 raw[6];
916 struct {
917 __be32 cqn;
918 } __packed comp;
919 struct {
920 u16 reserved1;
921 __be16 token;
922 u32 reserved2;
923 u8 reserved3[3];
924 u8 status;
925 __be64 out_param;
926 } __packed cmd;
927 struct {
928 __be32 qpn;
929 } __packed qp;
930 struct {
931 __be32 srqn;
932 } __packed srq;
933 struct {
934 __be32 cqn;
935 u32 reserved1;
936 u8 reserved2[3];
937 u8 syndrome;
938 } __packed cq_err;
939 struct {
940 u32 reserved1[2];
941 __be32 port;
942 } __packed port_change;
943 struct {
944 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
945 u32 reserved;
946 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
947 } __packed comm_channel_arm;
948 struct {
949 u8 port;
950 u8 reserved[3];
951 __be64 mac;
952 } __packed mac_update;
953 struct {
954 __be32 slave_id;
955 } __packed flr_event;
956 struct {
957 __be16 current_temperature;
958 __be16 warning_threshold;
959 } __packed warming;
960 struct {
961 u8 reserved[3];
962 u8 port;
963 union {
964 struct {
965 __be16 mstr_sm_lid;
966 __be16 port_lid;
967 __be32 changed_attr;
968 u8 reserved[3];
969 u8 mstr_sm_sl;
970 __be64 gid_prefix;
971 } __packed port_info;
972 struct {
973 __be32 block_ptr;
974 __be32 tbl_entries_mask;
975 } __packed tbl_change_info;
976 struct {
977 u8 sl2vl_table[8];
978 } __packed sl2vl_tbl_change_info;
979 } params;
980 } __packed port_mgmt_change;
981 struct {
982 u8 reserved[3];
983 u8 port;
984 u32 reserved1[5];
985 } __packed bad_cable;
986 } event;
987 u8 slave_id;
988 u8 reserved3[2];
989 u8 owner;
990 } __packed;
991
992 struct mlx4_init_port_param {
993 int set_guid0;
994 int set_node_guid;
995 int set_si_guid;
996 u16 mtu;
997 int port_width_cap;
998 u16 vl_cap;
999 u16 max_gid;
1000 u16 max_pkey;
1001 u64 guid0;
1002 u64 node_guid;
1003 u64 si_guid;
1004 };
1005
1006 #define MAD_IFC_DATA_SZ 192
1007 /* MAD IFC Mailbox */
1008 struct mlx4_mad_ifc {
1009 u8 base_version;
1010 u8 mgmt_class;
1011 u8 class_version;
1012 u8 method;
1013 __be16 status;
1014 __be16 class_specific;
1015 __be64 tid;
1016 __be16 attr_id;
1017 __be16 resv;
1018 __be32 attr_mod;
1019 __be64 mkey;
1020 __be16 dr_slid;
1021 __be16 dr_dlid;
1022 u8 reserved[28];
1023 u8 data[MAD_IFC_DATA_SZ];
1024 } __packed;
1025
1026 #define mlx4_foreach_port(port, dev, type) \
1027 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1028 if ((type) == (dev)->caps.port_mask[(port)])
1029
1030 #define mlx4_foreach_ib_transport_port(port, dev) \
1031 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1032 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
1033 ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH))
1034
1035 #define MLX4_INVALID_SLAVE_ID 0xFF
1036 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
1037
1038 void handle_port_mgmt_change_event(struct work_struct *work);
1039
mlx4_master_func_num(struct mlx4_dev * dev)1040 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
1041 {
1042 return dev->caps.function;
1043 }
1044
mlx4_is_master(struct mlx4_dev * dev)1045 static inline int mlx4_is_master(struct mlx4_dev *dev)
1046 {
1047 return dev->flags & MLX4_FLAG_MASTER;
1048 }
1049
mlx4_num_reserved_sqps(struct mlx4_dev * dev)1050 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1051 {
1052 return dev->phys_caps.base_sqpn + 8 +
1053 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1054 }
1055
mlx4_is_qp_reserved(struct mlx4_dev * dev,u32 qpn)1056 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1057 {
1058 return (qpn < dev->phys_caps.base_sqpn + 8 +
1059 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1060 qpn >= dev->phys_caps.base_sqpn) ||
1061 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1062 }
1063
mlx4_is_guest_proxy(struct mlx4_dev * dev,int slave,u32 qpn)1064 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1065 {
1066 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1067
1068 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1069 return 1;
1070
1071 return 0;
1072 }
1073
mlx4_is_mfunc(struct mlx4_dev * dev)1074 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1075 {
1076 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1077 }
1078
mlx4_is_slave(struct mlx4_dev * dev)1079 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1080 {
1081 return dev->flags & MLX4_FLAG_SLAVE;
1082 }
1083
mlx4_is_eth(struct mlx4_dev * dev,int port)1084 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1085 {
1086 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1087 }
1088
1089 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1090 struct mlx4_buf *buf);
1091 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
mlx4_buf_offset(struct mlx4_buf * buf,int offset)1092 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1093 {
1094 if (buf->nbufs == 1)
1095 return buf->direct.buf + offset;
1096 else
1097 return buf->page_list[offset >> PAGE_SHIFT].buf +
1098 (offset & (PAGE_SIZE - 1));
1099 }
1100
1101 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1102 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1103 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1104 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1105
1106 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1107 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1108 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1109 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1110
1111 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1112 struct mlx4_mtt *mtt);
1113 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1114 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1115
1116 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1117 int npages, int page_shift, struct mlx4_mr *mr);
1118 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1119 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1120 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1121 struct mlx4_mw *mw);
1122 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1123 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1124 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1125 int start_index, int npages, u64 *page_list);
1126 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1127 struct mlx4_buf *buf);
1128
1129 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
1130 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1131
1132 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1133 int size);
1134 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1135 int size);
1136
1137 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1138 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1139 unsigned vector, int collapsed, int timestamp_en);
1140 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1141 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1142 int *base, u8 flags, u8 usage);
1143 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1144
1145 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
1146 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1147
1148 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1149 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1150 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1151 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1152 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1153
1154 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1155 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1156
1157 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1158 int block_mcast_loopback, enum mlx4_protocol prot);
1159 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1160 enum mlx4_protocol prot);
1161 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1162 u8 port, int block_mcast_loopback,
1163 enum mlx4_protocol protocol, u64 *reg_id);
1164 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1165 enum mlx4_protocol protocol, u64 reg_id);
1166
1167 enum {
1168 MLX4_DOMAIN_UVERBS = 0x1000,
1169 MLX4_DOMAIN_ETHTOOL = 0x2000,
1170 MLX4_DOMAIN_RFS = 0x3000,
1171 MLX4_DOMAIN_NIC = 0x5000,
1172 };
1173
1174 enum mlx4_net_trans_rule_id {
1175 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1176 MLX4_NET_TRANS_RULE_ID_IB,
1177 MLX4_NET_TRANS_RULE_ID_IPV6,
1178 MLX4_NET_TRANS_RULE_ID_IPV4,
1179 MLX4_NET_TRANS_RULE_ID_TCP,
1180 MLX4_NET_TRANS_RULE_ID_UDP,
1181 MLX4_NET_TRANS_RULE_ID_VXLAN,
1182 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1183 };
1184
1185 extern const u16 __sw_id_hw[];
1186
map_hw_to_sw_id(u16 header_id)1187 static inline int map_hw_to_sw_id(u16 header_id)
1188 {
1189
1190 int i;
1191 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1192 if (header_id == __sw_id_hw[i])
1193 return i;
1194 }
1195 return -EINVAL;
1196 }
1197
1198 enum mlx4_net_trans_promisc_mode {
1199 MLX4_FS_REGULAR = 1,
1200 MLX4_FS_ALL_DEFAULT,
1201 MLX4_FS_MC_DEFAULT,
1202 MLX4_FS_MIRROR_RX_PORT,
1203 MLX4_FS_MIRROR_SX_PORT,
1204 MLX4_FS_UC_SNIFFER,
1205 MLX4_FS_MC_SNIFFER,
1206 MLX4_FS_MODE_NUM, /* should be last */
1207 };
1208
1209 struct mlx4_spec_eth {
1210 u8 dst_mac[ETH_ALEN];
1211 u8 dst_mac_msk[ETH_ALEN];
1212 u8 src_mac[ETH_ALEN];
1213 u8 src_mac_msk[ETH_ALEN];
1214 u8 ether_type_enable;
1215 __be16 ether_type;
1216 __be16 vlan_id_msk;
1217 __be16 vlan_id;
1218 };
1219
1220 struct mlx4_spec_tcp_udp {
1221 __be16 dst_port;
1222 __be16 dst_port_msk;
1223 __be16 src_port;
1224 __be16 src_port_msk;
1225 };
1226
1227 struct mlx4_spec_ipv4 {
1228 __be32 dst_ip;
1229 __be32 dst_ip_msk;
1230 __be32 src_ip;
1231 __be32 src_ip_msk;
1232 };
1233
1234 struct mlx4_spec_ib {
1235 __be32 l3_qpn;
1236 __be32 qpn_msk;
1237 u8 dst_gid[16];
1238 u8 dst_gid_msk[16];
1239 };
1240
1241 struct mlx4_spec_vxlan {
1242 __be32 vni;
1243 __be32 vni_mask;
1244
1245 };
1246
1247 struct mlx4_spec_list {
1248 struct list_head list;
1249 enum mlx4_net_trans_rule_id id;
1250 union {
1251 struct mlx4_spec_eth eth;
1252 struct mlx4_spec_ib ib;
1253 struct mlx4_spec_ipv4 ipv4;
1254 struct mlx4_spec_tcp_udp tcp_udp;
1255 struct mlx4_spec_vxlan vxlan;
1256 };
1257 };
1258
1259 enum mlx4_net_trans_hw_rule_queue {
1260 MLX4_NET_TRANS_Q_FIFO,
1261 MLX4_NET_TRANS_Q_LIFO,
1262 };
1263
1264 struct mlx4_net_trans_rule {
1265 struct list_head list;
1266 enum mlx4_net_trans_hw_rule_queue queue_mode;
1267 bool exclusive;
1268 bool allow_loopback;
1269 enum mlx4_net_trans_promisc_mode promisc_mode;
1270 u8 port;
1271 u16 priority;
1272 u32 qpn;
1273 };
1274
1275 struct mlx4_net_trans_rule_hw_ctrl {
1276 __be16 prio;
1277 u8 type;
1278 u8 flags;
1279 u8 rsvd1;
1280 u8 funcid;
1281 u8 vep;
1282 u8 port;
1283 __be32 qpn;
1284 __be32 rsvd2;
1285 };
1286
1287 struct mlx4_net_trans_rule_hw_ib {
1288 u8 size;
1289 u8 rsvd1;
1290 __be16 id;
1291 u32 rsvd2;
1292 __be32 l3_qpn;
1293 __be32 qpn_mask;
1294 u8 dst_gid[16];
1295 u8 dst_gid_msk[16];
1296 } __packed;
1297
1298 struct mlx4_net_trans_rule_hw_eth {
1299 u8 size;
1300 u8 rsvd;
1301 __be16 id;
1302 u8 rsvd1[6];
1303 u8 dst_mac[6];
1304 u16 rsvd2;
1305 u8 dst_mac_msk[6];
1306 u16 rsvd3;
1307 u8 src_mac[6];
1308 u16 rsvd4;
1309 u8 src_mac_msk[6];
1310 u8 rsvd5;
1311 u8 ether_type_enable;
1312 __be16 ether_type;
1313 __be16 vlan_tag_msk;
1314 __be16 vlan_tag;
1315 } __packed;
1316
1317 struct mlx4_net_trans_rule_hw_tcp_udp {
1318 u8 size;
1319 u8 rsvd;
1320 __be16 id;
1321 __be16 rsvd1[3];
1322 __be16 dst_port;
1323 __be16 rsvd2;
1324 __be16 dst_port_msk;
1325 __be16 rsvd3;
1326 __be16 src_port;
1327 __be16 rsvd4;
1328 __be16 src_port_msk;
1329 } __packed;
1330
1331 struct mlx4_net_trans_rule_hw_ipv4 {
1332 u8 size;
1333 u8 rsvd;
1334 __be16 id;
1335 __be32 rsvd1;
1336 __be32 dst_ip;
1337 __be32 dst_ip_msk;
1338 __be32 src_ip;
1339 __be32 src_ip_msk;
1340 } __packed;
1341
1342 struct mlx4_net_trans_rule_hw_vxlan {
1343 u8 size;
1344 u8 rsvd;
1345 __be16 id;
1346 __be32 rsvd1;
1347 __be32 vni;
1348 __be32 vni_mask;
1349 } __packed;
1350
1351 struct _rule_hw {
1352 union {
1353 struct {
1354 u8 size;
1355 u8 rsvd;
1356 __be16 id;
1357 };
1358 struct mlx4_net_trans_rule_hw_eth eth;
1359 struct mlx4_net_trans_rule_hw_ib ib;
1360 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1361 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1362 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1363 };
1364 };
1365
1366 enum {
1367 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1368 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1369 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1370 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1371 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1372 };
1373
1374 enum {
1375 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
1376 };
1377
1378 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1379 enum mlx4_net_trans_promisc_mode mode);
1380 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1381 enum mlx4_net_trans_promisc_mode mode);
1382 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1383 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1384 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1385 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1386 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1387
1388 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1389 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1390 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1391 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1392 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1393 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1394 int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac);
1395 int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu);
1396 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1397 u8 promisc);
1398 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1399 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1400 u8 ignore_fcs_value);
1401 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1402 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1403 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1404 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port,
1405 bool *vlan_offload_disabled);
1406 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
1407 struct _rule_hw *eth_header);
1408 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1409 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1410 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1411 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1412
1413 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1414 int npages, u64 iova, u32 *lkey, u32 *rkey);
1415 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1416 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1417 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1418 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1419 u32 *lkey, u32 *rkey);
1420 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1421 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1422 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector);
1423 int mlx4_test_async(struct mlx4_dev *dev);
1424 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
1425 const u32 offset[], u32 value[],
1426 size_t array_len, u8 port);
1427 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1428 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1429 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1430 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1431 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1432
1433 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1434 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1435
1436 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1437 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1438 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1439
1440 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage);
1441 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1442 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1443
1444 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1445 int port);
1446 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1447 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1448 int mlx4_flow_attach(struct mlx4_dev *dev,
1449 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1450 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1451 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1452 enum mlx4_net_trans_promisc_mode flow_type);
1453 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1454 enum mlx4_net_trans_rule_id id);
1455 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1456
1457 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1458 int port, int qpn, u16 prio, u64 *reg_id);
1459
1460 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1461 int i, int val);
1462
1463 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1464
1465 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1466 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1467 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1468 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1469 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1470 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1471 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1472
1473 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1474 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1475
1476 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1477 int *slave_id);
1478 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1479 u8 *gid);
1480
1481 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1482 u32 max_range_qpn);
1483
1484 u64 mlx4_read_clock(struct mlx4_dev *dev);
1485
1486 struct mlx4_active_ports {
1487 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1488 };
1489 /* Returns a bitmap of the physical ports which are assigned to slave */
1490 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1491
1492 /* Returns the physical port that represents the virtual port of the slave, */
1493 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1494 /* mapping is returned. */
1495 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1496
1497 struct mlx4_slaves_pport {
1498 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1499 };
1500 /* Returns a bitmap of all slaves that are assigned to port. */
1501 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1502 int port);
1503
1504 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1505 /* the ports that are set in crit_ports. */
1506 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1507 struct mlx4_dev *dev,
1508 const struct mlx4_active_ports *crit_ports);
1509
1510 /* Returns the slave's virtual port that represents the physical port. */
1511 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1512
1513 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1514
1515 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1516 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1517 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1518 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1519 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1520 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1521 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1522 int enable);
1523 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1524 struct mlx4_mpt_entry ***mpt_entry);
1525 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1526 struct mlx4_mpt_entry **mpt_entry);
1527 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1528 u32 pdn);
1529 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1530 struct mlx4_mpt_entry *mpt_entry,
1531 u32 access);
1532 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1533 struct mlx4_mpt_entry **mpt_entry);
1534 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1535 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1536 u64 iova, u64 size, int npages,
1537 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1538
1539 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1540 u16 offset, u16 size, u8 *data);
1541 int mlx4_max_tc(struct mlx4_dev *dev);
1542
1543 /* Returns true if running in low memory profile (kdump kernel) */
mlx4_low_memory_profile(void)1544 static inline bool mlx4_low_memory_profile(void)
1545 {
1546 return is_kdump_kernel();
1547 }
1548
1549 /* ACCESS REG commands */
1550 enum mlx4_access_reg_method {
1551 MLX4_ACCESS_REG_QUERY = 0x1,
1552 MLX4_ACCESS_REG_WRITE = 0x2,
1553 };
1554
1555 /* ACCESS PTYS Reg command */
1556 enum mlx4_ptys_proto {
1557 MLX4_PTYS_IB = 1<<0,
1558 MLX4_PTYS_EN = 1<<2,
1559 };
1560
1561 enum mlx4_ptys_flags {
1562 MLX4_PTYS_AN_DISABLE_CAP = 1 << 5,
1563 MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6,
1564 };
1565
1566 struct mlx4_ptys_reg {
1567 u8 flags;
1568 u8 local_port;
1569 u8 resrvd2;
1570 u8 proto_mask;
1571 __be32 resrvd3[2];
1572 __be32 eth_proto_cap;
1573 __be16 ib_width_cap;
1574 __be16 ib_speed_cap;
1575 __be32 resrvd4;
1576 __be32 eth_proto_admin;
1577 __be16 ib_width_admin;
1578 __be16 ib_speed_admin;
1579 __be32 resrvd5;
1580 __be32 eth_proto_oper;
1581 __be16 ib_width_oper;
1582 __be16 ib_speed_oper;
1583 __be32 resrvd6;
1584 __be32 eth_proto_lp_adv;
1585 } __packed;
1586
1587 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1588 enum mlx4_access_reg_method method,
1589 struct mlx4_ptys_reg *ptys_reg);
1590
1591 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1592 struct mlx4_clock_params *params);
1593
mlx4_to_hw_uar_index(struct mlx4_dev * dev,int index)1594 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
1595 {
1596 return (index << (PAGE_SHIFT - dev->uar_page_shift));
1597 }
1598
mlx4_get_num_reserved_uar(struct mlx4_dev * dev)1599 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
1600 {
1601 /* The first 128 UARs are used for EQ doorbells */
1602 return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
1603 }
1604 #endif /* MLX4_DEVICE_H */
1605
