1 /* linux/amba/pl093.h 2 * 3 * Copyright (c) 2008 Simtec Electronics 4 * http://armlinux.simtec.co.uk/ 5 * Ben Dooks <ben@simtec.co.uk> 6 * 7 * AMBA PL093 SSMC (synchronous static memory controller) 8 * See DDI0236.pdf (r0p4) for more details 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #define SMB_BANK(x) ((x) * 0x20) /* each bank control set is 0x20 apart */ 16 17 /* Offsets for SMBxxxxRy registers */ 18 19 #define SMBIDCYR (0x00) 20 #define SMBWSTRDR (0x04) 21 #define SMBWSTWRR (0x08) 22 #define SMBWSTOENR (0x0C) 23 #define SMBWSTWENR (0x10) 24 #define SMBCR (0x14) 25 #define SMBSR (0x18) 26 #define SMBWSTBRDR (0x1C) 27 28 /* Masks for SMB registers */ 29 #define IDCY_MASK (0xf) 30 #define WSTRD_MASK (0xf) 31 #define WSTWR_MASK (0xf) 32 #define WSTOEN_MASK (0xf) 33 #define WSTWEN_MASK (0xf) 34 35 /* Notes from datasheet: 36 * WSTOEN <= WSTRD 37 * WSTWEN <= WSTWR 38 * 39 * WSTOEN is not used with nWAIT 40 */ 41 42 /* SMBCR bit definitions */ 43 #define SMBCR_BIWRITEEN (1 << 21) 44 #define SMBCR_ADDRVALIDWRITEEN (1 << 20) 45 #define SMBCR_SYNCWRITE (1 << 17) 46 #define SMBCR_BMWRITE (1 << 16) 47 #define SMBCR_WRAPREAD (1 << 14) 48 #define SMBCR_BIREADEN (1 << 13) 49 #define SMBCR_ADDRVALIDREADEN (1 << 12) 50 #define SMBCR_SYNCREAD (1 << 9) 51 #define SMBCR_BMREAD (1 << 8) 52 #define SMBCR_SMBLSPOL (1 << 6) 53 #define SMBCR_WP (1 << 3) 54 #define SMBCR_WAITEN (1 << 2) 55 #define SMBCR_WAITPOL (1 << 1) 56 #define SMBCR_RBLE (1 << 0) 57 58 #define SMBCR_BURSTLENWRITE_MASK (3 << 18) 59 #define SMBCR_BURSTLENWRITE_4 (0 << 18) 60 #define SMBCR_BURSTLENWRITE_8 (1 << 18) 61 #define SMBCR_BURSTLENWRITE_RESERVED (2 << 18) 62 #define SMBCR_BURSTLENWRITE_CONTINUOUS (3 << 18) 63 64 #define SMBCR_BURSTLENREAD_MASK (3 << 10) 65 #define SMBCR_BURSTLENREAD_4 (0 << 10) 66 #define SMBCR_BURSTLENREAD_8 (1 << 10) 67 #define SMBCR_BURSTLENREAD_16 (2 << 10) 68 #define SMBCR_BURSTLENREAD_CONTINUOUS (3 << 10) 69 70 #define SMBCR_MW_MASK (3 << 4) 71 #define SMBCR_MW_8BIT (0 << 4) 72 #define SMBCR_MW_16BIT (1 << 4) 73 #define SMBCR_MW_M32BIT (2 << 4) 74 75 /* SSMC status registers */ 76 #define SSMCCSR (0x200) 77 #define SSMCCR (0x204) 78 #define SSMCITCR (0x208) 79 #define SSMCITIP (0x20C) 80 #define SSMCITIOP (0x210) 81
