1 /* 2 * tsi148.h 3 * 4 * Support for the Tundra TSI148 VME Bridge chip 5 * 6 * Author: Tom Armistead 7 * Updated and maintained by Ajit Prem 8 * Copyright 2004 Motorola Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #ifndef TSI148_H 17 #define TSI148_H 18 19 #ifndef PCI_VENDOR_ID_TUNDRA 20 #define PCI_VENDOR_ID_TUNDRA 0x10e3 21 #endif 22 23 #ifndef PCI_DEVICE_ID_TUNDRA_TSI148 24 #define PCI_DEVICE_ID_TUNDRA_TSI148 0x148 25 #endif 26 27 /* 28 * Define the number of each that the Tsi148 supports. 29 */ 30 #define TSI148_MAX_MASTER 8 /* Max Master Windows */ 31 #define TSI148_MAX_SLAVE 8 /* Max Slave Windows */ 32 #define TSI148_MAX_DMA 2 /* Max DMA Controllers */ 33 #define TSI148_MAX_MAILBOX 4 /* Max Mail Box registers */ 34 #define TSI148_MAX_SEMAPHORE 8 /* Max Semaphores */ 35 36 /* Structure used to hold driver specific information */ 37 struct tsi148_driver { 38 void __iomem *base; /* Base Address of device registers */ 39 wait_queue_head_t dma_queue[2]; 40 wait_queue_head_t iack_queue; 41 void (*lm_callback[4])(void *); /* Called in interrupt handler */ 42 void *lm_data[4]; 43 void *crcsr_kernel; 44 dma_addr_t crcsr_bus; 45 struct vme_master_resource *flush_image; 46 struct mutex vme_rmw; /* Only one RMW cycle at a time */ 47 struct mutex vme_int; /* 48 * Only one VME interrupt can be 49 * generated at a time, provide locking 50 */ 51 }; 52 53 /* 54 * Layout of a DMAC Linked-List Descriptor 55 * 56 * Note: This structure is accessed via the chip and therefore must be 57 * correctly laid out - It must also be aligned on 64-bit boundaries. 58 */ 59 struct tsi148_dma_descriptor { 60 __be32 dsau; /* Source Address */ 61 __be32 dsal; 62 __be32 ddau; /* Destination Address */ 63 __be32 ddal; 64 __be32 dsat; /* Source attributes */ 65 __be32 ddat; /* Destination attributes */ 66 __be32 dnlau; /* Next link address */ 67 __be32 dnlal; 68 __be32 dcnt; /* Byte count */ 69 __be32 ddbs; /* 2eSST Broadcast select */ 70 }; 71 72 struct tsi148_dma_entry { 73 /* 74 * The descriptor needs to be aligned on a 64-bit boundary, we increase 75 * the chance of this by putting it first in the structure. 76 */ 77 struct tsi148_dma_descriptor descriptor; 78 struct list_head list; 79 dma_addr_t dma_handle; 80 }; 81 82 /* 83 * TSI148 ASIC register structure overlays and bit field definitions. 84 * 85 * Note: Tsi148 Register Group (CRG) consists of the following 86 * combination of registers: 87 * PCFS - PCI Configuration Space Registers 88 * LCSR - Local Control and Status Registers 89 * GCSR - Global Control and Status Registers 90 * CR/CSR - Subset of Configuration ROM / 91 * Control and Status Registers 92 */ 93 94 95 /* 96 * Command/Status Registers (CRG + $004) 97 */ 98 #define TSI148_PCFS_ID 0x0 99 #define TSI148_PCFS_CSR 0x4 100 #define TSI148_PCFS_CLASS 0x8 101 #define TSI148_PCFS_MISC0 0xC 102 #define TSI148_PCFS_MBARL 0x10 103 #define TSI148_PCFS_MBARU 0x14 104 105 #define TSI148_PCFS_SUBID 0x28 106 107 #define TSI148_PCFS_CAPP 0x34 108 109 #define TSI148_PCFS_MISC1 0x3C 110 111 #define TSI148_PCFS_XCAPP 0x40 112 #define TSI148_PCFS_XSTAT 0x44 113 114 /* 115 * LCSR definitions 116 */ 117 118 /* 119 * Outbound Translations 120 */ 121 #define TSI148_LCSR_OT0_OTSAU 0x100 122 #define TSI148_LCSR_OT0_OTSAL 0x104 123 #define TSI148_LCSR_OT0_OTEAU 0x108 124 #define TSI148_LCSR_OT0_OTEAL 0x10C 125 #define TSI148_LCSR_OT0_OTOFU 0x110 126 #define TSI148_LCSR_OT0_OTOFL 0x114 127 #define TSI148_LCSR_OT0_OTBS 0x118 128 #define TSI148_LCSR_OT0_OTAT 0x11C 129 130 #define TSI148_LCSR_OT1_OTSAU 0x120 131 #define TSI148_LCSR_OT1_OTSAL 0x124 132 #define TSI148_LCSR_OT1_OTEAU 0x128 133 #define TSI148_LCSR_OT1_OTEAL 0x12C 134 #define TSI148_LCSR_OT1_OTOFU 0x130 135 #define TSI148_LCSR_OT1_OTOFL 0x134 136 #define TSI148_LCSR_OT1_OTBS 0x138 137 #define TSI148_LCSR_OT1_OTAT 0x13C 138 139 #define TSI148_LCSR_OT2_OTSAU 0x140 140 #define TSI148_LCSR_OT2_OTSAL 0x144 141 #define TSI148_LCSR_OT2_OTEAU 0x148 142 #define TSI148_LCSR_OT2_OTEAL 0x14C 143 #define TSI148_LCSR_OT2_OTOFU 0x150 144 #define TSI148_LCSR_OT2_OTOFL 0x154 145 #define TSI148_LCSR_OT2_OTBS 0x158 146 #define TSI148_LCSR_OT2_OTAT 0x15C 147 148 #define TSI148_LCSR_OT3_OTSAU 0x160 149 #define TSI148_LCSR_OT3_OTSAL 0x164 150 #define TSI148_LCSR_OT3_OTEAU 0x168 151 #define TSI148_LCSR_OT3_OTEAL 0x16C 152 #define TSI148_LCSR_OT3_OTOFU 0x170 153 #define TSI148_LCSR_OT3_OTOFL 0x174 154 #define TSI148_LCSR_OT3_OTBS 0x178 155 #define TSI148_LCSR_OT3_OTAT 0x17C 156 157 #define TSI148_LCSR_OT4_OTSAU 0x180 158 #define TSI148_LCSR_OT4_OTSAL 0x184 159 #define TSI148_LCSR_OT4_OTEAU 0x188 160 #define TSI148_LCSR_OT4_OTEAL 0x18C 161 #define TSI148_LCSR_OT4_OTOFU 0x190 162 #define TSI148_LCSR_OT4_OTOFL 0x194 163 #define TSI148_LCSR_OT4_OTBS 0x198 164 #define TSI148_LCSR_OT4_OTAT 0x19C 165 166 #define TSI148_LCSR_OT5_OTSAU 0x1A0 167 #define TSI148_LCSR_OT5_OTSAL 0x1A4 168 #define TSI148_LCSR_OT5_OTEAU 0x1A8 169 #define TSI148_LCSR_OT5_OTEAL 0x1AC 170 #define TSI148_LCSR_OT5_OTOFU 0x1B0 171 #define TSI148_LCSR_OT5_OTOFL 0x1B4 172 #define TSI148_LCSR_OT5_OTBS 0x1B8 173 #define TSI148_LCSR_OT5_OTAT 0x1BC 174 175 #define TSI148_LCSR_OT6_OTSAU 0x1C0 176 #define TSI148_LCSR_OT6_OTSAL 0x1C4 177 #define TSI148_LCSR_OT6_OTEAU 0x1C8 178 #define TSI148_LCSR_OT6_OTEAL 0x1CC 179 #define TSI148_LCSR_OT6_OTOFU 0x1D0 180 #define TSI148_LCSR_OT6_OTOFL 0x1D4 181 #define TSI148_LCSR_OT6_OTBS 0x1D8 182 #define TSI148_LCSR_OT6_OTAT 0x1DC 183 184 #define TSI148_LCSR_OT7_OTSAU 0x1E0 185 #define TSI148_LCSR_OT7_OTSAL 0x1E4 186 #define TSI148_LCSR_OT7_OTEAU 0x1E8 187 #define TSI148_LCSR_OT7_OTEAL 0x1EC 188 #define TSI148_LCSR_OT7_OTOFU 0x1F0 189 #define TSI148_LCSR_OT7_OTOFL 0x1F4 190 #define TSI148_LCSR_OT7_OTBS 0x1F8 191 #define TSI148_LCSR_OT7_OTAT 0x1FC 192 193 #define TSI148_LCSR_OT0 0x100 194 #define TSI148_LCSR_OT1 0x120 195 #define TSI148_LCSR_OT2 0x140 196 #define TSI148_LCSR_OT3 0x160 197 #define TSI148_LCSR_OT4 0x180 198 #define TSI148_LCSR_OT5 0x1A0 199 #define TSI148_LCSR_OT6 0x1C0 200 #define TSI148_LCSR_OT7 0x1E0 201 202 static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1, 203 TSI148_LCSR_OT2, TSI148_LCSR_OT3, 204 TSI148_LCSR_OT4, TSI148_LCSR_OT5, 205 TSI148_LCSR_OT6, TSI148_LCSR_OT7 }; 206 207 #define TSI148_LCSR_OFFSET_OTSAU 0x0 208 #define TSI148_LCSR_OFFSET_OTSAL 0x4 209 #define TSI148_LCSR_OFFSET_OTEAU 0x8 210 #define TSI148_LCSR_OFFSET_OTEAL 0xC 211 #define TSI148_LCSR_OFFSET_OTOFU 0x10 212 #define TSI148_LCSR_OFFSET_OTOFL 0x14 213 #define TSI148_LCSR_OFFSET_OTBS 0x18 214 #define TSI148_LCSR_OFFSET_OTAT 0x1C 215 216 /* 217 * VMEbus interrupt ack 218 * offset 200 219 */ 220 #define TSI148_LCSR_VIACK1 0x204 221 #define TSI148_LCSR_VIACK2 0x208 222 #define TSI148_LCSR_VIACK3 0x20C 223 #define TSI148_LCSR_VIACK4 0x210 224 #define TSI148_LCSR_VIACK5 0x214 225 #define TSI148_LCSR_VIACK6 0x218 226 #define TSI148_LCSR_VIACK7 0x21C 227 228 static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1, 229 TSI148_LCSR_VIACK2, TSI148_LCSR_VIACK3, 230 TSI148_LCSR_VIACK4, TSI148_LCSR_VIACK5, 231 TSI148_LCSR_VIACK6, TSI148_LCSR_VIACK7 }; 232 233 /* 234 * RMW 235 * offset 220 236 */ 237 #define TSI148_LCSR_RMWAU 0x220 238 #define TSI148_LCSR_RMWAL 0x224 239 #define TSI148_LCSR_RMWEN 0x228 240 #define TSI148_LCSR_RMWC 0x22C 241 #define TSI148_LCSR_RMWS 0x230 242 243 /* 244 * VMEbus control 245 * offset 234 246 */ 247 #define TSI148_LCSR_VMCTRL 0x234 248 #define TSI148_LCSR_VCTRL 0x238 249 #define TSI148_LCSR_VSTAT 0x23C 250 251 /* 252 * PCI status 253 * offset 240 254 */ 255 #define TSI148_LCSR_PSTAT 0x240 256 257 /* 258 * VME filter. 259 * offset 250 260 */ 261 #define TSI148_LCSR_VMEFL 0x250 262 263 /* 264 * VME exception. 265 * offset 260 266 */ 267 #define TSI148_LCSR_VEAU 0x260 268 #define TSI148_LCSR_VEAL 0x264 269 #define TSI148_LCSR_VEAT 0x268 270 271 /* 272 * PCI error 273 * offset 270 274 */ 275 #define TSI148_LCSR_EDPAU 0x270 276 #define TSI148_LCSR_EDPAL 0x274 277 #define TSI148_LCSR_EDPXA 0x278 278 #define TSI148_LCSR_EDPXS 0x27C 279 #define TSI148_LCSR_EDPAT 0x280 280 281 /* 282 * Inbound Translations 283 * offset 300 284 */ 285 #define TSI148_LCSR_IT0_ITSAU 0x300 286 #define TSI148_LCSR_IT0_ITSAL 0x304 287 #define TSI148_LCSR_IT0_ITEAU 0x308 288 #define TSI148_LCSR_IT0_ITEAL 0x30C 289 #define TSI148_LCSR_IT0_ITOFU 0x310 290 #define TSI148_LCSR_IT0_ITOFL 0x314 291 #define TSI148_LCSR_IT0_ITAT 0x318 292 293 #define TSI148_LCSR_IT1_ITSAU 0x320 294 #define TSI148_LCSR_IT1_ITSAL 0x324 295 #define TSI148_LCSR_IT1_ITEAU 0x328 296 #define TSI148_LCSR_IT1_ITEAL 0x32C 297 #define TSI148_LCSR_IT1_ITOFU 0x330 298 #define TSI148_LCSR_IT1_ITOFL 0x334 299 #define TSI148_LCSR_IT1_ITAT 0x338 300 301 #define TSI148_LCSR_IT2_ITSAU 0x340 302 #define TSI148_LCSR_IT2_ITSAL 0x344 303 #define TSI148_LCSR_IT2_ITEAU 0x348 304 #define TSI148_LCSR_IT2_ITEAL 0x34C 305 #define TSI148_LCSR_IT2_ITOFU 0x350 306 #define TSI148_LCSR_IT2_ITOFL 0x354 307 #define TSI148_LCSR_IT2_ITAT 0x358 308 309 #define TSI148_LCSR_IT3_ITSAU 0x360 310 #define TSI148_LCSR_IT3_ITSAL 0x364 311 #define TSI148_LCSR_IT3_ITEAU 0x368 312 #define TSI148_LCSR_IT3_ITEAL 0x36C 313 #define TSI148_LCSR_IT3_ITOFU 0x370 314 #define TSI148_LCSR_IT3_ITOFL 0x374 315 #define TSI148_LCSR_IT3_ITAT 0x378 316 317 #define TSI148_LCSR_IT4_ITSAU 0x380 318 #define TSI148_LCSR_IT4_ITSAL 0x384 319 #define TSI148_LCSR_IT4_ITEAU 0x388 320 #define TSI148_LCSR_IT4_ITEAL 0x38C 321 #define TSI148_LCSR_IT4_ITOFU 0x390 322 #define TSI148_LCSR_IT4_ITOFL 0x394 323 #define TSI148_LCSR_IT4_ITAT 0x398 324 325 #define TSI148_LCSR_IT5_ITSAU 0x3A0 326 #define TSI148_LCSR_IT5_ITSAL 0x3A4 327 #define TSI148_LCSR_IT5_ITEAU 0x3A8 328 #define TSI148_LCSR_IT5_ITEAL 0x3AC 329 #define TSI148_LCSR_IT5_ITOFU 0x3B0 330 #define TSI148_LCSR_IT5_ITOFL 0x3B4 331 #define TSI148_LCSR_IT5_ITAT 0x3B8 332 333 #define TSI148_LCSR_IT6_ITSAU 0x3C0 334 #define TSI148_LCSR_IT6_ITSAL 0x3C4 335 #define TSI148_LCSR_IT6_ITEAU 0x3C8 336 #define TSI148_LCSR_IT6_ITEAL 0x3CC 337 #define TSI148_LCSR_IT6_ITOFU 0x3D0 338 #define TSI148_LCSR_IT6_ITOFL 0x3D4 339 #define TSI148_LCSR_IT6_ITAT 0x3D8 340 341 #define TSI148_LCSR_IT7_ITSAU 0x3E0 342 #define TSI148_LCSR_IT7_ITSAL 0x3E4 343 #define TSI148_LCSR_IT7_ITEAU 0x3E8 344 #define TSI148_LCSR_IT7_ITEAL 0x3EC 345 #define TSI148_LCSR_IT7_ITOFU 0x3F0 346 #define TSI148_LCSR_IT7_ITOFL 0x3F4 347 #define TSI148_LCSR_IT7_ITAT 0x3F8 348 349 350 #define TSI148_LCSR_IT0 0x300 351 #define TSI148_LCSR_IT1 0x320 352 #define TSI148_LCSR_IT2 0x340 353 #define TSI148_LCSR_IT3 0x360 354 #define TSI148_LCSR_IT4 0x380 355 #define TSI148_LCSR_IT5 0x3A0 356 #define TSI148_LCSR_IT6 0x3C0 357 #define TSI148_LCSR_IT7 0x3E0 358 359 static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1, 360 TSI148_LCSR_IT2, TSI148_LCSR_IT3, 361 TSI148_LCSR_IT4, TSI148_LCSR_IT5, 362 TSI148_LCSR_IT6, TSI148_LCSR_IT7 }; 363 364 #define TSI148_LCSR_OFFSET_ITSAU 0x0 365 #define TSI148_LCSR_OFFSET_ITSAL 0x4 366 #define TSI148_LCSR_OFFSET_ITEAU 0x8 367 #define TSI148_LCSR_OFFSET_ITEAL 0xC 368 #define TSI148_LCSR_OFFSET_ITOFU 0x10 369 #define TSI148_LCSR_OFFSET_ITOFL 0x14 370 #define TSI148_LCSR_OFFSET_ITAT 0x18 371 372 /* 373 * Inbound Translation GCSR 374 * offset 400 375 */ 376 #define TSI148_LCSR_GBAU 0x400 377 #define TSI148_LCSR_GBAL 0x404 378 #define TSI148_LCSR_GCSRAT 0x408 379 380 /* 381 * Inbound Translation CRG 382 * offset 40C 383 */ 384 #define TSI148_LCSR_CBAU 0x40C 385 #define TSI148_LCSR_CBAL 0x410 386 #define TSI148_LCSR_CSRAT 0x414 387 388 /* 389 * Inbound Translation CR/CSR 390 * CRG 391 * offset 418 392 */ 393 #define TSI148_LCSR_CROU 0x418 394 #define TSI148_LCSR_CROL 0x41C 395 #define TSI148_LCSR_CRAT 0x420 396 397 /* 398 * Inbound Translation Location Monitor 399 * offset 424 400 */ 401 #define TSI148_LCSR_LMBAU 0x424 402 #define TSI148_LCSR_LMBAL 0x428 403 #define TSI148_LCSR_LMAT 0x42C 404 405 /* 406 * VMEbus Interrupt Control. 407 * offset 430 408 */ 409 #define TSI148_LCSR_BCU 0x430 410 #define TSI148_LCSR_BCL 0x434 411 #define TSI148_LCSR_BPGTR 0x438 412 #define TSI148_LCSR_BPCTR 0x43C 413 #define TSI148_LCSR_VICR 0x440 414 415 /* 416 * Local Bus Interrupt Control. 417 * offset 448 418 */ 419 #define TSI148_LCSR_INTEN 0x448 420 #define TSI148_LCSR_INTEO 0x44C 421 #define TSI148_LCSR_INTS 0x450 422 #define TSI148_LCSR_INTC 0x454 423 #define TSI148_LCSR_INTM1 0x458 424 #define TSI148_LCSR_INTM2 0x45C 425 426 /* 427 * DMA Controllers 428 * offset 500 429 */ 430 #define TSI148_LCSR_DCTL0 0x500 431 #define TSI148_LCSR_DSTA0 0x504 432 #define TSI148_LCSR_DCSAU0 0x508 433 #define TSI148_LCSR_DCSAL0 0x50C 434 #define TSI148_LCSR_DCDAU0 0x510 435 #define TSI148_LCSR_DCDAL0 0x514 436 #define TSI148_LCSR_DCLAU0 0x518 437 #define TSI148_LCSR_DCLAL0 0x51C 438 #define TSI148_LCSR_DSAU0 0x520 439 #define TSI148_LCSR_DSAL0 0x524 440 #define TSI148_LCSR_DDAU0 0x528 441 #define TSI148_LCSR_DDAL0 0x52C 442 #define TSI148_LCSR_DSAT0 0x530 443 #define TSI148_LCSR_DDAT0 0x534 444 #define TSI148_LCSR_DNLAU0 0x538 445 #define TSI148_LCSR_DNLAL0 0x53C 446 #define TSI148_LCSR_DCNT0 0x540 447 #define TSI148_LCSR_DDBS0 0x544 448 449 #define TSI148_LCSR_DCTL1 0x580 450 #define TSI148_LCSR_DSTA1 0x584 451 #define TSI148_LCSR_DCSAU1 0x588 452 #define TSI148_LCSR_DCSAL1 0x58C 453 #define TSI148_LCSR_DCDAU1 0x590 454 #define TSI148_LCSR_DCDAL1 0x594 455 #define TSI148_LCSR_DCLAU1 0x598 456 #define TSI148_LCSR_DCLAL1 0x59C 457 #define TSI148_LCSR_DSAU1 0x5A0 458 #define TSI148_LCSR_DSAL1 0x5A4 459 #define TSI148_LCSR_DDAU1 0x5A8 460 #define TSI148_LCSR_DDAL1 0x5AC 461 #define TSI148_LCSR_DSAT1 0x5B0 462 #define TSI148_LCSR_DDAT1 0x5B4 463 #define TSI148_LCSR_DNLAU1 0x5B8 464 #define TSI148_LCSR_DNLAL1 0x5BC 465 #define TSI148_LCSR_DCNT1 0x5C0 466 #define TSI148_LCSR_DDBS1 0x5C4 467 468 #define TSI148_LCSR_DMA0 0x500 469 #define TSI148_LCSR_DMA1 0x580 470 471 472 static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0, 473 TSI148_LCSR_DMA1 }; 474 475 #define TSI148_LCSR_OFFSET_DCTL 0x0 476 #define TSI148_LCSR_OFFSET_DSTA 0x4 477 #define TSI148_LCSR_OFFSET_DCSAU 0x8 478 #define TSI148_LCSR_OFFSET_DCSAL 0xC 479 #define TSI148_LCSR_OFFSET_DCDAU 0x10 480 #define TSI148_LCSR_OFFSET_DCDAL 0x14 481 #define TSI148_LCSR_OFFSET_DCLAU 0x18 482 #define TSI148_LCSR_OFFSET_DCLAL 0x1C 483 #define TSI148_LCSR_OFFSET_DSAU 0x20 484 #define TSI148_LCSR_OFFSET_DSAL 0x24 485 #define TSI148_LCSR_OFFSET_DDAU 0x28 486 #define TSI148_LCSR_OFFSET_DDAL 0x2C 487 #define TSI148_LCSR_OFFSET_DSAT 0x30 488 #define TSI148_LCSR_OFFSET_DDAT 0x34 489 #define TSI148_LCSR_OFFSET_DNLAU 0x38 490 #define TSI148_LCSR_OFFSET_DNLAL 0x3C 491 #define TSI148_LCSR_OFFSET_DCNT 0x40 492 #define TSI148_LCSR_OFFSET_DDBS 0x44 493 494 /* 495 * GCSR Register Group 496 */ 497 498 /* 499 * GCSR CRG 500 * offset 00 600 - DEVI/VENI 501 * offset 04 604 - CTRL/GA/REVID 502 * offset 08 608 - Semaphore3/2/1/0 503 * offset 0C 60C - Seamphore7/6/5/4 504 */ 505 #define TSI148_GCSR_ID 0x600 506 #define TSI148_GCSR_CSR 0x604 507 #define TSI148_GCSR_SEMA0 0x608 508 #define TSI148_GCSR_SEMA1 0x60C 509 510 /* 511 * Mail Box 512 * GCSR CRG 513 * offset 10 610 - Mailbox0 514 */ 515 #define TSI148_GCSR_MBOX0 0x610 516 #define TSI148_GCSR_MBOX1 0x614 517 #define TSI148_GCSR_MBOX2 0x618 518 #define TSI148_GCSR_MBOX3 0x61C 519 520 static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0, 521 TSI148_GCSR_MBOX1, 522 TSI148_GCSR_MBOX2, 523 TSI148_GCSR_MBOX3 }; 524 525 /* 526 * CR/CSR 527 */ 528 529 /* 530 * CR/CSR CRG 531 * offset 7FFF4 FF4 - CSRBCR 532 * offset 7FFF8 FF8 - CSRBSR 533 * offset 7FFFC FFC - CBAR 534 */ 535 #define TSI148_CSRBCR 0xFF4 536 #define TSI148_CSRBSR 0xFF8 537 #define TSI148_CBAR 0xFFC 538 539 540 541 542 /* 543 * TSI148 Register Bit Definitions 544 */ 545 546 /* 547 * PFCS Register Set 548 */ 549 #define TSI148_PCFS_CMMD_SERR (1<<8) /* SERR_L out pin ssys err */ 550 #define TSI148_PCFS_CMMD_PERR (1<<6) /* PERR_L out pin parity */ 551 #define TSI148_PCFS_CMMD_MSTR (1<<2) /* PCI bus master */ 552 #define TSI148_PCFS_CMMD_MEMSP (1<<1) /* PCI mem space access */ 553 #define TSI148_PCFS_CMMD_IOSP (1<<0) /* PCI I/O space enable */ 554 555 #define TSI148_PCFS_STAT_RCPVE (1<<15) /* Detected Parity Error */ 556 #define TSI148_PCFS_STAT_SIGSE (1<<14) /* Signalled System Error */ 557 #define TSI148_PCFS_STAT_RCVMA (1<<13) /* Received Master Abort */ 558 #define TSI148_PCFS_STAT_RCVTA (1<<12) /* Received Target Abort */ 559 #define TSI148_PCFS_STAT_SIGTA (1<<11) /* Signalled Target Abort */ 560 #define TSI148_PCFS_STAT_SELTIM (3<<9) /* DELSEL Timing */ 561 #define TSI148_PCFS_STAT_DPAR (1<<8) /* Data Parity Err Reported */ 562 #define TSI148_PCFS_STAT_FAST (1<<7) /* Fast back-to-back Cap */ 563 #define TSI148_PCFS_STAT_P66M (1<<5) /* 66 MHz Capable */ 564 #define TSI148_PCFS_STAT_CAPL (1<<4) /* Capab List - address $34 */ 565 566 /* 567 * Revision ID/Class Code Registers (CRG +$008) 568 */ 569 #define TSI148_PCFS_CLAS_M (0xFF<<24) /* Class ID */ 570 #define TSI148_PCFS_SUBCLAS_M (0xFF<<16) /* Sub-Class ID */ 571 #define TSI148_PCFS_PROGIF_M (0xFF<<8) /* Sub-Class ID */ 572 #define TSI148_PCFS_REVID_M (0xFF<<0) /* Rev ID */ 573 574 /* 575 * Cache Line Size/ Master Latency Timer/ Header Type Registers (CRG + $00C) 576 */ 577 #define TSI148_PCFS_HEAD_M (0xFF<<16) /* Master Lat Timer */ 578 #define TSI148_PCFS_MLAT_M (0xFF<<8) /* Master Lat Timer */ 579 #define TSI148_PCFS_CLSZ_M (0xFF<<0) /* Cache Line Size */ 580 581 /* 582 * Memory Base Address Lower Reg (CRG + $010) 583 */ 584 #define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF<<12) /* Base Addr Lower Mask */ 585 #define TSI148_PCFS_MBARL_PRE (1<<3) /* Prefetch */ 586 #define TSI148_PCFS_MBARL_MTYPE_M (3<<1) /* Memory Type Mask */ 587 #define TSI148_PCFS_MBARL_IOMEM (1<<0) /* I/O Space Indicator */ 588 589 /* 590 * Message Signaled Interrupt Capabilities Register (CRG + $040) 591 */ 592 #define TSI148_PCFS_MSICAP_64BAC (1<<7) /* 64-bit Address Capable */ 593 #define TSI148_PCFS_MSICAP_MME_M (7<<4) /* Multiple Msg Enable Mask */ 594 #define TSI148_PCFS_MSICAP_MMC_M (7<<1) /* Multiple Msg Capable Mask */ 595 #define TSI148_PCFS_MSICAP_MSIEN (1<<0) /* Msg signaled INT Enable */ 596 597 /* 598 * Message Address Lower Register (CRG +$044) 599 */ 600 #define TSI148_PCFS_MSIAL_M (0x3FFFFFFF<<2) /* Mask */ 601 602 /* 603 * Message Data Register (CRG + 4C) 604 */ 605 #define TSI148_PCFS_MSIMD_M (0xFFFF<<0) /* Mask */ 606 607 /* 608 * PCI-X Capabilities Register (CRG + $050) 609 */ 610 #define TSI148_PCFS_PCIXCAP_MOST_M (7<<4) /* Max outstanding Split Tran */ 611 #define TSI148_PCFS_PCIXCAP_MMRBC_M (3<<2) /* Max Mem Read byte cnt */ 612 #define TSI148_PCFS_PCIXCAP_ERO (1<<1) /* Enable Relaxed Ordering */ 613 #define TSI148_PCFS_PCIXCAP_DPERE (1<<0) /* Data Parity Recover Enable */ 614 615 /* 616 * PCI-X Status Register (CRG +$054) 617 */ 618 #define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29) /* Received Split Comp Error */ 619 #define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */ 620 #define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans 621 */ 622 #define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */ 623 #define TSI148_PCFS_PCIXSTAT_DC (1<<20) /* Device Complexity */ 624 #define TSI148_PCFS_PCIXSTAT_USC (1<<19) /* Unexpected Split comp */ 625 #define TSI148_PCFS_PCIXSTAT_SCD (1<<18) /* Split completion discard */ 626 #define TSI148_PCFS_PCIXSTAT_133C (1<<17) /* 133MHz capable */ 627 #define TSI148_PCFS_PCIXSTAT_64D (1<<16) /* 64 bit device */ 628 #define TSI148_PCFS_PCIXSTAT_BN_M (0xFF<<8) /* Bus number */ 629 #define TSI148_PCFS_PCIXSTAT_DN_M (0x1F<<3) /* Device number */ 630 #define TSI148_PCFS_PCIXSTAT_FN_M (7<<0) /* Function Number */ 631 632 /* 633 * LCSR Registers 634 */ 635 636 /* 637 * Outbound Translation Starting Address Lower 638 */ 639 #define TSI148_LCSR_OTSAL_M (0xFFFF<<16) /* Mask */ 640 641 /* 642 * Outbound Translation Ending Address Lower 643 */ 644 #define TSI148_LCSR_OTEAL_M (0xFFFF<<16) /* Mask */ 645 646 /* 647 * Outbound Translation Offset Lower 648 */ 649 #define TSI148_LCSR_OTOFFL_M (0xFFFF<<16) /* Mask */ 650 651 /* 652 * Outbound Translation 2eSST Broadcast Select 653 */ 654 #define TSI148_LCSR_OTBS_M (0xFFFFF<<0) /* Mask */ 655 656 /* 657 * Outbound Translation Attribute 658 */ 659 #define TSI148_LCSR_OTAT_EN (1<<31) /* Window Enable */ 660 #define TSI148_LCSR_OTAT_MRPFD (1<<18) /* Prefetch Disable */ 661 662 #define TSI148_LCSR_OTAT_PFS_M (3<<16) /* Prefetch Size Mask */ 663 #define TSI148_LCSR_OTAT_PFS_2 (0<<16) /* 2 Cache Lines P Size */ 664 #define TSI148_LCSR_OTAT_PFS_4 (1<<16) /* 4 Cache Lines P Size */ 665 #define TSI148_LCSR_OTAT_PFS_8 (2<<16) /* 8 Cache Lines P Size */ 666 #define TSI148_LCSR_OTAT_PFS_16 (3<<16) /* 16 Cache Lines P Size */ 667 668 #define TSI148_LCSR_OTAT_2eSSTM_M (7<<11) /* 2eSST Xfer Rate Mask */ 669 #define TSI148_LCSR_OTAT_2eSSTM_160 (0<<11) /* 160MB/s 2eSST Xfer Rate */ 670 #define TSI148_LCSR_OTAT_2eSSTM_267 (1<<11) /* 267MB/s 2eSST Xfer Rate */ 671 #define TSI148_LCSR_OTAT_2eSSTM_320 (2<<11) /* 320MB/s 2eSST Xfer Rate */ 672 673 #define TSI148_LCSR_OTAT_TM_M (7<<8) /* Xfer Protocol Mask */ 674 #define TSI148_LCSR_OTAT_TM_SCT (0<<8) /* SCT Xfer Protocol */ 675 #define TSI148_LCSR_OTAT_TM_BLT (1<<8) /* BLT Xfer Protocol */ 676 #define TSI148_LCSR_OTAT_TM_MBLT (2<<8) /* MBLT Xfer Protocol */ 677 #define TSI148_LCSR_OTAT_TM_2eVME (3<<8) /* 2eVME Xfer Protocol */ 678 #define TSI148_LCSR_OTAT_TM_2eSST (4<<8) /* 2eSST Xfer Protocol */ 679 #define TSI148_LCSR_OTAT_TM_2eSSTB (5<<8) /* 2eSST Bcast Xfer Protocol */ 680 681 #define TSI148_LCSR_OTAT_DBW_M (3<<6) /* Max Data Width */ 682 #define TSI148_LCSR_OTAT_DBW_16 (0<<6) /* 16-bit Data Width */ 683 #define TSI148_LCSR_OTAT_DBW_32 (1<<6) /* 32-bit Data Width */ 684 685 #define TSI148_LCSR_OTAT_SUP (1<<5) /* Supervisory Access */ 686 #define TSI148_LCSR_OTAT_PGM (1<<4) /* Program Access */ 687 688 #define TSI148_LCSR_OTAT_AMODE_M (0xf<<0) /* Address Mode Mask */ 689 #define TSI148_LCSR_OTAT_AMODE_A16 (0<<0) /* A16 Address Space */ 690 #define TSI148_LCSR_OTAT_AMODE_A24 (1<<0) /* A24 Address Space */ 691 #define TSI148_LCSR_OTAT_AMODE_A32 (2<<0) /* A32 Address Space */ 692 #define TSI148_LCSR_OTAT_AMODE_A64 (4<<0) /* A32 Address Space */ 693 #define TSI148_LCSR_OTAT_AMODE_CRCSR (5<<0) /* CR/CSR Address Space */ 694 #define TSI148_LCSR_OTAT_AMODE_USER1 (8<<0) /* User1 Address Space */ 695 #define TSI148_LCSR_OTAT_AMODE_USER2 (9<<0) /* User2 Address Space */ 696 #define TSI148_LCSR_OTAT_AMODE_USER3 (10<<0) /* User3 Address Space */ 697 #define TSI148_LCSR_OTAT_AMODE_USER4 (11<<0) /* User4 Address Space */ 698 699 /* 700 * VME Master Control Register CRG+$234 701 */ 702 #define TSI148_LCSR_VMCTRL_VSA (1<<27) /* VMEbus Stop Ack */ 703 #define TSI148_LCSR_VMCTRL_VS (1<<26) /* VMEbus Stop */ 704 #define TSI148_LCSR_VMCTRL_DHB (1<<25) /* Device Has Bus */ 705 #define TSI148_LCSR_VMCTRL_DWB (1<<24) /* Device Wants Bus */ 706 707 #define TSI148_LCSR_VMCTRL_RMWEN (1<<20) /* RMW Enable */ 708 709 #define TSI148_LCSR_VMCTRL_ATO_M (7<<16) /* Master Access Time-out Mask 710 */ 711 #define TSI148_LCSR_VMCTRL_ATO_32 (0<<16) /* 32 us */ 712 #define TSI148_LCSR_VMCTRL_ATO_128 (1<<16) /* 128 us */ 713 #define TSI148_LCSR_VMCTRL_ATO_512 (2<<16) /* 512 us */ 714 #define TSI148_LCSR_VMCTRL_ATO_2M (3<<16) /* 2 ms */ 715 #define TSI148_LCSR_VMCTRL_ATO_8M (4<<16) /* 8 ms */ 716 #define TSI148_LCSR_VMCTRL_ATO_32M (5<<16) /* 32 ms */ 717 #define TSI148_LCSR_VMCTRL_ATO_128M (6<<16) /* 128 ms */ 718 #define TSI148_LCSR_VMCTRL_ATO_DIS (7<<16) /* Disabled */ 719 720 #define TSI148_LCSR_VMCTRL_VTOFF_M (7<<12) /* VMEbus Master Time off */ 721 #define TSI148_LCSR_VMCTRL_VTOFF_0 (0<<12) /* 0us */ 722 #define TSI148_LCSR_VMCTRL_VTOFF_1 (1<<12) /* 1us */ 723 #define TSI148_LCSR_VMCTRL_VTOFF_2 (2<<12) /* 2us */ 724 #define TSI148_LCSR_VMCTRL_VTOFF_4 (3<<12) /* 4us */ 725 #define TSI148_LCSR_VMCTRL_VTOFF_8 (4<<12) /* 8us */ 726 #define TSI148_LCSR_VMCTRL_VTOFF_16 (5<<12) /* 16us */ 727 #define TSI148_LCSR_VMCTRL_VTOFF_32 (6<<12) /* 32us */ 728 #define TSI148_LCSR_VMCTRL_VTOFF_64 (7<<12) /* 64us */ 729 730 #define TSI148_LCSR_VMCTRL_VTON_M (7<<8) /* VMEbus Master Time On */ 731 #define TSI148_LCSR_VMCTRL_VTON_4 (0<<8) /* 8us */ 732 #define TSI148_LCSR_VMCTRL_VTON_8 (1<<8) /* 8us */ 733 #define TSI148_LCSR_VMCTRL_VTON_16 (2<<8) /* 16us */ 734 #define TSI148_LCSR_VMCTRL_VTON_32 (3<<8) /* 32us */ 735 #define TSI148_LCSR_VMCTRL_VTON_64 (4<<8) /* 64us */ 736 #define TSI148_LCSR_VMCTRL_VTON_128 (5<<8) /* 128us */ 737 #define TSI148_LCSR_VMCTRL_VTON_256 (6<<8) /* 256us */ 738 #define TSI148_LCSR_VMCTRL_VTON_512 (7<<8) /* 512us */ 739 740 #define TSI148_LCSR_VMCTRL_VREL_M (3<<3) /* VMEbus Master Rel Mode Mask 741 */ 742 #define TSI148_LCSR_VMCTRL_VREL_T_D (0<<3) /* Time on or Done */ 743 #define TSI148_LCSR_VMCTRL_VREL_T_R_D (1<<3) /* Time on and REQ or Done */ 744 #define TSI148_LCSR_VMCTRL_VREL_T_B_D (2<<3) /* Time on and BCLR or Done */ 745 #define TSI148_LCSR_VMCTRL_VREL_T_D_R (3<<3) /* Time on or Done and REQ */ 746 747 #define TSI148_LCSR_VMCTRL_VFAIR (1<<2) /* VMEbus Master Fair Mode */ 748 #define TSI148_LCSR_VMCTRL_VREQL_M (3<<0) /* VMEbus Master Req Level Mask 749 */ 750 751 /* 752 * VMEbus Control Register CRG+$238 753 */ 754 #define TSI148_LCSR_VCTRL_LRE (1<<31) /* Late Retry Enable */ 755 756 #define TSI148_LCSR_VCTRL_DLT_M (0xF<<24) /* Deadlock Timer */ 757 #define TSI148_LCSR_VCTRL_DLT_OFF (0<<24) /* Deadlock Timer Off */ 758 #define TSI148_LCSR_VCTRL_DLT_16 (1<<24) /* 16 VCLKS */ 759 #define TSI148_LCSR_VCTRL_DLT_32 (2<<24) /* 32 VCLKS */ 760 #define TSI148_LCSR_VCTRL_DLT_64 (3<<24) /* 64 VCLKS */ 761 #define TSI148_LCSR_VCTRL_DLT_128 (4<<24) /* 128 VCLKS */ 762 #define TSI148_LCSR_VCTRL_DLT_256 (5<<24) /* 256 VCLKS */ 763 #define TSI148_LCSR_VCTRL_DLT_512 (6<<24) /* 512 VCLKS */ 764 #define TSI148_LCSR_VCTRL_DLT_1024 (7<<24) /* 1024 VCLKS */ 765 #define TSI148_LCSR_VCTRL_DLT_2048 (8<<24) /* 2048 VCLKS */ 766 #define TSI148_LCSR_VCTRL_DLT_4096 (9<<24) /* 4096 VCLKS */ 767 #define TSI148_LCSR_VCTRL_DLT_8192 (0xA<<24) /* 8192 VCLKS */ 768 #define TSI148_LCSR_VCTRL_DLT_16384 (0xB<<24) /* 16384 VCLKS */ 769 #define TSI148_LCSR_VCTRL_DLT_32768 (0xC<<24) /* 32768 VCLKS */ 770 771 #define TSI148_LCSR_VCTRL_NERBB (1<<20) /* No Early Release of Bus Busy 772 */ 773 774 #define TSI148_LCSR_VCTRL_SRESET (1<<17) /* System Reset */ 775 #define TSI148_LCSR_VCTRL_LRESET (1<<16) /* Local Reset */ 776 777 #define TSI148_LCSR_VCTRL_SFAILAI (1<<15) /* SYSFAIL Auto Slot ID */ 778 #define TSI148_LCSR_VCTRL_BID_M (0x1F<<8) /* Broadcast ID Mask */ 779 780 #define TSI148_LCSR_VCTRL_ATOEN (1<<7) /* Arbiter Time-out Enable */ 781 #define TSI148_LCSR_VCTRL_ROBIN (1<<6) /* VMEbus Round Robin */ 782 783 #define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask 784 */ 785 #define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */ 786 #define TSI148_LCSR_VCTRL_GTO_16 (1<<0) /* 16 us */ 787 #define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */ 788 #define TSI148_LCSR_VCTRL_GTO_64 (3<<0) /* 64 us */ 789 #define TSI148_LCSR_VCTRL_GTO_128 (4<<0) /* 128 us */ 790 #define TSI148_LCSR_VCTRL_GTO_256 (5<<0) /* 256 us */ 791 #define TSI148_LCSR_VCTRL_GTO_512 (6<<0) /* 512 us */ 792 #define TSI148_LCSR_VCTRL_GTO_DIS (7<<0) /* Disabled */ 793 794 /* 795 * VMEbus Status Register CRG + $23C 796 */ 797 #define TSI148_LCSR_VSTAT_CPURST (1<<15) /* Clear power up reset */ 798 #define TSI148_LCSR_VSTAT_BRDFL (1<<14) /* Board fail */ 799 #define TSI148_LCSR_VSTAT_PURSTS (1<<12) /* Power up reset status */ 800 #define TSI148_LCSR_VSTAT_BDFAILS (1<<11) /* Board Fail Status */ 801 #define TSI148_LCSR_VSTAT_SYSFAILS (1<<10) /* System Fail Status */ 802 #define TSI148_LCSR_VSTAT_ACFAILS (1<<9) /* AC fail status */ 803 #define TSI148_LCSR_VSTAT_SCONS (1<<8) /* System Cont Status */ 804 #define TSI148_LCSR_VSTAT_GAP (1<<5) /* Geographic Addr Parity */ 805 #define TSI148_LCSR_VSTAT_GA_M (0x1F<<0) /* Geographic Addr Mask */ 806 807 /* 808 * PCI Configuration Status Register CRG+$240 809 */ 810 #define TSI148_LCSR_PSTAT_REQ64S (1<<6) /* Request 64 status set */ 811 #define TSI148_LCSR_PSTAT_M66ENS (1<<5) /* M66ENS 66Mhz enable */ 812 #define TSI148_LCSR_PSTAT_FRAMES (1<<4) /* Frame Status */ 813 #define TSI148_LCSR_PSTAT_IRDYS (1<<3) /* IRDY status */ 814 #define TSI148_LCSR_PSTAT_DEVSELS (1<<2) /* DEVL status */ 815 #define TSI148_LCSR_PSTAT_STOPS (1<<1) /* STOP status */ 816 #define TSI148_LCSR_PSTAT_TRDYS (1<<0) /* TRDY status */ 817 818 /* 819 * VMEbus Exception Attributes Register CRG + $268 820 */ 821 #define TSI148_LCSR_VEAT_VES (1<<31) /* Status */ 822 #define TSI148_LCSR_VEAT_VEOF (1<<30) /* Overflow */ 823 #define TSI148_LCSR_VEAT_VESCL (1<<29) /* Status Clear */ 824 #define TSI148_LCSR_VEAT_2EOT (1<<21) /* 2e Odd Termination */ 825 #define TSI148_LCSR_VEAT_2EST (1<<20) /* 2e Slave terminated */ 826 #define TSI148_LCSR_VEAT_BERR (1<<19) /* Bus Error */ 827 #define TSI148_LCSR_VEAT_LWORD (1<<18) /* LWORD_ signal state */ 828 #define TSI148_LCSR_VEAT_WRITE (1<<17) /* WRITE_ signal state */ 829 #define TSI148_LCSR_VEAT_IACK (1<<16) /* IACK_ signal state */ 830 #define TSI148_LCSR_VEAT_DS1 (1<<15) /* DS1_ signal state */ 831 #define TSI148_LCSR_VEAT_DS0 (1<<14) /* DS0_ signal state */ 832 #define TSI148_LCSR_VEAT_AM_M (0x3F<<8) /* Address Mode Mask */ 833 #define TSI148_LCSR_VEAT_XAM_M (0xFF<<0) /* Master AMode Mask */ 834 835 836 /* 837 * VMEbus PCI Error Diagnostics PCI/X Attributes Register CRG + $280 838 */ 839 #define TSI148_LCSR_EDPAT_EDPCL (1<<29) 840 841 /* 842 * Inbound Translation Starting Address Lower 843 */ 844 #define TSI148_LCSR_ITSAL6432_M (0xFFFF<<16) /* Mask */ 845 #define TSI148_LCSR_ITSAL24_M (0x00FFF<<12) /* Mask */ 846 #define TSI148_LCSR_ITSAL16_M (0x0000FFF<<4) /* Mask */ 847 848 /* 849 * Inbound Translation Ending Address Lower 850 */ 851 #define TSI148_LCSR_ITEAL6432_M (0xFFFF<<16) /* Mask */ 852 #define TSI148_LCSR_ITEAL24_M (0x00FFF<<12) /* Mask */ 853 #define TSI148_LCSR_ITEAL16_M (0x0000FFF<<4) /* Mask */ 854 855 /* 856 * Inbound Translation Offset Lower 857 */ 858 #define TSI148_LCSR_ITOFFL6432_M (0xFFFF<<16) /* Mask */ 859 #define TSI148_LCSR_ITOFFL24_M (0xFFFFF<<12) /* Mask */ 860 #define TSI148_LCSR_ITOFFL16_M (0xFFFFFFF<<4) /* Mask */ 861 862 /* 863 * Inbound Translation Attribute 864 */ 865 #define TSI148_LCSR_ITAT_EN (1<<31) /* Window Enable */ 866 #define TSI148_LCSR_ITAT_TH (1<<18) /* Prefetch Threshold */ 867 868 #define TSI148_LCSR_ITAT_VFS_M (3<<16) /* Virtual FIFO Size Mask */ 869 #define TSI148_LCSR_ITAT_VFS_64 (0<<16) /* 64 bytes Virtual FIFO Size */ 870 #define TSI148_LCSR_ITAT_VFS_128 (1<<16) /* 128 bytes Virtual FIFO Sz */ 871 #define TSI148_LCSR_ITAT_VFS_256 (2<<16) /* 256 bytes Virtual FIFO Sz */ 872 #define TSI148_LCSR_ITAT_VFS_512 (3<<16) /* 512 bytes Virtual FIFO Sz */ 873 874 #define TSI148_LCSR_ITAT_2eSSTM_M (7<<12) /* 2eSST Xfer Rate Mask */ 875 #define TSI148_LCSR_ITAT_2eSSTM_160 (0<<12) /* 160MB/s 2eSST Xfer Rate */ 876 #define TSI148_LCSR_ITAT_2eSSTM_267 (1<<12) /* 267MB/s 2eSST Xfer Rate */ 877 #define TSI148_LCSR_ITAT_2eSSTM_320 (2<<12) /* 320MB/s 2eSST Xfer Rate */ 878 879 #define TSI148_LCSR_ITAT_2eSSTB (1<<11) /* 2eSST Bcast Xfer Protocol */ 880 #define TSI148_LCSR_ITAT_2eSST (1<<10) /* 2eSST Xfer Protocol */ 881 #define TSI148_LCSR_ITAT_2eVME (1<<9) /* 2eVME Xfer Protocol */ 882 #define TSI148_LCSR_ITAT_MBLT (1<<8) /* MBLT Xfer Protocol */ 883 #define TSI148_LCSR_ITAT_BLT (1<<7) /* BLT Xfer Protocol */ 884 885 #define TSI148_LCSR_ITAT_AS_M (7<<4) /* Address Space Mask */ 886 #define TSI148_LCSR_ITAT_AS_A16 (0<<4) /* A16 Address Space */ 887 #define TSI148_LCSR_ITAT_AS_A24 (1<<4) /* A24 Address Space */ 888 #define TSI148_LCSR_ITAT_AS_A32 (2<<4) /* A32 Address Space */ 889 #define TSI148_LCSR_ITAT_AS_A64 (4<<4) /* A64 Address Space */ 890 891 #define TSI148_LCSR_ITAT_SUPR (1<<3) /* Supervisor Access */ 892 #define TSI148_LCSR_ITAT_NPRIV (1<<2) /* Non-Priv (User) Access */ 893 #define TSI148_LCSR_ITAT_PGM (1<<1) /* Program Access */ 894 #define TSI148_LCSR_ITAT_DATA (1<<0) /* Data Access */ 895 896 /* 897 * GCSR Base Address Lower Address CRG +$404 898 */ 899 #define TSI148_LCSR_GBAL_M (0x7FFFFFF<<5) /* Mask */ 900 901 /* 902 * GCSR Attribute Register CRG + $408 903 */ 904 #define TSI148_LCSR_GCSRAT_EN (1<<7) /* Enable access to GCSR */ 905 906 #define TSI148_LCSR_GCSRAT_AS_M (7<<4) /* Address Space Mask */ 907 #define TSI148_LCSR_GCSRAT_AS_A16 (0<<4) /* Address Space 16 */ 908 #define TSI148_LCSR_GCSRAT_AS_A24 (1<<4) /* Address Space 24 */ 909 #define TSI148_LCSR_GCSRAT_AS_A32 (2<<4) /* Address Space 32 */ 910 #define TSI148_LCSR_GCSRAT_AS_A64 (4<<4) /* Address Space 64 */ 911 912 #define TSI148_LCSR_GCSRAT_SUPR (1<<3) /* Sup set -GCSR decoder */ 913 #define TSI148_LCSR_GCSRAT_NPRIV (1<<2) /* Non-Privliged set - CGSR */ 914 #define TSI148_LCSR_GCSRAT_PGM (1<<1) /* Program set - GCSR decoder */ 915 #define TSI148_LCSR_GCSRAT_DATA (1<<0) /* DATA set GCSR decoder */ 916 917 /* 918 * CRG Base Address Lower Address CRG + $410 919 */ 920 #define TSI148_LCSR_CBAL_M (0xFFFFF<<12) 921 922 /* 923 * CRG Attribute Register CRG + $414 924 */ 925 #define TSI148_LCSR_CRGAT_EN (1<<7) /* Enable PRG Access */ 926 927 #define TSI148_LCSR_CRGAT_AS_M (7<<4) /* Address Space */ 928 #define TSI148_LCSR_CRGAT_AS_A16 (0<<4) /* Address Space 16 */ 929 #define TSI148_LCSR_CRGAT_AS_A24 (1<<4) /* Address Space 24 */ 930 #define TSI148_LCSR_CRGAT_AS_A32 (2<<4) /* Address Space 32 */ 931 #define TSI148_LCSR_CRGAT_AS_A64 (4<<4) /* Address Space 64 */ 932 933 #define TSI148_LCSR_CRGAT_SUPR (1<<3) /* Supervisor Access */ 934 #define TSI148_LCSR_CRGAT_NPRIV (1<<2) /* Non-Privliged(User) Access */ 935 #define TSI148_LCSR_CRGAT_PGM (1<<1) /* Program Access */ 936 #define TSI148_LCSR_CRGAT_DATA (1<<0) /* Data Access */ 937 938 /* 939 * CR/CSR Offset Lower Register CRG + $41C 940 */ 941 #define TSI148_LCSR_CROL_M (0x1FFF<<19) /* Mask */ 942 943 /* 944 * CR/CSR Attribute register CRG + $420 945 */ 946 #define TSI148_LCSR_CRAT_EN (1<<7) /* Enable access to CR/CSR */ 947 948 /* 949 * Location Monitor base address lower register CRG + $428 950 */ 951 #define TSI148_LCSR_LMBAL_M (0x7FFFFFF<<5) /* Mask */ 952 953 /* 954 * Location Monitor Attribute Register CRG + $42C 955 */ 956 #define TSI148_LCSR_LMAT_EN (1<<7) /* Enable Location Monitor */ 957 958 #define TSI148_LCSR_LMAT_AS_M (7<<4) /* Address Space MASK */ 959 #define TSI148_LCSR_LMAT_AS_A16 (0<<4) /* A16 */ 960 #define TSI148_LCSR_LMAT_AS_A24 (1<<4) /* A24 */ 961 #define TSI148_LCSR_LMAT_AS_A32 (2<<4) /* A32 */ 962 #define TSI148_LCSR_LMAT_AS_A64 (4<<4) /* A64 */ 963 964 #define TSI148_LCSR_LMAT_SUPR (1<<3) /* Supervisor Access */ 965 #define TSI148_LCSR_LMAT_NPRIV (1<<2) /* Non-Priv (User) Access */ 966 #define TSI148_LCSR_LMAT_PGM (1<<1) /* Program Access */ 967 #define TSI148_LCSR_LMAT_DATA (1<<0) /* Data Access */ 968 969 /* 970 * Broadcast Pulse Generator Timer Register CRG + $438 971 */ 972 #define TSI148_LCSR_BPGTR_BPGT_M (0xFFFF<<0) /* Mask */ 973 974 /* 975 * Broadcast Programmable Clock Timer Register CRG + $43C 976 */ 977 #define TSI148_LCSR_BPCTR_BPCT_M (0xFFFFFF<<0) /* Mask */ 978 979 /* 980 * VMEbus Interrupt Control Register CRG + $43C 981 */ 982 #define TSI148_LCSR_VICR_CNTS_M (3<<22) /* Cntr Source MASK */ 983 #define TSI148_LCSR_VICR_CNTS_DIS (1<<22) /* Cntr Disable */ 984 #define TSI148_LCSR_VICR_CNTS_IRQ1 (2<<22) /* IRQ1 to Cntr */ 985 #define TSI148_LCSR_VICR_CNTS_IRQ2 (3<<22) /* IRQ2 to Cntr */ 986 987 #define TSI148_LCSR_VICR_EDGIS_M (3<<20) /* Edge interrupt MASK */ 988 #define TSI148_LCSR_VICR_EDGIS_DIS (1<<20) /* Edge interrupt Disable */ 989 #define TSI148_LCSR_VICR_EDGIS_IRQ1 (2<<20) /* IRQ1 to Edge */ 990 #define TSI148_LCSR_VICR_EDGIS_IRQ2 (3<<20) /* IRQ2 to Edge */ 991 992 #define TSI148_LCSR_VICR_IRQIF_M (3<<18) /* IRQ1* Function MASK */ 993 #define TSI148_LCSR_VICR_IRQIF_NORM (1<<18) /* Normal */ 994 #define TSI148_LCSR_VICR_IRQIF_PULSE (2<<18) /* Pulse Generator */ 995 #define TSI148_LCSR_VICR_IRQIF_PROG (3<<18) /* Programmable Clock */ 996 #define TSI148_LCSR_VICR_IRQIF_1U (4<<18) /* 1us Clock */ 997 998 #define TSI148_LCSR_VICR_IRQ2F_M (3<<16) /* IRQ2* Function MASK */ 999 #define TSI148_LCSR_VICR_IRQ2F_NORM (1<<16) /* Normal */ 1000 #define TSI148_LCSR_VICR_IRQ2F_PULSE (2<<16) /* Pulse Generator */ 1001 #define TSI148_LCSR_VICR_IRQ2F_PROG (3<<16) /* Programmable Clock */ 1002 #define TSI148_LCSR_VICR_IRQ2F_1U (4<<16) /* 1us Clock */ 1003 1004 #define TSI148_LCSR_VICR_BIP (1<<15) /* Broadcast Interrupt Pulse */ 1005 1006 #define TSI148_LCSR_VICR_IRQC (1<<12) /* VMEbus IRQ Clear */ 1007 #define TSI148_LCSR_VICR_IRQS (1<<11) /* VMEbus IRQ Status */ 1008 1009 #define TSI148_LCSR_VICR_IRQL_M (7<<8) /* VMEbus SW IRQ Level Mask */ 1010 #define TSI148_LCSR_VICR_IRQL_1 (1<<8) /* VMEbus SW IRQ Level 1 */ 1011 #define TSI148_LCSR_VICR_IRQL_2 (2<<8) /* VMEbus SW IRQ Level 2 */ 1012 #define TSI148_LCSR_VICR_IRQL_3 (3<<8) /* VMEbus SW IRQ Level 3 */ 1013 #define TSI148_LCSR_VICR_IRQL_4 (4<<8) /* VMEbus SW IRQ Level 4 */ 1014 #define TSI148_LCSR_VICR_IRQL_5 (5<<8) /* VMEbus SW IRQ Level 5 */ 1015 #define TSI148_LCSR_VICR_IRQL_6 (6<<8) /* VMEbus SW IRQ Level 6 */ 1016 #define TSI148_LCSR_VICR_IRQL_7 (7<<8) /* VMEbus SW IRQ Level 7 */ 1017 1018 static const int TSI148_LCSR_VICR_IRQL[8] = { 0, TSI148_LCSR_VICR_IRQL_1, 1019 TSI148_LCSR_VICR_IRQL_2, TSI148_LCSR_VICR_IRQL_3, 1020 TSI148_LCSR_VICR_IRQL_4, TSI148_LCSR_VICR_IRQL_5, 1021 TSI148_LCSR_VICR_IRQL_6, TSI148_LCSR_VICR_IRQL_7 }; 1022 1023 #define TSI148_LCSR_VICR_STID_M (0xFF<<0) /* Status/ID Mask */ 1024 1025 /* 1026 * Interrupt Enable Register CRG + $440 1027 */ 1028 #define TSI148_LCSR_INTEN_DMA1EN (1<<25) /* DMAC 1 */ 1029 #define TSI148_LCSR_INTEN_DMA0EN (1<<24) /* DMAC 0 */ 1030 #define TSI148_LCSR_INTEN_LM3EN (1<<23) /* Location Monitor 3 */ 1031 #define TSI148_LCSR_INTEN_LM2EN (1<<22) /* Location Monitor 2 */ 1032 #define TSI148_LCSR_INTEN_LM1EN (1<<21) /* Location Monitor 1 */ 1033 #define TSI148_LCSR_INTEN_LM0EN (1<<20) /* Location Monitor 0 */ 1034 #define TSI148_LCSR_INTEN_MB3EN (1<<19) /* Mail Box 3 */ 1035 #define TSI148_LCSR_INTEN_MB2EN (1<<18) /* Mail Box 2 */ 1036 #define TSI148_LCSR_INTEN_MB1EN (1<<17) /* Mail Box 1 */ 1037 #define TSI148_LCSR_INTEN_MB0EN (1<<16) /* Mail Box 0 */ 1038 #define TSI148_LCSR_INTEN_PERREN (1<<13) /* PCI/X Error */ 1039 #define TSI148_LCSR_INTEN_VERREN (1<<12) /* VMEbus Error */ 1040 #define TSI148_LCSR_INTEN_VIEEN (1<<11) /* VMEbus IRQ Edge */ 1041 #define TSI148_LCSR_INTEN_IACKEN (1<<10) /* IACK */ 1042 #define TSI148_LCSR_INTEN_SYSFLEN (1<<9) /* System Fail */ 1043 #define TSI148_LCSR_INTEN_ACFLEN (1<<8) /* AC Fail */ 1044 #define TSI148_LCSR_INTEN_IRQ7EN (1<<7) /* IRQ7 */ 1045 #define TSI148_LCSR_INTEN_IRQ6EN (1<<6) /* IRQ6 */ 1046 #define TSI148_LCSR_INTEN_IRQ5EN (1<<5) /* IRQ5 */ 1047 #define TSI148_LCSR_INTEN_IRQ4EN (1<<4) /* IRQ4 */ 1048 #define TSI148_LCSR_INTEN_IRQ3EN (1<<3) /* IRQ3 */ 1049 #define TSI148_LCSR_INTEN_IRQ2EN (1<<2) /* IRQ2 */ 1050 #define TSI148_LCSR_INTEN_IRQ1EN (1<<1) /* IRQ1 */ 1051 1052 static const int TSI148_LCSR_INTEN_LMEN[4] = { TSI148_LCSR_INTEN_LM0EN, 1053 TSI148_LCSR_INTEN_LM1EN, 1054 TSI148_LCSR_INTEN_LM2EN, 1055 TSI148_LCSR_INTEN_LM3EN }; 1056 1057 static const int TSI148_LCSR_INTEN_IRQEN[7] = { TSI148_LCSR_INTEN_IRQ1EN, 1058 TSI148_LCSR_INTEN_IRQ2EN, 1059 TSI148_LCSR_INTEN_IRQ3EN, 1060 TSI148_LCSR_INTEN_IRQ4EN, 1061 TSI148_LCSR_INTEN_IRQ5EN, 1062 TSI148_LCSR_INTEN_IRQ6EN, 1063 TSI148_LCSR_INTEN_IRQ7EN }; 1064 1065 /* 1066 * Interrupt Enable Out Register CRG + $444 1067 */ 1068 #define TSI148_LCSR_INTEO_DMA1EO (1<<25) /* DMAC 1 */ 1069 #define TSI148_LCSR_INTEO_DMA0EO (1<<24) /* DMAC 0 */ 1070 #define TSI148_LCSR_INTEO_LM3EO (1<<23) /* Loc Monitor 3 */ 1071 #define TSI148_LCSR_INTEO_LM2EO (1<<22) /* Loc Monitor 2 */ 1072 #define TSI148_LCSR_INTEO_LM1EO (1<<21) /* Loc Monitor 1 */ 1073 #define TSI148_LCSR_INTEO_LM0EO (1<<20) /* Location Monitor 0 */ 1074 #define TSI148_LCSR_INTEO_MB3EO (1<<19) /* Mail Box 3 */ 1075 #define TSI148_LCSR_INTEO_MB2EO (1<<18) /* Mail Box 2 */ 1076 #define TSI148_LCSR_INTEO_MB1EO (1<<17) /* Mail Box 1 */ 1077 #define TSI148_LCSR_INTEO_MB0EO (1<<16) /* Mail Box 0 */ 1078 #define TSI148_LCSR_INTEO_PERREO (1<<13) /* PCI/X Error */ 1079 #define TSI148_LCSR_INTEO_VERREO (1<<12) /* VMEbus Error */ 1080 #define TSI148_LCSR_INTEO_VIEEO (1<<11) /* VMEbus IRQ Edge */ 1081 #define TSI148_LCSR_INTEO_IACKEO (1<<10) /* IACK */ 1082 #define TSI148_LCSR_INTEO_SYSFLEO (1<<9) /* System Fail */ 1083 #define TSI148_LCSR_INTEO_ACFLEO (1<<8) /* AC Fail */ 1084 #define TSI148_LCSR_INTEO_IRQ7EO (1<<7) /* IRQ7 */ 1085 #define TSI148_LCSR_INTEO_IRQ6EO (1<<6) /* IRQ6 */ 1086 #define TSI148_LCSR_INTEO_IRQ5EO (1<<5) /* IRQ5 */ 1087 #define TSI148_LCSR_INTEO_IRQ4EO (1<<4) /* IRQ4 */ 1088 #define TSI148_LCSR_INTEO_IRQ3EO (1<<3) /* IRQ3 */ 1089 #define TSI148_LCSR_INTEO_IRQ2EO (1<<2) /* IRQ2 */ 1090 #define TSI148_LCSR_INTEO_IRQ1EO (1<<1) /* IRQ1 */ 1091 1092 static const int TSI148_LCSR_INTEO_LMEO[4] = { TSI148_LCSR_INTEO_LM0EO, 1093 TSI148_LCSR_INTEO_LM1EO, 1094 TSI148_LCSR_INTEO_LM2EO, 1095 TSI148_LCSR_INTEO_LM3EO }; 1096 1097 static const int TSI148_LCSR_INTEO_IRQEO[7] = { TSI148_LCSR_INTEO_IRQ1EO, 1098 TSI148_LCSR_INTEO_IRQ2EO, 1099 TSI148_LCSR_INTEO_IRQ3EO, 1100 TSI148_LCSR_INTEO_IRQ4EO, 1101 TSI148_LCSR_INTEO_IRQ5EO, 1102 TSI148_LCSR_INTEO_IRQ6EO, 1103 TSI148_LCSR_INTEO_IRQ7EO }; 1104 1105 /* 1106 * Interrupt Status Register CRG + $448 1107 */ 1108 #define TSI148_LCSR_INTS_DMA1S (1<<25) /* DMA 1 */ 1109 #define TSI148_LCSR_INTS_DMA0S (1<<24) /* DMA 0 */ 1110 #define TSI148_LCSR_INTS_LM3S (1<<23) /* Location Monitor 3 */ 1111 #define TSI148_LCSR_INTS_LM2S (1<<22) /* Location Monitor 2 */ 1112 #define TSI148_LCSR_INTS_LM1S (1<<21) /* Location Monitor 1 */ 1113 #define TSI148_LCSR_INTS_LM0S (1<<20) /* Location Monitor 0 */ 1114 #define TSI148_LCSR_INTS_MB3S (1<<19) /* Mail Box 3 */ 1115 #define TSI148_LCSR_INTS_MB2S (1<<18) /* Mail Box 2 */ 1116 #define TSI148_LCSR_INTS_MB1S (1<<17) /* Mail Box 1 */ 1117 #define TSI148_LCSR_INTS_MB0S (1<<16) /* Mail Box 0 */ 1118 #define TSI148_LCSR_INTS_PERRS (1<<13) /* PCI/X Error */ 1119 #define TSI148_LCSR_INTS_VERRS (1<<12) /* VMEbus Error */ 1120 #define TSI148_LCSR_INTS_VIES (1<<11) /* VMEbus IRQ Edge */ 1121 #define TSI148_LCSR_INTS_IACKS (1<<10) /* IACK */ 1122 #define TSI148_LCSR_INTS_SYSFLS (1<<9) /* System Fail */ 1123 #define TSI148_LCSR_INTS_ACFLS (1<<8) /* AC Fail */ 1124 #define TSI148_LCSR_INTS_IRQ7S (1<<7) /* IRQ7 */ 1125 #define TSI148_LCSR_INTS_IRQ6S (1<<6) /* IRQ6 */ 1126 #define TSI148_LCSR_INTS_IRQ5S (1<<5) /* IRQ5 */ 1127 #define TSI148_LCSR_INTS_IRQ4S (1<<4) /* IRQ4 */ 1128 #define TSI148_LCSR_INTS_IRQ3S (1<<3) /* IRQ3 */ 1129 #define TSI148_LCSR_INTS_IRQ2S (1<<2) /* IRQ2 */ 1130 #define TSI148_LCSR_INTS_IRQ1S (1<<1) /* IRQ1 */ 1131 1132 static const int TSI148_LCSR_INTS_LMS[4] = { TSI148_LCSR_INTS_LM0S, 1133 TSI148_LCSR_INTS_LM1S, 1134 TSI148_LCSR_INTS_LM2S, 1135 TSI148_LCSR_INTS_LM3S }; 1136 1137 static const int TSI148_LCSR_INTS_MBS[4] = { TSI148_LCSR_INTS_MB0S, 1138 TSI148_LCSR_INTS_MB1S, 1139 TSI148_LCSR_INTS_MB2S, 1140 TSI148_LCSR_INTS_MB3S }; 1141 1142 /* 1143 * Interrupt Clear Register CRG + $44C 1144 */ 1145 #define TSI148_LCSR_INTC_DMA1C (1<<25) /* DMA 1 */ 1146 #define TSI148_LCSR_INTC_DMA0C (1<<24) /* DMA 0 */ 1147 #define TSI148_LCSR_INTC_LM3C (1<<23) /* Location Monitor 3 */ 1148 #define TSI148_LCSR_INTC_LM2C (1<<22) /* Location Monitor 2 */ 1149 #define TSI148_LCSR_INTC_LM1C (1<<21) /* Location Monitor 1 */ 1150 #define TSI148_LCSR_INTC_LM0C (1<<20) /* Location Monitor 0 */ 1151 #define TSI148_LCSR_INTC_MB3C (1<<19) /* Mail Box 3 */ 1152 #define TSI148_LCSR_INTC_MB2C (1<<18) /* Mail Box 2 */ 1153 #define TSI148_LCSR_INTC_MB1C (1<<17) /* Mail Box 1 */ 1154 #define TSI148_LCSR_INTC_MB0C (1<<16) /* Mail Box 0 */ 1155 #define TSI148_LCSR_INTC_PERRC (1<<13) /* VMEbus Error */ 1156 #define TSI148_LCSR_INTC_VERRC (1<<12) /* VMEbus Access Time-out */ 1157 #define TSI148_LCSR_INTC_VIEC (1<<11) /* VMEbus IRQ Edge */ 1158 #define TSI148_LCSR_INTC_IACKC (1<<10) /* IACK */ 1159 #define TSI148_LCSR_INTC_SYSFLC (1<<9) /* System Fail */ 1160 #define TSI148_LCSR_INTC_ACFLC (1<<8) /* AC Fail */ 1161 1162 static const int TSI148_LCSR_INTC_LMC[4] = { TSI148_LCSR_INTC_LM0C, 1163 TSI148_LCSR_INTC_LM1C, 1164 TSI148_LCSR_INTC_LM2C, 1165 TSI148_LCSR_INTC_LM3C }; 1166 1167 static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C, 1168 TSI148_LCSR_INTC_MB1C, 1169 TSI148_LCSR_INTC_MB2C, 1170 TSI148_LCSR_INTC_MB3C }; 1171 1172 /* 1173 * Interrupt Map Register 1 CRG + $458 1174 */ 1175 #define TSI148_LCSR_INTM1_DMA1M_M (3<<18) /* DMA 1 */ 1176 #define TSI148_LCSR_INTM1_DMA0M_M (3<<16) /* DMA 0 */ 1177 #define TSI148_LCSR_INTM1_LM3M_M (3<<14) /* Location Monitor 3 */ 1178 #define TSI148_LCSR_INTM1_LM2M_M (3<<12) /* Location Monitor 2 */ 1179 #define TSI148_LCSR_INTM1_LM1M_M (3<<10) /* Location Monitor 1 */ 1180 #define TSI148_LCSR_INTM1_LM0M_M (3<<8) /* Location Monitor 0 */ 1181 #define TSI148_LCSR_INTM1_MB3M_M (3<<6) /* Mail Box 3 */ 1182 #define TSI148_LCSR_INTM1_MB2M_M (3<<4) /* Mail Box 2 */ 1183 #define TSI148_LCSR_INTM1_MB1M_M (3<<2) /* Mail Box 1 */ 1184 #define TSI148_LCSR_INTM1_MB0M_M (3<<0) /* Mail Box 0 */ 1185 1186 /* 1187 * Interrupt Map Register 2 CRG + $45C 1188 */ 1189 #define TSI148_LCSR_INTM2_PERRM_M (3<<26) /* PCI Bus Error */ 1190 #define TSI148_LCSR_INTM2_VERRM_M (3<<24) /* VMEbus Error */ 1191 #define TSI148_LCSR_INTM2_VIEM_M (3<<22) /* VMEbus IRQ Edge */ 1192 #define TSI148_LCSR_INTM2_IACKM_M (3<<20) /* IACK */ 1193 #define TSI148_LCSR_INTM2_SYSFLM_M (3<<18) /* System Fail */ 1194 #define TSI148_LCSR_INTM2_ACFLM_M (3<<16) /* AC Fail */ 1195 #define TSI148_LCSR_INTM2_IRQ7M_M (3<<14) /* IRQ7 */ 1196 #define TSI148_LCSR_INTM2_IRQ6M_M (3<<12) /* IRQ6 */ 1197 #define TSI148_LCSR_INTM2_IRQ5M_M (3<<10) /* IRQ5 */ 1198 #define TSI148_LCSR_INTM2_IRQ4M_M (3<<8) /* IRQ4 */ 1199 #define TSI148_LCSR_INTM2_IRQ3M_M (3<<6) /* IRQ3 */ 1200 #define TSI148_LCSR_INTM2_IRQ2M_M (3<<4) /* IRQ2 */ 1201 #define TSI148_LCSR_INTM2_IRQ1M_M (3<<2) /* IRQ1 */ 1202 1203 /* 1204 * DMA Control (0-1) Registers CRG + $500 1205 */ 1206 #define TSI148_LCSR_DCTL_ABT (1<<27) /* Abort */ 1207 #define TSI148_LCSR_DCTL_PAU (1<<26) /* Pause */ 1208 #define TSI148_LCSR_DCTL_DGO (1<<25) /* DMA Go */ 1209 1210 #define TSI148_LCSR_DCTL_MOD (1<<23) /* Mode */ 1211 1212 #define TSI148_LCSR_DCTL_VBKS_M (7<<12) /* VMEbus block Size MASK */ 1213 #define TSI148_LCSR_DCTL_VBKS_32 (0<<12) /* VMEbus block Size 32 */ 1214 #define TSI148_LCSR_DCTL_VBKS_64 (1<<12) /* VMEbus block Size 64 */ 1215 #define TSI148_LCSR_DCTL_VBKS_128 (2<<12) /* VMEbus block Size 128 */ 1216 #define TSI148_LCSR_DCTL_VBKS_256 (3<<12) /* VMEbus block Size 256 */ 1217 #define TSI148_LCSR_DCTL_VBKS_512 (4<<12) /* VMEbus block Size 512 */ 1218 #define TSI148_LCSR_DCTL_VBKS_1024 (5<<12) /* VMEbus block Size 1024 */ 1219 #define TSI148_LCSR_DCTL_VBKS_2048 (6<<12) /* VMEbus block Size 2048 */ 1220 #define TSI148_LCSR_DCTL_VBKS_4096 (7<<12) /* VMEbus block Size 4096 */ 1221 1222 #define TSI148_LCSR_DCTL_VBOT_M (7<<8) /* VMEbus back-off MASK */ 1223 #define TSI148_LCSR_DCTL_VBOT_0 (0<<8) /* VMEbus back-off 0us */ 1224 #define TSI148_LCSR_DCTL_VBOT_1 (1<<8) /* VMEbus back-off 1us */ 1225 #define TSI148_LCSR_DCTL_VBOT_2 (2<<8) /* VMEbus back-off 2us */ 1226 #define TSI148_LCSR_DCTL_VBOT_4 (3<<8) /* VMEbus back-off 4us */ 1227 #define TSI148_LCSR_DCTL_VBOT_8 (4<<8) /* VMEbus back-off 8us */ 1228 #define TSI148_LCSR_DCTL_VBOT_16 (5<<8) /* VMEbus back-off 16us */ 1229 #define TSI148_LCSR_DCTL_VBOT_32 (6<<8) /* VMEbus back-off 32us */ 1230 #define TSI148_LCSR_DCTL_VBOT_64 (7<<8) /* VMEbus back-off 64us */ 1231 1232 #define TSI148_LCSR_DCTL_PBKS_M (7<<4) /* PCI block size MASK */ 1233 #define TSI148_LCSR_DCTL_PBKS_32 (0<<4) /* PCI block size 32 bytes */ 1234 #define TSI148_LCSR_DCTL_PBKS_64 (1<<4) /* PCI block size 64 bytes */ 1235 #define TSI148_LCSR_DCTL_PBKS_128 (2<<4) /* PCI block size 128 bytes */ 1236 #define TSI148_LCSR_DCTL_PBKS_256 (3<<4) /* PCI block size 256 bytes */ 1237 #define TSI148_LCSR_DCTL_PBKS_512 (4<<4) /* PCI block size 512 bytes */ 1238 #define TSI148_LCSR_DCTL_PBKS_1024 (5<<4) /* PCI block size 1024 bytes */ 1239 #define TSI148_LCSR_DCTL_PBKS_2048 (6<<4) /* PCI block size 2048 bytes */ 1240 #define TSI148_LCSR_DCTL_PBKS_4096 (7<<4) /* PCI block size 4096 bytes */ 1241 1242 #define TSI148_LCSR_DCTL_PBOT_M (7<<0) /* PCI back off MASK */ 1243 #define TSI148_LCSR_DCTL_PBOT_0 (0<<0) /* PCI back off 0us */ 1244 #define TSI148_LCSR_DCTL_PBOT_1 (1<<0) /* PCI back off 1us */ 1245 #define TSI148_LCSR_DCTL_PBOT_2 (2<<0) /* PCI back off 2us */ 1246 #define TSI148_LCSR_DCTL_PBOT_4 (3<<0) /* PCI back off 3us */ 1247 #define TSI148_LCSR_DCTL_PBOT_8 (4<<0) /* PCI back off 4us */ 1248 #define TSI148_LCSR_DCTL_PBOT_16 (5<<0) /* PCI back off 8us */ 1249 #define TSI148_LCSR_DCTL_PBOT_32 (6<<0) /* PCI back off 16us */ 1250 #define TSI148_LCSR_DCTL_PBOT_64 (7<<0) /* PCI back off 32us */ 1251 1252 /* 1253 * DMA Status Registers (0-1) CRG + $504 1254 */ 1255 #define TSI148_LCSR_DSTA_SMA (1<<31) /* PCI Signalled Master Abt */ 1256 #define TSI148_LCSR_DSTA_RTA (1<<30) /* PCI Received Target Abt */ 1257 #define TSI148_LCSR_DSTA_MRC (1<<29) /* PCI Max Retry Count */ 1258 #define TSI148_LCSR_DSTA_VBE (1<<28) /* VMEbus error */ 1259 #define TSI148_LCSR_DSTA_ABT (1<<27) /* Abort */ 1260 #define TSI148_LCSR_DSTA_PAU (1<<26) /* Pause */ 1261 #define TSI148_LCSR_DSTA_DON (1<<25) /* Done */ 1262 #define TSI148_LCSR_DSTA_BSY (1<<24) /* Busy */ 1263 1264 /* 1265 * DMA Current Link Address Lower (0-1) 1266 */ 1267 #define TSI148_LCSR_DCLAL_M (0x3FFFFFF<<6) /* Mask */ 1268 1269 /* 1270 * DMA Source Attribute (0-1) Reg 1271 */ 1272 #define TSI148_LCSR_DSAT_TYP_M (3<<28) /* Source Bus Type */ 1273 #define TSI148_LCSR_DSAT_TYP_PCI (0<<28) /* PCI Bus */ 1274 #define TSI148_LCSR_DSAT_TYP_VME (1<<28) /* VMEbus */ 1275 #define TSI148_LCSR_DSAT_TYP_PAT (2<<28) /* Data Pattern */ 1276 1277 #define TSI148_LCSR_DSAT_PSZ (1<<25) /* Pattern Size */ 1278 #define TSI148_LCSR_DSAT_NIN (1<<24) /* No Increment */ 1279 1280 #define TSI148_LCSR_DSAT_2eSSTM_M (3<<11) /* 2eSST Trans Rate Mask */ 1281 #define TSI148_LCSR_DSAT_2eSSTM_160 (0<<11) /* 160 MB/s */ 1282 #define TSI148_LCSR_DSAT_2eSSTM_267 (1<<11) /* 267 MB/s */ 1283 #define TSI148_LCSR_DSAT_2eSSTM_320 (2<<11) /* 320 MB/s */ 1284 1285 #define TSI148_LCSR_DSAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */ 1286 #define TSI148_LCSR_DSAT_TM_SCT (0<<8) /* SCT */ 1287 #define TSI148_LCSR_DSAT_TM_BLT (1<<8) /* BLT */ 1288 #define TSI148_LCSR_DSAT_TM_MBLT (2<<8) /* MBLT */ 1289 #define TSI148_LCSR_DSAT_TM_2eVME (3<<8) /* 2eVME */ 1290 #define TSI148_LCSR_DSAT_TM_2eSST (4<<8) /* 2eSST */ 1291 #define TSI148_LCSR_DSAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */ 1292 1293 #define TSI148_LCSR_DSAT_DBW_M (3<<6) /* Max Data Width MASK */ 1294 #define TSI148_LCSR_DSAT_DBW_16 (0<<6) /* 16 Bits */ 1295 #define TSI148_LCSR_DSAT_DBW_32 (1<<6) /* 32 Bits */ 1296 1297 #define TSI148_LCSR_DSAT_SUP (1<<5) /* Supervisory Mode */ 1298 #define TSI148_LCSR_DSAT_PGM (1<<4) /* Program Mode */ 1299 1300 #define TSI148_LCSR_DSAT_AMODE_M (0xf<<0) /* Address Space Mask */ 1301 #define TSI148_LCSR_DSAT_AMODE_A16 (0<<0) /* A16 */ 1302 #define TSI148_LCSR_DSAT_AMODE_A24 (1<<0) /* A24 */ 1303 #define TSI148_LCSR_DSAT_AMODE_A32 (2<<0) /* A32 */ 1304 #define TSI148_LCSR_DSAT_AMODE_A64 (4<<0) /* A64 */ 1305 #define TSI148_LCSR_DSAT_AMODE_CRCSR (5<<0) /* CR/CSR */ 1306 #define TSI148_LCSR_DSAT_AMODE_USER1 (8<<0) /* User1 */ 1307 #define TSI148_LCSR_DSAT_AMODE_USER2 (9<<0) /* User2 */ 1308 #define TSI148_LCSR_DSAT_AMODE_USER3 (0xa<<0) /* User3 */ 1309 #define TSI148_LCSR_DSAT_AMODE_USER4 (0xb<<0) /* User4 */ 1310 1311 /* 1312 * DMA Destination Attribute Registers (0-1) 1313 */ 1314 #define TSI148_LCSR_DDAT_TYP_PCI (0<<28) /* Destination PCI Bus */ 1315 #define TSI148_LCSR_DDAT_TYP_VME (1<<28) /* Destination VMEbus */ 1316 1317 #define TSI148_LCSR_DDAT_2eSSTM_M (3<<11) /* 2eSST Transfer Rate Mask */ 1318 #define TSI148_LCSR_DDAT_2eSSTM_160 (0<<11) /* 160 MB/s */ 1319 #define TSI148_LCSR_DDAT_2eSSTM_267 (1<<11) /* 267 MB/s */ 1320 #define TSI148_LCSR_DDAT_2eSSTM_320 (2<<11) /* 320 MB/s */ 1321 1322 #define TSI148_LCSR_DDAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */ 1323 #define TSI148_LCSR_DDAT_TM_SCT (0<<8) /* SCT */ 1324 #define TSI148_LCSR_DDAT_TM_BLT (1<<8) /* BLT */ 1325 #define TSI148_LCSR_DDAT_TM_MBLT (2<<8) /* MBLT */ 1326 #define TSI148_LCSR_DDAT_TM_2eVME (3<<8) /* 2eVME */ 1327 #define TSI148_LCSR_DDAT_TM_2eSST (4<<8) /* 2eSST */ 1328 #define TSI148_LCSR_DDAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */ 1329 1330 #define TSI148_LCSR_DDAT_DBW_M (3<<6) /* Max Data Width MASK */ 1331 #define TSI148_LCSR_DDAT_DBW_16 (0<<6) /* 16 Bits */ 1332 #define TSI148_LCSR_DDAT_DBW_32 (1<<6) /* 32 Bits */ 1333 1334 #define TSI148_LCSR_DDAT_SUP (1<<5) /* Supervisory/User Access */ 1335 #define TSI148_LCSR_DDAT_PGM (1<<4) /* Program/Data Access */ 1336 1337 #define TSI148_LCSR_DDAT_AMODE_M (0xf<<0) /* Address Space Mask */ 1338 #define TSI148_LCSR_DDAT_AMODE_A16 (0<<0) /* A16 */ 1339 #define TSI148_LCSR_DDAT_AMODE_A24 (1<<0) /* A24 */ 1340 #define TSI148_LCSR_DDAT_AMODE_A32 (2<<0) /* A32 */ 1341 #define TSI148_LCSR_DDAT_AMODE_A64 (4<<0) /* A64 */ 1342 #define TSI148_LCSR_DDAT_AMODE_CRCSR (5<<0) /* CRC/SR */ 1343 #define TSI148_LCSR_DDAT_AMODE_USER1 (8<<0) /* User1 */ 1344 #define TSI148_LCSR_DDAT_AMODE_USER2 (9<<0) /* User2 */ 1345 #define TSI148_LCSR_DDAT_AMODE_USER3 (0xa<<0) /* User3 */ 1346 #define TSI148_LCSR_DDAT_AMODE_USER4 (0xb<<0) /* User4 */ 1347 1348 /* 1349 * DMA Next Link Address Lower 1350 */ 1351 #define TSI148_LCSR_DNLAL_DNLAL_M (0x3FFFFFF<<6) /* Address Mask */ 1352 #define TSI148_LCSR_DNLAL_LLA (1<<0) /* Last Link Address Indicator */ 1353 1354 /* 1355 * DMA 2eSST Broadcast Select 1356 */ 1357 #define TSI148_LCSR_DBS_M (0x1FFFFF<<0) /* Mask */ 1358 1359 /* 1360 * GCSR Register Group 1361 */ 1362 1363 /* 1364 * GCSR Control and Status Register CRG + $604 1365 */ 1366 #define TSI148_GCSR_GCTRL_LRST (1<<15) /* Local Reset */ 1367 #define TSI148_GCSR_GCTRL_SFAILEN (1<<14) /* System Fail enable */ 1368 #define TSI148_GCSR_GCTRL_BDFAILS (1<<13) /* Board Fail Status */ 1369 #define TSI148_GCSR_GCTRL_SCON (1<<12) /* System Copntroller */ 1370 #define TSI148_GCSR_GCTRL_MEN (1<<11) /* Module Enable (READY) */ 1371 1372 #define TSI148_GCSR_GCTRL_LMI3S (1<<7) /* Loc Monitor 3 Int Status */ 1373 #define TSI148_GCSR_GCTRL_LMI2S (1<<6) /* Loc Monitor 2 Int Status */ 1374 #define TSI148_GCSR_GCTRL_LMI1S (1<<5) /* Loc Monitor 1 Int Status */ 1375 #define TSI148_GCSR_GCTRL_LMI0S (1<<4) /* Loc Monitor 0 Int Status */ 1376 #define TSI148_GCSR_GCTRL_MBI3S (1<<3) /* Mail box 3 Int Status */ 1377 #define TSI148_GCSR_GCTRL_MBI2S (1<<2) /* Mail box 2 Int Status */ 1378 #define TSI148_GCSR_GCTRL_MBI1S (1<<1) /* Mail box 1 Int Status */ 1379 #define TSI148_GCSR_GCTRL_MBI0S (1<<0) /* Mail box 0 Int Status */ 1380 1381 #define TSI148_GCSR_GAP (1<<5) /* Geographic Addr Parity */ 1382 #define TSI148_GCSR_GA_M (0x1F<<0) /* Geographic Address Mask */ 1383 1384 /* 1385 * CR/CSR Register Group 1386 */ 1387 1388 /* 1389 * CR/CSR Bit Clear Register CRG + $FF4 1390 */ 1391 #define TSI148_CRCSR_CSRBCR_LRSTC (1<<7) /* Local Reset Clear */ 1392 #define TSI148_CRCSR_CSRBCR_SFAILC (1<<6) /* System Fail Enable Clear */ 1393 #define TSI148_CRCSR_CSRBCR_BDFAILS (1<<5) /* Board Fail Status */ 1394 #define TSI148_CRCSR_CSRBCR_MENC (1<<4) /* Module Enable Clear */ 1395 #define TSI148_CRCSR_CSRBCR_BERRSC (1<<3) /* Bus Error Status Clear */ 1396 1397 /* 1398 * CR/CSR Bit Set Register CRG+$FF8 1399 */ 1400 #define TSI148_CRCSR_CSRBSR_LISTS (1<<7) /* Local Reset Clear */ 1401 #define TSI148_CRCSR_CSRBSR_SFAILS (1<<6) /* System Fail Enable Clear */ 1402 #define TSI148_CRCSR_CSRBSR_BDFAILS (1<<5) /* Board Fail Status */ 1403 #define TSI148_CRCSR_CSRBSR_MENS (1<<4) /* Module Enable Clear */ 1404 #define TSI148_CRCSR_CSRBSR_BERRS (1<<3) /* Bus Error Status Clear */ 1405 1406 /* 1407 * CR/CSR Base Address Register CRG + FFC 1408 */ 1409 #define TSI148_CRCSR_CBAR_M (0x1F<<3) /* Mask */ 1410 1411 #endif /* TSI148_H */ 1412
