1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NXP (Philips) SCC+++(SCN+++) serial driver
4 *
5 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
6 *
7 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
8 */
9
10 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
11 #define SUPPORT_SYSRQ
12 #endif
13
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/device.h>
19 #include <linux/console.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial.h>
22 #include <linux/io.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/spinlock.h>
26 #include <linux/platform_device.h>
27 #include <linux/platform_data/serial-sccnxp.h>
28 #include <linux/regulator/consumer.h>
29
30 #define SCCNXP_NAME "uart-sccnxp"
31 #define SCCNXP_MAJOR 204
32 #define SCCNXP_MINOR 205
33
34 #define SCCNXP_MR_REG (0x00)
35 # define MR0_BAUD_NORMAL (0 << 0)
36 # define MR0_BAUD_EXT1 (1 << 0)
37 # define MR0_BAUD_EXT2 (5 << 0)
38 # define MR0_FIFO (1 << 3)
39 # define MR0_TXLVL (1 << 4)
40 # define MR1_BITS_5 (0 << 0)
41 # define MR1_BITS_6 (1 << 0)
42 # define MR1_BITS_7 (2 << 0)
43 # define MR1_BITS_8 (3 << 0)
44 # define MR1_PAR_EVN (0 << 2)
45 # define MR1_PAR_ODD (1 << 2)
46 # define MR1_PAR_NO (4 << 2)
47 # define MR2_STOP1 (7 << 0)
48 # define MR2_STOP2 (0xf << 0)
49 #define SCCNXP_SR_REG (0x01)
50 #define SCCNXP_CSR_REG SCCNXP_SR_REG
51 # define SR_RXRDY (1 << 0)
52 # define SR_FULL (1 << 1)
53 # define SR_TXRDY (1 << 2)
54 # define SR_TXEMT (1 << 3)
55 # define SR_OVR (1 << 4)
56 # define SR_PE (1 << 5)
57 # define SR_FE (1 << 6)
58 # define SR_BRK (1 << 7)
59 #define SCCNXP_CR_REG (0x02)
60 # define CR_RX_ENABLE (1 << 0)
61 # define CR_RX_DISABLE (1 << 1)
62 # define CR_TX_ENABLE (1 << 2)
63 # define CR_TX_DISABLE (1 << 3)
64 # define CR_CMD_MRPTR1 (0x01 << 4)
65 # define CR_CMD_RX_RESET (0x02 << 4)
66 # define CR_CMD_TX_RESET (0x03 << 4)
67 # define CR_CMD_STATUS_RESET (0x04 << 4)
68 # define CR_CMD_BREAK_RESET (0x05 << 4)
69 # define CR_CMD_START_BREAK (0x06 << 4)
70 # define CR_CMD_STOP_BREAK (0x07 << 4)
71 # define CR_CMD_MRPTR0 (0x0b << 4)
72 #define SCCNXP_RHR_REG (0x03)
73 #define SCCNXP_THR_REG SCCNXP_RHR_REG
74 #define SCCNXP_IPCR_REG (0x04)
75 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
76 # define ACR_BAUD0 (0 << 7)
77 # define ACR_BAUD1 (1 << 7)
78 # define ACR_TIMER_MODE (6 << 4)
79 #define SCCNXP_ISR_REG (0x05)
80 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
81 # define IMR_TXRDY (1 << 0)
82 # define IMR_RXRDY (1 << 1)
83 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
84 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
85 #define SCCNXP_IPR_REG (0x0d)
86 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
87 #define SCCNXP_SOP_REG (0x0e)
88 #define SCCNXP_ROP_REG (0x0f)
89
90 /* Route helpers */
91 #define MCTRL_MASK(sig) (0xf << (sig))
92 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
93 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
94
95 #define SCCNXP_HAVE_IO 0x00000001
96 #define SCCNXP_HAVE_MR0 0x00000002
97
98 struct sccnxp_chip {
99 const char *name;
100 unsigned int nr;
101 unsigned long freq_min;
102 unsigned long freq_std;
103 unsigned long freq_max;
104 unsigned int flags;
105 unsigned int fifosize;
106 };
107
108 struct sccnxp_port {
109 struct uart_driver uart;
110 struct uart_port port[SCCNXP_MAX_UARTS];
111 bool opened[SCCNXP_MAX_UARTS];
112
113 int irq;
114 u8 imr;
115
116 struct sccnxp_chip *chip;
117
118 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
119 struct console console;
120 #endif
121
122 spinlock_t lock;
123
124 bool poll;
125 struct timer_list timer;
126
127 struct sccnxp_pdata pdata;
128
129 struct regulator *regulator;
130 };
131
132 static const struct sccnxp_chip sc2681 = {
133 .name = "SC2681",
134 .nr = 2,
135 .freq_min = 1000000,
136 .freq_std = 3686400,
137 .freq_max = 4000000,
138 .flags = SCCNXP_HAVE_IO,
139 .fifosize = 3,
140 };
141
142 static const struct sccnxp_chip sc2691 = {
143 .name = "SC2691",
144 .nr = 1,
145 .freq_min = 1000000,
146 .freq_std = 3686400,
147 .freq_max = 4000000,
148 .flags = 0,
149 .fifosize = 3,
150 };
151
152 static const struct sccnxp_chip sc2692 = {
153 .name = "SC2692",
154 .nr = 2,
155 .freq_min = 1000000,
156 .freq_std = 3686400,
157 .freq_max = 4000000,
158 .flags = SCCNXP_HAVE_IO,
159 .fifosize = 3,
160 };
161
162 static const struct sccnxp_chip sc2891 = {
163 .name = "SC2891",
164 .nr = 1,
165 .freq_min = 100000,
166 .freq_std = 3686400,
167 .freq_max = 8000000,
168 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
169 .fifosize = 16,
170 };
171
172 static const struct sccnxp_chip sc2892 = {
173 .name = "SC2892",
174 .nr = 2,
175 .freq_min = 100000,
176 .freq_std = 3686400,
177 .freq_max = 8000000,
178 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
179 .fifosize = 16,
180 };
181
182 static const struct sccnxp_chip sc28202 = {
183 .name = "SC28202",
184 .nr = 2,
185 .freq_min = 1000000,
186 .freq_std = 14745600,
187 .freq_max = 50000000,
188 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
189 .fifosize = 256,
190 };
191
192 static const struct sccnxp_chip sc68681 = {
193 .name = "SC68681",
194 .nr = 2,
195 .freq_min = 1000000,
196 .freq_std = 3686400,
197 .freq_max = 4000000,
198 .flags = SCCNXP_HAVE_IO,
199 .fifosize = 3,
200 };
201
202 static const struct sccnxp_chip sc68692 = {
203 .name = "SC68692",
204 .nr = 2,
205 .freq_min = 1000000,
206 .freq_std = 3686400,
207 .freq_max = 4000000,
208 .flags = SCCNXP_HAVE_IO,
209 .fifosize = 3,
210 };
211
sccnxp_read(struct uart_port * port,u8 reg)212 static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
213 {
214 return readb(port->membase + (reg << port->regshift));
215 }
216
sccnxp_write(struct uart_port * port,u8 reg,u8 v)217 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
218 {
219 writeb(v, port->membase + (reg << port->regshift));
220 }
221
sccnxp_port_read(struct uart_port * port,u8 reg)222 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
223 {
224 return sccnxp_read(port, (port->line << 3) + reg);
225 }
226
sccnxp_port_write(struct uart_port * port,u8 reg,u8 v)227 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
228 {
229 sccnxp_write(port, (port->line << 3) + reg, v);
230 }
231
sccnxp_update_best_err(int a,int b,int * besterr)232 static int sccnxp_update_best_err(int a, int b, int *besterr)
233 {
234 int err = abs(a - b);
235
236 if ((*besterr < 0) || (*besterr > err)) {
237 *besterr = err;
238 return 0;
239 }
240
241 return 1;
242 }
243
244 static const struct {
245 u8 csr;
246 u8 acr;
247 u8 mr0;
248 int baud;
249 } baud_std[] = {
250 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
251 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
252 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
253 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
254 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
255 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
256 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
257 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
258 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
259 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
260 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
261 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
262 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
263 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
264 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
265 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
266 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
267 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
268 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
269 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
270 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
271 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
272 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
273 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
274 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
275 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
276 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
277 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
278 { 0, 0, 0, 0 }
279 };
280
sccnxp_set_baud(struct uart_port * port,int baud)281 static int sccnxp_set_baud(struct uart_port *port, int baud)
282 {
283 struct sccnxp_port *s = dev_get_drvdata(port->dev);
284 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
285 struct sccnxp_chip *chip = s->chip;
286 u8 i, acr = 0, csr = 0, mr0 = 0;
287
288 /* Find best baud from table */
289 for (i = 0; baud_std[i].baud && besterr; i++) {
290 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
291 continue;
292 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
293 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
294 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
295 acr = baud_std[i].acr;
296 csr = baud_std[i].csr;
297 mr0 = baud_std[i].mr0;
298 bestbaud = tmp_baud;
299 }
300 }
301
302 if (chip->flags & SCCNXP_HAVE_MR0) {
303 /* Enable FIFO, set half level for TX */
304 mr0 |= MR0_FIFO | MR0_TXLVL;
305 /* Update MR0 */
306 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
307 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
308 }
309
310 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
311 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
312
313 if (baud != bestbaud)
314 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
315 baud, bestbaud);
316
317 return bestbaud;
318 }
319
sccnxp_enable_irq(struct uart_port * port,int mask)320 static void sccnxp_enable_irq(struct uart_port *port, int mask)
321 {
322 struct sccnxp_port *s = dev_get_drvdata(port->dev);
323
324 s->imr |= mask << (port->line * 4);
325 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
326 }
327
sccnxp_disable_irq(struct uart_port * port,int mask)328 static void sccnxp_disable_irq(struct uart_port *port, int mask)
329 {
330 struct sccnxp_port *s = dev_get_drvdata(port->dev);
331
332 s->imr &= ~(mask << (port->line * 4));
333 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
334 }
335
sccnxp_set_bit(struct uart_port * port,int sig,int state)336 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
337 {
338 u8 bitmask;
339 struct sccnxp_port *s = dev_get_drvdata(port->dev);
340
341 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
342 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
343 if (state)
344 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
345 else
346 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
347 }
348 }
349
sccnxp_handle_rx(struct uart_port * port)350 static void sccnxp_handle_rx(struct uart_port *port)
351 {
352 u8 sr;
353 unsigned int ch, flag;
354
355 for (;;) {
356 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
357 if (!(sr & SR_RXRDY))
358 break;
359 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
360
361 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
362
363 port->icount.rx++;
364 flag = TTY_NORMAL;
365
366 if (unlikely(sr)) {
367 if (sr & SR_BRK) {
368 port->icount.brk++;
369 sccnxp_port_write(port, SCCNXP_CR_REG,
370 CR_CMD_BREAK_RESET);
371 if (uart_handle_break(port))
372 continue;
373 } else if (sr & SR_PE)
374 port->icount.parity++;
375 else if (sr & SR_FE)
376 port->icount.frame++;
377 else if (sr & SR_OVR) {
378 port->icount.overrun++;
379 sccnxp_port_write(port, SCCNXP_CR_REG,
380 CR_CMD_STATUS_RESET);
381 }
382
383 sr &= port->read_status_mask;
384 if (sr & SR_BRK)
385 flag = TTY_BREAK;
386 else if (sr & SR_PE)
387 flag = TTY_PARITY;
388 else if (sr & SR_FE)
389 flag = TTY_FRAME;
390 else if (sr & SR_OVR)
391 flag = TTY_OVERRUN;
392 }
393
394 if (uart_handle_sysrq_char(port, ch))
395 continue;
396
397 if (sr & port->ignore_status_mask)
398 continue;
399
400 uart_insert_char(port, sr, SR_OVR, ch, flag);
401 }
402
403 tty_flip_buffer_push(&port->state->port);
404 }
405
sccnxp_handle_tx(struct uart_port * port)406 static void sccnxp_handle_tx(struct uart_port *port)
407 {
408 u8 sr;
409 struct circ_buf *xmit = &port->state->xmit;
410 struct sccnxp_port *s = dev_get_drvdata(port->dev);
411
412 if (unlikely(port->x_char)) {
413 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
414 port->icount.tx++;
415 port->x_char = 0;
416 return;
417 }
418
419 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
420 /* Disable TX if FIFO is empty */
421 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
422 sccnxp_disable_irq(port, IMR_TXRDY);
423
424 /* Set direction to input */
425 if (s->chip->flags & SCCNXP_HAVE_IO)
426 sccnxp_set_bit(port, DIR_OP, 0);
427 }
428 return;
429 }
430
431 while (!uart_circ_empty(xmit)) {
432 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
433 if (!(sr & SR_TXRDY))
434 break;
435
436 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
437 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
438 port->icount.tx++;
439 }
440
441 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
442 uart_write_wakeup(port);
443 }
444
sccnxp_handle_events(struct sccnxp_port * s)445 static void sccnxp_handle_events(struct sccnxp_port *s)
446 {
447 int i;
448 u8 isr;
449
450 do {
451 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
452 isr &= s->imr;
453 if (!isr)
454 break;
455
456 for (i = 0; i < s->uart.nr; i++) {
457 if (s->opened[i] && (isr & ISR_RXRDY(i)))
458 sccnxp_handle_rx(&s->port[i]);
459 if (s->opened[i] && (isr & ISR_TXRDY(i)))
460 sccnxp_handle_tx(&s->port[i]);
461 }
462 } while (1);
463 }
464
sccnxp_timer(struct timer_list * t)465 static void sccnxp_timer(struct timer_list *t)
466 {
467 struct sccnxp_port *s = from_timer(s, t, timer);
468 unsigned long flags;
469
470 spin_lock_irqsave(&s->lock, flags);
471 sccnxp_handle_events(s);
472 spin_unlock_irqrestore(&s->lock, flags);
473
474 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
475 }
476
sccnxp_ist(int irq,void * dev_id)477 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
478 {
479 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
480 unsigned long flags;
481
482 spin_lock_irqsave(&s->lock, flags);
483 sccnxp_handle_events(s);
484 spin_unlock_irqrestore(&s->lock, flags);
485
486 return IRQ_HANDLED;
487 }
488
sccnxp_start_tx(struct uart_port * port)489 static void sccnxp_start_tx(struct uart_port *port)
490 {
491 struct sccnxp_port *s = dev_get_drvdata(port->dev);
492 unsigned long flags;
493
494 spin_lock_irqsave(&s->lock, flags);
495
496 /* Set direction to output */
497 if (s->chip->flags & SCCNXP_HAVE_IO)
498 sccnxp_set_bit(port, DIR_OP, 1);
499
500 sccnxp_enable_irq(port, IMR_TXRDY);
501
502 spin_unlock_irqrestore(&s->lock, flags);
503 }
504
sccnxp_stop_tx(struct uart_port * port)505 static void sccnxp_stop_tx(struct uart_port *port)
506 {
507 /* Do nothing */
508 }
509
sccnxp_stop_rx(struct uart_port * port)510 static void sccnxp_stop_rx(struct uart_port *port)
511 {
512 struct sccnxp_port *s = dev_get_drvdata(port->dev);
513 unsigned long flags;
514
515 spin_lock_irqsave(&s->lock, flags);
516 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
517 spin_unlock_irqrestore(&s->lock, flags);
518 }
519
sccnxp_tx_empty(struct uart_port * port)520 static unsigned int sccnxp_tx_empty(struct uart_port *port)
521 {
522 u8 val;
523 unsigned long flags;
524 struct sccnxp_port *s = dev_get_drvdata(port->dev);
525
526 spin_lock_irqsave(&s->lock, flags);
527 val = sccnxp_port_read(port, SCCNXP_SR_REG);
528 spin_unlock_irqrestore(&s->lock, flags);
529
530 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
531 }
532
sccnxp_set_mctrl(struct uart_port * port,unsigned int mctrl)533 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
534 {
535 struct sccnxp_port *s = dev_get_drvdata(port->dev);
536 unsigned long flags;
537
538 if (!(s->chip->flags & SCCNXP_HAVE_IO))
539 return;
540
541 spin_lock_irqsave(&s->lock, flags);
542
543 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
544 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
545
546 spin_unlock_irqrestore(&s->lock, flags);
547 }
548
sccnxp_get_mctrl(struct uart_port * port)549 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
550 {
551 u8 bitmask, ipr;
552 unsigned long flags;
553 struct sccnxp_port *s = dev_get_drvdata(port->dev);
554 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
555
556 if (!(s->chip->flags & SCCNXP_HAVE_IO))
557 return mctrl;
558
559 spin_lock_irqsave(&s->lock, flags);
560
561 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
562
563 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
564 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
565 DSR_IP);
566 mctrl &= ~TIOCM_DSR;
567 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
568 }
569 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
570 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
571 CTS_IP);
572 mctrl &= ~TIOCM_CTS;
573 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
574 }
575 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
576 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
577 DCD_IP);
578 mctrl &= ~TIOCM_CAR;
579 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
580 }
581 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
582 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
583 RNG_IP);
584 mctrl &= ~TIOCM_RNG;
585 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
586 }
587
588 spin_unlock_irqrestore(&s->lock, flags);
589
590 return mctrl;
591 }
592
sccnxp_break_ctl(struct uart_port * port,int break_state)593 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
594 {
595 struct sccnxp_port *s = dev_get_drvdata(port->dev);
596 unsigned long flags;
597
598 spin_lock_irqsave(&s->lock, flags);
599 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
600 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
601 spin_unlock_irqrestore(&s->lock, flags);
602 }
603
sccnxp_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)604 static void sccnxp_set_termios(struct uart_port *port,
605 struct ktermios *termios, struct ktermios *old)
606 {
607 struct sccnxp_port *s = dev_get_drvdata(port->dev);
608 unsigned long flags;
609 u8 mr1, mr2;
610 int baud;
611
612 spin_lock_irqsave(&s->lock, flags);
613
614 /* Mask termios capabilities we don't support */
615 termios->c_cflag &= ~CMSPAR;
616
617 /* Disable RX & TX, reset break condition, status and FIFOs */
618 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
619 CR_RX_DISABLE | CR_TX_DISABLE);
620 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
621 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
622 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
623
624 /* Word size */
625 switch (termios->c_cflag & CSIZE) {
626 case CS5:
627 mr1 = MR1_BITS_5;
628 break;
629 case CS6:
630 mr1 = MR1_BITS_6;
631 break;
632 case CS7:
633 mr1 = MR1_BITS_7;
634 break;
635 case CS8:
636 default:
637 mr1 = MR1_BITS_8;
638 break;
639 }
640
641 /* Parity */
642 if (termios->c_cflag & PARENB) {
643 if (termios->c_cflag & PARODD)
644 mr1 |= MR1_PAR_ODD;
645 } else
646 mr1 |= MR1_PAR_NO;
647
648 /* Stop bits */
649 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
650
651 /* Update desired format */
652 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
653 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
654 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
655
656 /* Set read status mask */
657 port->read_status_mask = SR_OVR;
658 if (termios->c_iflag & INPCK)
659 port->read_status_mask |= SR_PE | SR_FE;
660 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
661 port->read_status_mask |= SR_BRK;
662
663 /* Set status ignore mask */
664 port->ignore_status_mask = 0;
665 if (termios->c_iflag & IGNBRK)
666 port->ignore_status_mask |= SR_BRK;
667 if (termios->c_iflag & IGNPAR)
668 port->ignore_status_mask |= SR_PE;
669 if (!(termios->c_cflag & CREAD))
670 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
671
672 /* Setup baudrate */
673 baud = uart_get_baud_rate(port, termios, old, 50,
674 (s->chip->flags & SCCNXP_HAVE_MR0) ?
675 230400 : 38400);
676 baud = sccnxp_set_baud(port, baud);
677
678 /* Update timeout according to new baud rate */
679 uart_update_timeout(port, termios->c_cflag, baud);
680
681 /* Report actual baudrate back to core */
682 if (tty_termios_baud_rate(termios))
683 tty_termios_encode_baud_rate(termios, baud, baud);
684
685 /* Enable RX & TX */
686 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
687
688 spin_unlock_irqrestore(&s->lock, flags);
689 }
690
sccnxp_startup(struct uart_port * port)691 static int sccnxp_startup(struct uart_port *port)
692 {
693 struct sccnxp_port *s = dev_get_drvdata(port->dev);
694 unsigned long flags;
695
696 spin_lock_irqsave(&s->lock, flags);
697
698 if (s->chip->flags & SCCNXP_HAVE_IO) {
699 /* Outputs are controlled manually */
700 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
701 }
702
703 /* Reset break condition, status and FIFOs */
704 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
705 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
706 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
707 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
708
709 /* Enable RX & TX */
710 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
711
712 /* Enable RX interrupt */
713 sccnxp_enable_irq(port, IMR_RXRDY);
714
715 s->opened[port->line] = 1;
716
717 spin_unlock_irqrestore(&s->lock, flags);
718
719 return 0;
720 }
721
sccnxp_shutdown(struct uart_port * port)722 static void sccnxp_shutdown(struct uart_port *port)
723 {
724 struct sccnxp_port *s = dev_get_drvdata(port->dev);
725 unsigned long flags;
726
727 spin_lock_irqsave(&s->lock, flags);
728
729 s->opened[port->line] = 0;
730
731 /* Disable interrupts */
732 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
733
734 /* Disable TX & RX */
735 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
736
737 /* Leave direction to input */
738 if (s->chip->flags & SCCNXP_HAVE_IO)
739 sccnxp_set_bit(port, DIR_OP, 0);
740
741 spin_unlock_irqrestore(&s->lock, flags);
742 }
743
sccnxp_type(struct uart_port * port)744 static const char *sccnxp_type(struct uart_port *port)
745 {
746 struct sccnxp_port *s = dev_get_drvdata(port->dev);
747
748 return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
749 }
750
sccnxp_release_port(struct uart_port * port)751 static void sccnxp_release_port(struct uart_port *port)
752 {
753 /* Do nothing */
754 }
755
sccnxp_request_port(struct uart_port * port)756 static int sccnxp_request_port(struct uart_port *port)
757 {
758 /* Do nothing */
759 return 0;
760 }
761
sccnxp_config_port(struct uart_port * port,int flags)762 static void sccnxp_config_port(struct uart_port *port, int flags)
763 {
764 if (flags & UART_CONFIG_TYPE)
765 port->type = PORT_SC26XX;
766 }
767
sccnxp_verify_port(struct uart_port * port,struct serial_struct * s)768 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
769 {
770 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
771 return 0;
772 if (s->irq == port->irq)
773 return 0;
774
775 return -EINVAL;
776 }
777
778 static const struct uart_ops sccnxp_ops = {
779 .tx_empty = sccnxp_tx_empty,
780 .set_mctrl = sccnxp_set_mctrl,
781 .get_mctrl = sccnxp_get_mctrl,
782 .stop_tx = sccnxp_stop_tx,
783 .start_tx = sccnxp_start_tx,
784 .stop_rx = sccnxp_stop_rx,
785 .break_ctl = sccnxp_break_ctl,
786 .startup = sccnxp_startup,
787 .shutdown = sccnxp_shutdown,
788 .set_termios = sccnxp_set_termios,
789 .type = sccnxp_type,
790 .release_port = sccnxp_release_port,
791 .request_port = sccnxp_request_port,
792 .config_port = sccnxp_config_port,
793 .verify_port = sccnxp_verify_port,
794 };
795
796 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
sccnxp_console_putchar(struct uart_port * port,int c)797 static void sccnxp_console_putchar(struct uart_port *port, int c)
798 {
799 int tryes = 100000;
800
801 while (tryes--) {
802 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
803 sccnxp_port_write(port, SCCNXP_THR_REG, c);
804 break;
805 }
806 barrier();
807 }
808 }
809
sccnxp_console_write(struct console * co,const char * c,unsigned n)810 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
811 {
812 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
813 struct uart_port *port = &s->port[co->index];
814 unsigned long flags;
815
816 spin_lock_irqsave(&s->lock, flags);
817 uart_console_write(port, c, n, sccnxp_console_putchar);
818 spin_unlock_irqrestore(&s->lock, flags);
819 }
820
sccnxp_console_setup(struct console * co,char * options)821 static int sccnxp_console_setup(struct console *co, char *options)
822 {
823 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
824 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
825 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
826
827 if (options)
828 uart_parse_options(options, &baud, &parity, &bits, &flow);
829
830 return uart_set_options(port, co, baud, parity, bits, flow);
831 }
832 #endif
833
834 static const struct platform_device_id sccnxp_id_table[] = {
835 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, },
836 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, },
837 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, },
838 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, },
839 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, },
840 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, },
841 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, },
842 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, },
843 { }
844 };
845 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
846
sccnxp_probe(struct platform_device * pdev)847 static int sccnxp_probe(struct platform_device *pdev)
848 {
849 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
850 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
851 int i, ret, uartclk;
852 struct sccnxp_port *s;
853 void __iomem *membase;
854 struct clk *clk;
855
856 membase = devm_ioremap_resource(&pdev->dev, res);
857 if (IS_ERR(membase))
858 return PTR_ERR(membase);
859
860 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
861 if (!s) {
862 dev_err(&pdev->dev, "Error allocating port structure\n");
863 return -ENOMEM;
864 }
865 platform_set_drvdata(pdev, s);
866
867 spin_lock_init(&s->lock);
868
869 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
870
871 s->regulator = devm_regulator_get(&pdev->dev, "vcc");
872 if (!IS_ERR(s->regulator)) {
873 ret = regulator_enable(s->regulator);
874 if (ret) {
875 dev_err(&pdev->dev,
876 "Failed to enable regulator: %i\n", ret);
877 return ret;
878 }
879 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
880 return -EPROBE_DEFER;
881
882 clk = devm_clk_get(&pdev->dev, NULL);
883 if (IS_ERR(clk)) {
884 ret = PTR_ERR(clk);
885 if (ret == -EPROBE_DEFER)
886 goto err_out;
887 uartclk = 0;
888 } else {
889 ret = clk_prepare_enable(clk);
890 if (ret)
891 goto err_out;
892
893 ret = devm_add_action_or_reset(&pdev->dev,
894 (void(*)(void *))clk_disable_unprepare,
895 clk);
896 if (ret)
897 goto err_out;
898
899 uartclk = clk_get_rate(clk);
900 }
901
902 if (!uartclk) {
903 dev_notice(&pdev->dev, "Using default clock frequency\n");
904 uartclk = s->chip->freq_std;
905 }
906
907 /* Check input frequency */
908 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
909 dev_err(&pdev->dev, "Frequency out of bounds\n");
910 ret = -EINVAL;
911 goto err_out;
912 }
913
914 if (pdata)
915 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
916
917 if (s->pdata.poll_time_us) {
918 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
919 s->pdata.poll_time_us);
920 s->poll = 1;
921 }
922
923 if (!s->poll) {
924 s->irq = platform_get_irq(pdev, 0);
925 if (s->irq < 0) {
926 dev_err(&pdev->dev, "Missing irq resource data\n");
927 ret = -ENXIO;
928 goto err_out;
929 }
930 }
931
932 s->uart.owner = THIS_MODULE;
933 s->uart.dev_name = "ttySC";
934 s->uart.major = SCCNXP_MAJOR;
935 s->uart.minor = SCCNXP_MINOR;
936 s->uart.nr = s->chip->nr;
937 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
938 s->uart.cons = &s->console;
939 s->uart.cons->device = uart_console_device;
940 s->uart.cons->write = sccnxp_console_write;
941 s->uart.cons->setup = sccnxp_console_setup;
942 s->uart.cons->flags = CON_PRINTBUFFER;
943 s->uart.cons->index = -1;
944 s->uart.cons->data = s;
945 strcpy(s->uart.cons->name, "ttySC");
946 #endif
947 ret = uart_register_driver(&s->uart);
948 if (ret) {
949 dev_err(&pdev->dev, "Registering UART driver failed\n");
950 goto err_out;
951 }
952
953 for (i = 0; i < s->uart.nr; i++) {
954 s->port[i].line = i;
955 s->port[i].dev = &pdev->dev;
956 s->port[i].irq = s->irq;
957 s->port[i].type = PORT_SC26XX;
958 s->port[i].fifosize = s->chip->fifosize;
959 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
960 s->port[i].iotype = UPIO_MEM;
961 s->port[i].mapbase = res->start;
962 s->port[i].membase = membase;
963 s->port[i].regshift = s->pdata.reg_shift;
964 s->port[i].uartclk = uartclk;
965 s->port[i].ops = &sccnxp_ops;
966 uart_add_one_port(&s->uart, &s->port[i]);
967 /* Set direction to input */
968 if (s->chip->flags & SCCNXP_HAVE_IO)
969 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
970 }
971
972 /* Disable interrupts */
973 s->imr = 0;
974 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
975
976 if (!s->poll) {
977 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
978 sccnxp_ist,
979 IRQF_TRIGGER_FALLING |
980 IRQF_ONESHOT,
981 dev_name(&pdev->dev), s);
982 if (!ret)
983 return 0;
984
985 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
986 } else {
987 timer_setup(&s->timer, sccnxp_timer, 0);
988 mod_timer(&s->timer, jiffies +
989 usecs_to_jiffies(s->pdata.poll_time_us));
990 return 0;
991 }
992
993 uart_unregister_driver(&s->uart);
994 err_out:
995 if (!IS_ERR(s->regulator))
996 regulator_disable(s->regulator);
997
998 return ret;
999 }
1000
sccnxp_remove(struct platform_device * pdev)1001 static int sccnxp_remove(struct platform_device *pdev)
1002 {
1003 int i;
1004 struct sccnxp_port *s = platform_get_drvdata(pdev);
1005
1006 if (!s->poll)
1007 devm_free_irq(&pdev->dev, s->irq, s);
1008 else
1009 del_timer_sync(&s->timer);
1010
1011 for (i = 0; i < s->uart.nr; i++)
1012 uart_remove_one_port(&s->uart, &s->port[i]);
1013
1014 uart_unregister_driver(&s->uart);
1015
1016 if (!IS_ERR(s->regulator))
1017 return regulator_disable(s->regulator);
1018
1019 return 0;
1020 }
1021
1022 static struct platform_driver sccnxp_uart_driver = {
1023 .driver = {
1024 .name = SCCNXP_NAME,
1025 },
1026 .probe = sccnxp_probe,
1027 .remove = sccnxp_remove,
1028 .id_table = sccnxp_id_table,
1029 };
1030 module_platform_driver(sccnxp_uart_driver);
1031
1032 MODULE_LICENSE("GPL v2");
1033 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1034 MODULE_DESCRIPTION("SCCNXP serial driver");
1035
