1 /* 2 * DRA752 bandgap registers, bitfields and temperature definitions 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5 * Contact: 6 * Eduardo Valentin <eduardo.valentin@ti.com> 7 * Tero Kristo <t-kristo@ti.com> 8 * 9 * This is an auto generated file. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * version 2 as published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 23 * 02110-1301 USA 24 * 25 */ 26 #ifndef __DRA752_BANDGAP_H 27 #define __DRA752_BANDGAP_H 28 29 /** 30 * *** DRA752 *** 31 * 32 * Below, in sequence, are the Register definitions, 33 * the bitfields and the temperature definitions for DRA752. 34 */ 35 36 /** 37 * DRA752 register definitions 38 * 39 * Registers are defined as offsets. The offsets are 40 * relative to FUSE_OPP_BGAP_GPU on DRA752. 41 * DRA752_BANDGAP_BASE 0x4a0021e0 42 * 43 * Register below are grouped by domain (not necessarily in offset order) 44 */ 45 46 47 /* DRA752.common register offsets */ 48 #define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0 49 #define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8 50 #define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c 51 #define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8 52 53 /* DRA752.core register offsets */ 54 #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8 55 #define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154 56 #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac 57 #define DRA752_DTEMP_CORE_1_OFFSET 0x20c 58 #define DRA752_DTEMP_CORE_2_OFFSET 0x210 59 60 /* DRA752.iva register offsets */ 61 #define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388 62 #define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398 63 #define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4 64 #define DRA752_DTEMP_IVA_1_OFFSET 0x3d4 65 #define DRA752_DTEMP_IVA_2_OFFSET 0x3d8 66 67 /* DRA752.mpu register offsets */ 68 #define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4 69 #define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c 70 #define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4 71 #define DRA752_DTEMP_MPU_1_OFFSET 0x1e4 72 #define DRA752_DTEMP_MPU_2_OFFSET 0x1e8 73 74 /* DRA752.dspeve register offsets */ 75 #define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384 76 #define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394 77 #define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0 78 #define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0 79 #define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4 80 81 /* DRA752.gpu register offsets */ 82 #define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0 83 #define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150 84 #define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8 85 #define DRA752_DTEMP_GPU_1_OFFSET 0x1f8 86 #define DRA752_DTEMP_GPU_2_OFFSET 0x1fc 87 88 /** 89 * Register bitfields for DRA752 90 * 91 * All the macros bellow define the required bits for 92 * controlling temperature on DRA752. Bit defines are 93 * grouped by register. 94 */ 95 96 /* DRA752.BANDGAP_STATUS_1 */ 97 #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5) 98 #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4) 99 #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3) 100 #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2) 101 #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1) 102 #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0) 103 104 /* DRA752.BANDGAP_CTRL_2 */ 105 #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22) 106 #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21) 107 #define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3) 108 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2) 109 #define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1) 110 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0) 111 112 /* DRA752.BANDGAP_STATUS_2 */ 113 #define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3) 114 #define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2) 115 #define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1) 116 #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0) 117 118 /* DRA752.BANDGAP_CTRL_1 */ 119 #define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27) 120 #define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23) 121 #define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22) 122 #define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21) 123 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5) 124 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4) 125 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3) 126 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2) 127 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1) 128 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0) 129 130 /* DRA752.TEMP_SENSOR */ 131 #define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11) 132 #define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10) 133 #define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0) 134 135 /* DRA752.BANDGAP_THRESHOLD */ 136 #define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16) 137 #define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0) 138 139 /** 140 * Temperature limits and thresholds for DRA752 141 * 142 * All the macros bellow are definitions for handling the 143 * ADC conversions and representation of temperature limits 144 * and thresholds for DRA752. Definitions are grouped 145 * by temperature domain. 146 */ 147 148 /* DRA752.common temperature definitions */ 149 /* ADC conversion table limits */ 150 #define DRA752_ADC_START_VALUE 540 151 #define DRA752_ADC_END_VALUE 945 152 153 /* DRA752.GPU temperature definitions */ 154 /* bandgap clock limits */ 155 #define DRA752_GPU_MAX_FREQ 1500000 156 #define DRA752_GPU_MIN_FREQ 1000000 157 /* interrupts thresholds */ 158 #define DRA752_GPU_T_HOT 800 159 #define DRA752_GPU_T_COLD 795 160 161 /* DRA752.MPU temperature definitions */ 162 /* bandgap clock limits */ 163 #define DRA752_MPU_MAX_FREQ 1500000 164 #define DRA752_MPU_MIN_FREQ 1000000 165 /* interrupts thresholds */ 166 #define DRA752_MPU_T_HOT 800 167 #define DRA752_MPU_T_COLD 795 168 169 /* DRA752.CORE temperature definitions */ 170 /* bandgap clock limits */ 171 #define DRA752_CORE_MAX_FREQ 1500000 172 #define DRA752_CORE_MIN_FREQ 1000000 173 /* interrupts thresholds */ 174 #define DRA752_CORE_T_HOT 800 175 #define DRA752_CORE_T_COLD 795 176 177 /* DRA752.DSPEVE temperature definitions */ 178 /* bandgap clock limits */ 179 #define DRA752_DSPEVE_MAX_FREQ 1500000 180 #define DRA752_DSPEVE_MIN_FREQ 1000000 181 /* interrupts thresholds */ 182 #define DRA752_DSPEVE_T_HOT 800 183 #define DRA752_DSPEVE_T_COLD 795 184 185 /* DRA752.IVA temperature definitions */ 186 /* bandgap clock limits */ 187 #define DRA752_IVA_MAX_FREQ 1500000 188 #define DRA752_IVA_MIN_FREQ 1000000 189 /* interrupts thresholds */ 190 #define DRA752_IVA_T_HOT 800 191 #define DRA752_IVA_T_COLD 795 192 193 #endif /* __DRA752_BANDGAP_H */ 194
