1 /*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
4 * Sascha Hauer <s.hauer@pengutronix.de>
5 * Dawei Chien <dawei.chien@mediatek.com>
6 * Louis Yu <louis.yu@mediatek.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/nvmem-consumer.h>
24 #include <linux/of.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <linux/io.h>
30 #include <linux/thermal.h>
31 #include <linux/reset.h>
32 #include <linux/types.h>
33
34 /* AUXADC Registers */
35 #define AUXADC_CON1_SET_V 0x008
36 #define AUXADC_CON1_CLR_V 0x00c
37 #define AUXADC_CON2_V 0x010
38 #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
39
40 #define APMIXED_SYS_TS_CON1 0x604
41
42 /* Thermal Controller Registers */
43 #define TEMP_MONCTL0 0x000
44 #define TEMP_MONCTL1 0x004
45 #define TEMP_MONCTL2 0x008
46 #define TEMP_MONIDET0 0x014
47 #define TEMP_MONIDET1 0x018
48 #define TEMP_MSRCTL0 0x038
49 #define TEMP_AHBPOLL 0x040
50 #define TEMP_AHBTO 0x044
51 #define TEMP_ADCPNP0 0x048
52 #define TEMP_ADCPNP1 0x04c
53 #define TEMP_ADCPNP2 0x050
54 #define TEMP_ADCPNP3 0x0b4
55
56 #define TEMP_ADCMUX 0x054
57 #define TEMP_ADCEN 0x060
58 #define TEMP_PNPMUXADDR 0x064
59 #define TEMP_ADCMUXADDR 0x068
60 #define TEMP_ADCENADDR 0x074
61 #define TEMP_ADCVALIDADDR 0x078
62 #define TEMP_ADCVOLTADDR 0x07c
63 #define TEMP_RDCTRL 0x080
64 #define TEMP_ADCVALIDMASK 0x084
65 #define TEMP_ADCVOLTAGESHIFT 0x088
66 #define TEMP_ADCWRITECTRL 0x08c
67 #define TEMP_MSR0 0x090
68 #define TEMP_MSR1 0x094
69 #define TEMP_MSR2 0x098
70 #define TEMP_MSR3 0x0B8
71
72 #define TEMP_SPARE0 0x0f0
73
74 #define PTPCORESEL 0x400
75
76 #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
77
78 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
79 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
80
81 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
82
83 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
84 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
85
86 #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
87 #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
88
89 /* MT8173 thermal sensors */
90 #define MT8173_TS1 0
91 #define MT8173_TS2 1
92 #define MT8173_TS3 2
93 #define MT8173_TS4 3
94 #define MT8173_TSABB 4
95
96 /* AUXADC channel 11 is used for the temperature sensors */
97 #define MT8173_TEMP_AUXADC_CHANNEL 11
98
99 /* The total number of temperature sensors in the MT8173 */
100 #define MT8173_NUM_SENSORS 5
101
102 /* The number of banks in the MT8173 */
103 #define MT8173_NUM_ZONES 4
104
105 /* The number of sensing points per bank */
106 #define MT8173_NUM_SENSORS_PER_ZONE 4
107
108 /*
109 * Layout of the fuses providing the calibration data
110 * These macros could be used for MT8173, MT2701, and MT2712.
111 * MT8173 has 5 sensors and needs 5 VTS calibration data.
112 * MT2701 has 3 sensors and needs 3 VTS calibration data.
113 * MT2712 has 4 sensors and needs 4 VTS calibration data.
114 */
115 #define MT8173_CALIB_BUF0_VALID BIT(0)
116 #define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff)
117 #define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff)
118 #define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff)
119 #define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff)
120 #define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff)
121 #define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff)
122 #define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f)
123 #define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f)
124 #define MT8173_CALIB_BUF0_O_SLOPE_SIGN(x) (((x) >> 7) & 0x1)
125 #define MT8173_CALIB_BUF1_ID(x) (((x) >> 9) & 0x1)
126
127 /* MT2701 thermal sensors */
128 #define MT2701_TS1 0
129 #define MT2701_TS2 1
130 #define MT2701_TSABB 2
131
132 /* AUXADC channel 11 is used for the temperature sensors */
133 #define MT2701_TEMP_AUXADC_CHANNEL 11
134
135 /* The total number of temperature sensors in the MT2701 */
136 #define MT2701_NUM_SENSORS 3
137
138 /* The number of sensing points per bank */
139 #define MT2701_NUM_SENSORS_PER_ZONE 3
140
141 /* MT2712 thermal sensors */
142 #define MT2712_TS1 0
143 #define MT2712_TS2 1
144 #define MT2712_TS3 2
145 #define MT2712_TS4 3
146
147 /* AUXADC channel 11 is used for the temperature sensors */
148 #define MT2712_TEMP_AUXADC_CHANNEL 11
149
150 /* The total number of temperature sensors in the MT2712 */
151 #define MT2712_NUM_SENSORS 4
152
153 /* The number of sensing points per bank */
154 #define MT2712_NUM_SENSORS_PER_ZONE 4
155
156 #define MT7622_TEMP_AUXADC_CHANNEL 11
157 #define MT7622_NUM_SENSORS 1
158 #define MT7622_NUM_ZONES 1
159 #define MT7622_NUM_SENSORS_PER_ZONE 1
160 #define MT7622_TS1 0
161
162 struct mtk_thermal;
163
164 struct thermal_bank_cfg {
165 unsigned int num_sensors;
166 const int *sensors;
167 };
168
169 struct mtk_thermal_bank {
170 struct mtk_thermal *mt;
171 int id;
172 };
173
174 struct mtk_thermal_data {
175 s32 num_banks;
176 s32 num_sensors;
177 s32 auxadc_channel;
178 const int *sensor_mux_values;
179 const int *msr;
180 const int *adcpnp;
181 struct thermal_bank_cfg bank_data[];
182 };
183
184 struct mtk_thermal {
185 struct device *dev;
186 void __iomem *thermal_base;
187
188 struct clk *clk_peri_therm;
189 struct clk *clk_auxadc;
190 /* lock: for getting and putting banks */
191 struct mutex lock;
192
193 /* Calibration values */
194 s32 adc_ge;
195 s32 degc_cali;
196 s32 o_slope;
197 s32 vts[MT8173_NUM_SENSORS];
198
199 const struct mtk_thermal_data *conf;
200 struct mtk_thermal_bank banks[];
201 };
202
203 /* MT8173 thermal sensor data */
204 static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
205 { MT8173_TS2, MT8173_TS3 },
206 { MT8173_TS2, MT8173_TS4 },
207 { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
208 { MT8173_TS2 },
209 };
210
211 static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
212 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
213 };
214
215 static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
216 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
217 };
218
219 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
220
221 /* MT2701 thermal sensor data */
222 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
223 MT2701_TS1, MT2701_TS2, MT2701_TSABB
224 };
225
226 static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
227 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
228 };
229
230 static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
231 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
232 };
233
234 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
235
236 /* MT2712 thermal sensor data */
237 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
238 MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
239 };
240
241 static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
242 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
243 };
244
245 static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
246 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
247 };
248
249 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
250
251 /* MT7622 thermal sensor data */
252 static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
253 static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
254 static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
255 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
256
257 /**
258 * The MT8173 thermal controller has four banks. Each bank can read up to
259 * four temperature sensors simultaneously. The MT8173 has a total of 5
260 * temperature sensors. We use each bank to measure a certain area of the
261 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
262 * areas, hence is used in different banks.
263 *
264 * The thermal core only gets the maximum temperature of all banks, so
265 * the bank concept wouldn't be necessary here. However, the SVS (Smart
266 * Voltage Scaling) unit makes its decisions based on the same bank
267 * data, and this indeed needs the temperatures of the individual banks
268 * for making better decisions.
269 */
270 static const struct mtk_thermal_data mt8173_thermal_data = {
271 .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
272 .num_banks = MT8173_NUM_ZONES,
273 .num_sensors = MT8173_NUM_SENSORS,
274 .bank_data = {
275 {
276 .num_sensors = 2,
277 .sensors = mt8173_bank_data[0],
278 }, {
279 .num_sensors = 2,
280 .sensors = mt8173_bank_data[1],
281 }, {
282 .num_sensors = 3,
283 .sensors = mt8173_bank_data[2],
284 }, {
285 .num_sensors = 1,
286 .sensors = mt8173_bank_data[3],
287 },
288 },
289 .msr = mt8173_msr,
290 .adcpnp = mt8173_adcpnp,
291 .sensor_mux_values = mt8173_mux_values,
292 };
293
294 /**
295 * The MT2701 thermal controller has one bank, which can read up to
296 * three temperature sensors simultaneously. The MT2701 has a total of 3
297 * temperature sensors.
298 *
299 * The thermal core only gets the maximum temperature of this one bank,
300 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
301 * Voltage Scaling) unit makes its decisions based on the same bank
302 * data.
303 */
304 static const struct mtk_thermal_data mt2701_thermal_data = {
305 .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
306 .num_banks = 1,
307 .num_sensors = MT2701_NUM_SENSORS,
308 .bank_data = {
309 {
310 .num_sensors = 3,
311 .sensors = mt2701_bank_data,
312 },
313 },
314 .msr = mt2701_msr,
315 .adcpnp = mt2701_adcpnp,
316 .sensor_mux_values = mt2701_mux_values,
317 };
318
319 /**
320 * The MT2712 thermal controller has one bank, which can read up to
321 * four temperature sensors simultaneously. The MT2712 has a total of 4
322 * temperature sensors.
323 *
324 * The thermal core only gets the maximum temperature of this one bank,
325 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
326 * Voltage Scaling) unit makes its decisions based on the same bank
327 * data.
328 */
329 static const struct mtk_thermal_data mt2712_thermal_data = {
330 .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
331 .num_banks = 1,
332 .num_sensors = MT2712_NUM_SENSORS,
333 .bank_data = {
334 {
335 .num_sensors = 4,
336 .sensors = mt2712_bank_data,
337 },
338 },
339 .msr = mt2712_msr,
340 .adcpnp = mt2712_adcpnp,
341 .sensor_mux_values = mt2712_mux_values,
342 };
343
344 /*
345 * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
346 * access.
347 */
348 static const struct mtk_thermal_data mt7622_thermal_data = {
349 .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
350 .num_banks = MT7622_NUM_ZONES,
351 .num_sensors = MT7622_NUM_SENSORS,
352 .bank_data = {
353 {
354 .num_sensors = 1,
355 .sensors = mt7622_bank_data,
356 },
357 },
358 .msr = mt7622_msr,
359 .adcpnp = mt7622_adcpnp,
360 .sensor_mux_values = mt7622_mux_values,
361 };
362
363 /**
364 * raw_to_mcelsius - convert a raw ADC value to mcelsius
365 * @mt: The thermal controller
366 * @raw: raw ADC value
367 *
368 * This converts the raw ADC value to mcelsius using the SoC specific
369 * calibration constants
370 */
raw_to_mcelsius(struct mtk_thermal * mt,int sensno,s32 raw)371 static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
372 {
373 s32 tmp;
374
375 raw &= 0xfff;
376
377 tmp = 203450520 << 3;
378 tmp /= 165 + mt->o_slope;
379 tmp /= 10000 + mt->adc_ge;
380 tmp *= raw - mt->vts[sensno] - 3350;
381 tmp >>= 3;
382
383 return mt->degc_cali * 500 - tmp;
384 }
385
386 /**
387 * mtk_thermal_get_bank - get bank
388 * @bank: The bank
389 *
390 * The bank registers are banked, we have to select a bank in the
391 * PTPCORESEL register to access it.
392 */
mtk_thermal_get_bank(struct mtk_thermal_bank * bank)393 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
394 {
395 struct mtk_thermal *mt = bank->mt;
396 u32 val;
397
398 mutex_lock(&mt->lock);
399
400 val = readl(mt->thermal_base + PTPCORESEL);
401 val &= ~0xf;
402 val |= bank->id;
403 writel(val, mt->thermal_base + PTPCORESEL);
404 }
405
406 /**
407 * mtk_thermal_put_bank - release bank
408 * @bank: The bank
409 *
410 * release a bank previously taken with mtk_thermal_get_bank,
411 */
mtk_thermal_put_bank(struct mtk_thermal_bank * bank)412 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
413 {
414 struct mtk_thermal *mt = bank->mt;
415
416 mutex_unlock(&mt->lock);
417 }
418
419 /**
420 * mtk_thermal_bank_temperature - get the temperature of a bank
421 * @bank: The bank
422 *
423 * The temperature of a bank is considered the maximum temperature of
424 * the sensors associated to the bank.
425 */
mtk_thermal_bank_temperature(struct mtk_thermal_bank * bank)426 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
427 {
428 struct mtk_thermal *mt = bank->mt;
429 const struct mtk_thermal_data *conf = mt->conf;
430 int i, temp = INT_MIN, max = INT_MIN;
431 u32 raw;
432
433 for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
434 raw = readl(mt->thermal_base + conf->msr[i]);
435
436 temp = raw_to_mcelsius(mt,
437 conf->bank_data[bank->id].sensors[i],
438 raw);
439
440 /*
441 * The first read of a sensor often contains very high bogus
442 * temperature value. Filter these out so that the system does
443 * not immediately shut down.
444 */
445 if (temp > 200000)
446 temp = 0;
447
448 if (temp > max)
449 max = temp;
450 }
451
452 return max;
453 }
454
mtk_read_temp(void * data,int * temperature)455 static int mtk_read_temp(void *data, int *temperature)
456 {
457 struct mtk_thermal *mt = data;
458 int i;
459 int tempmax = INT_MIN;
460
461 for (i = 0; i < mt->conf->num_banks; i++) {
462 struct mtk_thermal_bank *bank = &mt->banks[i];
463
464 mtk_thermal_get_bank(bank);
465
466 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
467
468 mtk_thermal_put_bank(bank);
469 }
470
471 *temperature = tempmax;
472
473 return 0;
474 }
475
476 static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
477 .get_temp = mtk_read_temp,
478 };
479
mtk_thermal_init_bank(struct mtk_thermal * mt,int num,u32 apmixed_phys_base,u32 auxadc_phys_base)480 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
481 u32 apmixed_phys_base, u32 auxadc_phys_base)
482 {
483 struct mtk_thermal_bank *bank = &mt->banks[num];
484 const struct mtk_thermal_data *conf = mt->conf;
485 int i;
486
487 bank->id = num;
488 bank->mt = mt;
489
490 mtk_thermal_get_bank(bank);
491
492 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
493 writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);
494
495 /*
496 * filt interval is 1 * 46.540us = 46.54us,
497 * sen interval is 429 * 46.540us = 19.96ms
498 */
499 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
500 TEMP_MONCTL2_SENSOR_INTERVAL(429),
501 mt->thermal_base + TEMP_MONCTL2);
502
503 /* poll is set to 10u */
504 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
505 mt->thermal_base + TEMP_AHBPOLL);
506
507 /* temperature sampling control, 1 sample */
508 writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
509
510 /* exceed this polling time, IRQ would be inserted */
511 writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);
512
513 /* number of interrupts per event, 1 is enough */
514 writel(0x0, mt->thermal_base + TEMP_MONIDET0);
515 writel(0x0, mt->thermal_base + TEMP_MONIDET1);
516
517 /*
518 * The MT8173 thermal controller does not have its own ADC. Instead it
519 * uses AHB bus accesses to control the AUXADC. To do this the thermal
520 * controller has to be programmed with the physical addresses of the
521 * AUXADC registers and with the various bit positions in the AUXADC.
522 * Also the thermal controller controls a mux in the APMIXEDSYS register
523 * space.
524 */
525
526 /*
527 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
528 * automatically by hw
529 */
530 writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX);
531
532 /* AHB address for auxadc mux selection */
533 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
534 mt->thermal_base + TEMP_ADCMUXADDR);
535
536 /* AHB address for pnp sensor mux selection */
537 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
538 mt->thermal_base + TEMP_PNPMUXADDR);
539
540 /* AHB value for auxadc enable */
541 writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN);
542
543 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
544 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
545 mt->thermal_base + TEMP_ADCENADDR);
546
547 /* AHB address for auxadc valid bit */
548 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
549 mt->thermal_base + TEMP_ADCVALIDADDR);
550
551 /* AHB address for auxadc voltage output */
552 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
553 mt->thermal_base + TEMP_ADCVOLTADDR);
554
555 /* read valid & voltage are at the same register */
556 writel(0x0, mt->thermal_base + TEMP_RDCTRL);
557
558 /* indicate where the valid bit is */
559 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
560 mt->thermal_base + TEMP_ADCVALIDMASK);
561
562 /* no shift */
563 writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
564
565 /* enable auxadc mux write transaction */
566 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
567 mt->thermal_base + TEMP_ADCWRITECTRL);
568
569 for (i = 0; i < conf->bank_data[num].num_sensors; i++)
570 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
571 mt->thermal_base + conf->adcpnp[i]);
572
573 writel((1 << conf->bank_data[num].num_sensors) - 1,
574 mt->thermal_base + TEMP_MONCTL0);
575
576 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
577 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
578 mt->thermal_base + TEMP_ADCWRITECTRL);
579
580 mtk_thermal_put_bank(bank);
581 }
582
of_get_phys_base(struct device_node * np)583 static u64 of_get_phys_base(struct device_node *np)
584 {
585 u64 size64;
586 const __be32 *regaddr_p;
587
588 regaddr_p = of_get_address(np, 0, &size64, NULL);
589 if (!regaddr_p)
590 return OF_BAD_ADDR;
591
592 return of_translate_address(np, regaddr_p);
593 }
594
mtk_thermal_get_calibration_data(struct device * dev,struct mtk_thermal * mt)595 static int mtk_thermal_get_calibration_data(struct device *dev,
596 struct mtk_thermal *mt)
597 {
598 struct nvmem_cell *cell;
599 u32 *buf;
600 size_t len;
601 int i, ret = 0;
602
603 /* Start with default values */
604 mt->adc_ge = 512;
605 for (i = 0; i < mt->conf->num_sensors; i++)
606 mt->vts[i] = 260;
607 mt->degc_cali = 40;
608 mt->o_slope = 0;
609
610 cell = nvmem_cell_get(dev, "calibration-data");
611 if (IS_ERR(cell)) {
612 if (PTR_ERR(cell) == -EPROBE_DEFER)
613 return PTR_ERR(cell);
614 return 0;
615 }
616
617 buf = (u32 *)nvmem_cell_read(cell, &len);
618
619 nvmem_cell_put(cell);
620
621 if (IS_ERR(buf))
622 return PTR_ERR(buf);
623
624 if (len < 3 * sizeof(u32)) {
625 dev_warn(dev, "invalid calibration data\n");
626 ret = -EINVAL;
627 goto out;
628 }
629
630 if (buf[0] & MT8173_CALIB_BUF0_VALID) {
631 mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]);
632 mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]);
633 mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]);
634 mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]);
635 mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]);
636 mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]);
637 mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]);
638 if (MT8173_CALIB_BUF1_ID(buf[1]) &
639 MT8173_CALIB_BUF0_O_SLOPE_SIGN(buf[0]))
640 mt->o_slope = -MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
641 else
642 mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
643 } else {
644 dev_info(dev, "Device not calibrated, using default calibration values\n");
645 }
646
647 out:
648 kfree(buf);
649
650 return ret;
651 }
652
653 static const struct of_device_id mtk_thermal_of_match[] = {
654 {
655 .compatible = "mediatek,mt8173-thermal",
656 .data = (void *)&mt8173_thermal_data,
657 },
658 {
659 .compatible = "mediatek,mt2701-thermal",
660 .data = (void *)&mt2701_thermal_data,
661 },
662 {
663 .compatible = "mediatek,mt2712-thermal",
664 .data = (void *)&mt2712_thermal_data,
665 },
666 {
667 .compatible = "mediatek,mt7622-thermal",
668 .data = (void *)&mt7622_thermal_data,
669 }, {
670 },
671 };
672 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
673
mtk_thermal_probe(struct platform_device * pdev)674 static int mtk_thermal_probe(struct platform_device *pdev)
675 {
676 int ret, i;
677 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
678 struct mtk_thermal *mt;
679 struct resource *res;
680 u64 auxadc_phys_base, apmixed_phys_base;
681 struct thermal_zone_device *tzdev;
682
683 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
684 if (!mt)
685 return -ENOMEM;
686
687 mt->conf = of_device_get_match_data(&pdev->dev);
688
689 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
690 if (IS_ERR(mt->clk_peri_therm))
691 return PTR_ERR(mt->clk_peri_therm);
692
693 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
694 if (IS_ERR(mt->clk_auxadc))
695 return PTR_ERR(mt->clk_auxadc);
696
697 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
698 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
699 if (IS_ERR(mt->thermal_base))
700 return PTR_ERR(mt->thermal_base);
701
702 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
703 if (ret)
704 return ret;
705
706 mutex_init(&mt->lock);
707
708 mt->dev = &pdev->dev;
709
710 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
711 if (!auxadc) {
712 dev_err(&pdev->dev, "missing auxadc node\n");
713 return -ENODEV;
714 }
715
716 auxadc_phys_base = of_get_phys_base(auxadc);
717
718 of_node_put(auxadc);
719
720 if (auxadc_phys_base == OF_BAD_ADDR) {
721 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
722 return -EINVAL;
723 }
724
725 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
726 if (!apmixedsys) {
727 dev_err(&pdev->dev, "missing apmixedsys node\n");
728 return -ENODEV;
729 }
730
731 apmixed_phys_base = of_get_phys_base(apmixedsys);
732
733 of_node_put(apmixedsys);
734
735 if (apmixed_phys_base == OF_BAD_ADDR) {
736 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
737 return -EINVAL;
738 }
739
740 ret = device_reset(&pdev->dev);
741 if (ret)
742 return ret;
743
744 ret = clk_prepare_enable(mt->clk_auxadc);
745 if (ret) {
746 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
747 return ret;
748 }
749
750 ret = clk_prepare_enable(mt->clk_peri_therm);
751 if (ret) {
752 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
753 goto err_disable_clk_auxadc;
754 }
755
756 for (i = 0; i < mt->conf->num_banks; i++)
757 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
758 auxadc_phys_base);
759
760 platform_set_drvdata(pdev, mt);
761
762 tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
763 &mtk_thermal_ops);
764 if (IS_ERR(tzdev)) {
765 ret = PTR_ERR(tzdev);
766 goto err_disable_clk_peri_therm;
767 }
768
769 return 0;
770
771 err_disable_clk_peri_therm:
772 clk_disable_unprepare(mt->clk_peri_therm);
773 err_disable_clk_auxadc:
774 clk_disable_unprepare(mt->clk_auxadc);
775
776 return ret;
777 }
778
mtk_thermal_remove(struct platform_device * pdev)779 static int mtk_thermal_remove(struct platform_device *pdev)
780 {
781 struct mtk_thermal *mt = platform_get_drvdata(pdev);
782
783 clk_disable_unprepare(mt->clk_peri_therm);
784 clk_disable_unprepare(mt->clk_auxadc);
785
786 return 0;
787 }
788
789 static struct platform_driver mtk_thermal_driver = {
790 .probe = mtk_thermal_probe,
791 .remove = mtk_thermal_remove,
792 .driver = {
793 .name = "mtk-thermal",
794 .of_match_table = mtk_thermal_of_match,
795 },
796 };
797
798 module_platform_driver(mtk_thermal_driver);
799
800 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
801 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
802 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
803 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
804 MODULE_DESCRIPTION("Mediatek thermal driver");
805 MODULE_LICENSE("GPL v2");
806
