1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/delay.h>
3 #include <linux/vmalloc.h>
4 
5 #include "XGIfb.h"
6 #include "vb_def.h"
7 #include "vb_util.h"
8 #include "vb_setmode.h"
9 #include "vb_init.h"
10 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
11 	{ 16, 0x45},
12 	{  8, 0x35},
13 	{  4, 0x31},
14 	{  2, 0x21} };
15 
16 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
17 	{ 128, 0x5D},
18 	{ 64, 0x59},
19 	{ 64, 0x4D},
20 	{ 32, 0x55},
21 	{ 32, 0x49},
22 	{ 32, 0x3D},
23 	{ 16, 0x51},
24 	{ 16, 0x45},
25 	{ 16, 0x39},
26 	{  8, 0x41},
27 	{  8, 0x35},
28 	{  4, 0x31} };
29 
30 #define XGIFB_ROM_SIZE	65536
31 
32 static unsigned char
XGINew_GetXG20DRAMType(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)33 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
34 		       struct vb_device_info *pVBInfo)
35 {
36 	unsigned char data, temp;
37 
38 	if (HwDeviceExtension->jChipType < XG20) {
39 		data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
40 		if (data == 0)
41 			data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
42 				   0x02) >> 1;
43 		return data;
44 	} else if (HwDeviceExtension->jChipType == XG27) {
45 		temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
46 		/* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
47 		if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
48 			data = 0; /* DDR */
49 		else
50 			data = 1; /* DDRII */
51 		return data;
52 	} else if (HwDeviceExtension->jChipType == XG21) {
53 		/* Independent GPIO control */
54 		xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
55 		usleep_range(800, 1800);
56 		xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
57 		/* GPIOF 0:DVI 1:DVO */
58 		data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
59 		/*
60 		 * HOTPLUG_SUPPORT
61 		 * for current XG20 & XG21, GPIOH is floating, driver will
62 		 * fix DDR temporarily
63 		 */
64 		/* DVI read GPIOH */
65 		data &= 0x01; /* 1=DDRII, 0=DDR */
66 		/* ~HOTPLUG_SUPPORT */
67 		xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
68 		return data;
69 	}
70 	data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
71 
72 	if (data == 1)
73 		data++;
74 
75 	return data;
76 }
77 
XGINew_DDR1x_MRS_340(unsigned long P3c4,struct vb_device_info * pVBInfo)78 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
79 				 struct vb_device_info *pVBInfo)
80 {
81 	xgifb_reg_set(P3c4, 0x18, 0x01);
82 	xgifb_reg_set(P3c4, 0x19, 0x20);
83 	xgifb_reg_set(P3c4, 0x16, 0x00);
84 	xgifb_reg_set(P3c4, 0x16, 0x80);
85 
86 	usleep_range(3, 1003);
87 	xgifb_reg_set(P3c4, 0x18, 0x00);
88 	xgifb_reg_set(P3c4, 0x19, 0x20);
89 	xgifb_reg_set(P3c4, 0x16, 0x00);
90 	xgifb_reg_set(P3c4, 0x16, 0x80);
91 
92 	usleep_range(60, 1060);
93 	xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
94 	xgifb_reg_set(P3c4, 0x19, 0x01);
95 	xgifb_reg_set(P3c4, 0x16, 0x03);
96 	xgifb_reg_set(P3c4, 0x16, 0x83);
97 	usleep_range(1, 1001);
98 	xgifb_reg_set(P3c4, 0x1B, 0x03);
99 	usleep_range(500, 1500);
100 	xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
101 	xgifb_reg_set(P3c4, 0x19, 0x00);
102 	xgifb_reg_set(P3c4, 0x16, 0x03);
103 	xgifb_reg_set(P3c4, 0x16, 0x83);
104 	xgifb_reg_set(P3c4, 0x1B, 0x00);
105 }
106 
XGINew_SetMemoryClock(struct vb_device_info * pVBInfo)107 static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
108 {
109 	xgifb_reg_set(pVBInfo->P3c4,
110 		      0x28,
111 		      pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
112 	xgifb_reg_set(pVBInfo->P3c4,
113 		      0x29,
114 		      pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
115 	xgifb_reg_set(pVBInfo->P3c4,
116 		      0x2A,
117 		      pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
118 
119 	xgifb_reg_set(pVBInfo->P3c4,
120 		      0x2E,
121 		      XGI340_ECLKData[pVBInfo->ram_type].SR2E);
122 	xgifb_reg_set(pVBInfo->P3c4,
123 		      0x2F,
124 		      XGI340_ECLKData[pVBInfo->ram_type].SR2F);
125 	xgifb_reg_set(pVBInfo->P3c4,
126 		      0x30,
127 		      XGI340_ECLKData[pVBInfo->ram_type].SR30);
128 }
129 
XGINew_DDRII_Bootup_XG27(struct xgi_hw_device_info * HwDeviceExtension,unsigned long P3c4,struct vb_device_info * pVBInfo)130 static void XGINew_DDRII_Bootup_XG27(
131 			struct xgi_hw_device_info *HwDeviceExtension,
132 			unsigned long P3c4, struct vb_device_info *pVBInfo)
133 {
134 	unsigned long P3d4 = P3c4 + 0x10;
135 
136 	pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
137 	XGINew_SetMemoryClock(pVBInfo);
138 
139 	/* Set Double Frequency */
140 	xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
141 
142 	usleep_range(200, 1200);
143 
144 	xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
145 	xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
146 	xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
147 	usleep_range(15, 1015);
148 	xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
149 	usleep_range(15, 1015);
150 
151 	xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
152 	xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
153 	xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
154 	usleep_range(15, 1015);
155 	xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
156 	usleep_range(15, 1015);
157 
158 	xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
159 	xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
160 	xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
161 	usleep_range(30, 1030);
162 	xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
163 	usleep_range(15, 1015);
164 
165 	xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
166 	xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
167 	xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
168 	usleep_range(30, 1030);
169 	xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
170 	xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
171 
172 	xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
173 	usleep_range(60, 1060);
174 	xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
175 
176 	xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
177 	xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
178 	xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
179 
180 	usleep_range(30, 1030);
181 	xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
182 	usleep_range(15, 1015);
183 
184 	xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
185 	xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
186 	xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
187 	usleep_range(30, 1030);
188 	xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
189 	usleep_range(15, 1015);
190 
191 	xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
192 	xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
193 	xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
194 	usleep_range(30, 1030);
195 	xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
196 	usleep_range(15, 1015);
197 
198 	/* Set SR1B refresh control 000:close; 010:open */
199 	xgifb_reg_set(P3c4, 0x1B, 0x04);
200 	usleep_range(200, 1200);
201 }
202 
XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info * HwDeviceExtension,unsigned long P3c4,struct vb_device_info * pVBInfo)203 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
204 				 unsigned long P3c4,
205 				 struct vb_device_info *pVBInfo)
206 {
207 	unsigned long P3d4 = P3c4 + 0x10;
208 
209 	pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
210 	XGINew_SetMemoryClock(pVBInfo);
211 
212 	xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
213 
214 	usleep_range(200, 1200);
215 	xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
216 	xgifb_reg_set(P3c4, 0x19, 0x80);
217 	xgifb_reg_set(P3c4, 0x16, 0x05);
218 	xgifb_reg_set(P3c4, 0x16, 0x85);
219 
220 	xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
221 	xgifb_reg_set(P3c4, 0x19, 0xC0);
222 	xgifb_reg_set(P3c4, 0x16, 0x05);
223 	xgifb_reg_set(P3c4, 0x16, 0x85);
224 
225 	xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
226 	xgifb_reg_set(P3c4, 0x19, 0x40);
227 	xgifb_reg_set(P3c4, 0x16, 0x05);
228 	xgifb_reg_set(P3c4, 0x16, 0x85);
229 
230 	xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
231 	xgifb_reg_set(P3c4, 0x19, 0x02);
232 	xgifb_reg_set(P3c4, 0x16, 0x05);
233 	xgifb_reg_set(P3c4, 0x16, 0x85);
234 
235 	usleep_range(15, 1015);
236 	xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
237 	usleep_range(30, 1030);
238 	xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
239 	usleep_range(100, 1100);
240 
241 	xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
242 	xgifb_reg_set(P3c4, 0x19, 0x00);
243 	xgifb_reg_set(P3c4, 0x16, 0x05);
244 	xgifb_reg_set(P3c4, 0x16, 0x85);
245 
246 	usleep_range(200, 1200);
247 }
248 
XGINew_DDR1x_MRS_XG20(unsigned long P3c4,struct vb_device_info * pVBInfo)249 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
250 				  struct vb_device_info *pVBInfo)
251 {
252 	xgifb_reg_set(P3c4, 0x18, 0x01);
253 	xgifb_reg_set(P3c4, 0x19, 0x40);
254 	xgifb_reg_set(P3c4, 0x16, 0x00);
255 	xgifb_reg_set(P3c4, 0x16, 0x80);
256 	usleep_range(60, 1060);
257 
258 	xgifb_reg_set(P3c4, 0x18, 0x00);
259 	xgifb_reg_set(P3c4, 0x19, 0x40);
260 	xgifb_reg_set(P3c4, 0x16, 0x00);
261 	xgifb_reg_set(P3c4, 0x16, 0x80);
262 	usleep_range(60, 1060);
263 	xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
264 	xgifb_reg_set(P3c4, 0x19, 0x01);
265 	xgifb_reg_set(P3c4, 0x16, 0x03);
266 	xgifb_reg_set(P3c4, 0x16, 0x83);
267 	usleep_range(1, 1001);
268 	xgifb_reg_set(P3c4, 0x1B, 0x03);
269 	usleep_range(500, 1500);
270 	xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
271 	xgifb_reg_set(P3c4, 0x19, 0x00);
272 	xgifb_reg_set(P3c4, 0x16, 0x03);
273 	xgifb_reg_set(P3c4, 0x16, 0x83);
274 	xgifb_reg_set(P3c4, 0x1B, 0x00);
275 }
276 
XGINew_DDR1x_DefaultRegister(struct xgi_hw_device_info * HwDeviceExtension,unsigned long Port,struct vb_device_info * pVBInfo)277 static void XGINew_DDR1x_DefaultRegister(
278 		struct xgi_hw_device_info *HwDeviceExtension,
279 		unsigned long Port, struct vb_device_info *pVBInfo)
280 {
281 	unsigned long P3d4 = Port, P3c4 = Port - 0x10;
282 
283 	if (HwDeviceExtension->jChipType >= XG20) {
284 		XGINew_SetMemoryClock(pVBInfo);
285 		xgifb_reg_set(P3d4,
286 			      0x82,
287 			      pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
288 		xgifb_reg_set(P3d4,
289 			      0x85,
290 			      pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
291 		xgifb_reg_set(P3d4,
292 			      0x86,
293 			      pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
294 
295 		xgifb_reg_set(P3d4, 0x98, 0x01);
296 		xgifb_reg_set(P3d4, 0x9A, 0x02);
297 
298 		XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
299 	} else {
300 		XGINew_SetMemoryClock(pVBInfo);
301 
302 		switch (HwDeviceExtension->jChipType) {
303 		case XG42:
304 			/* CR82 */
305 			xgifb_reg_set(P3d4,
306 				      0x82,
307 				      pVBInfo->CR40[11][pVBInfo->ram_type]);
308 			/* CR85 */
309 			xgifb_reg_set(P3d4,
310 				      0x85,
311 				      pVBInfo->CR40[12][pVBInfo->ram_type]);
312 			/* CR86 */
313 			xgifb_reg_set(P3d4,
314 				      0x86,
315 				      pVBInfo->CR40[13][pVBInfo->ram_type]);
316 			break;
317 		default:
318 			xgifb_reg_set(P3d4, 0x82, 0x88);
319 			xgifb_reg_set(P3d4, 0x86, 0x00);
320 			/* Insert read command for delay */
321 			xgifb_reg_get(P3d4, 0x86);
322 			xgifb_reg_set(P3d4, 0x86, 0x88);
323 			xgifb_reg_get(P3d4, 0x86);
324 			xgifb_reg_set(P3d4,
325 				      0x86,
326 				      pVBInfo->CR40[13][pVBInfo->ram_type]);
327 			xgifb_reg_set(P3d4, 0x82, 0x77);
328 			xgifb_reg_set(P3d4, 0x85, 0x00);
329 
330 			/* Insert read command for delay */
331 			xgifb_reg_get(P3d4, 0x85);
332 			xgifb_reg_set(P3d4, 0x85, 0x88);
333 
334 			/* Insert read command for delay */
335 			xgifb_reg_get(P3d4, 0x85);
336 			/* CR85 */
337 			xgifb_reg_set(P3d4,
338 				      0x85,
339 				      pVBInfo->CR40[12][pVBInfo->ram_type]);
340 			/* CR82 */
341 			xgifb_reg_set(P3d4,
342 				      0x82,
343 				      pVBInfo->CR40[11][pVBInfo->ram_type]);
344 			break;
345 		}
346 
347 		xgifb_reg_set(P3d4, 0x97, 0x00);
348 		xgifb_reg_set(P3d4, 0x98, 0x01);
349 		xgifb_reg_set(P3d4, 0x9A, 0x02);
350 		XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
351 	}
352 }
353 
XGINew_DDR2_DefaultRegister(struct xgi_hw_device_info * HwDeviceExtension,unsigned long Port,struct vb_device_info * pVBInfo)354 static void XGINew_DDR2_DefaultRegister(
355 		struct xgi_hw_device_info *HwDeviceExtension,
356 		unsigned long Port, struct vb_device_info *pVBInfo)
357 {
358 	unsigned long P3d4 = Port, P3c4 = Port - 0x10;
359 	/*
360 	 * keep following setting sequence, each setting in
361 	 * the same reg insert idle
362 	 */
363 	xgifb_reg_set(P3d4, 0x82, 0x77);
364 	xgifb_reg_set(P3d4, 0x86, 0x00);
365 	xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
366 	xgifb_reg_set(P3d4, 0x86, 0x88);
367 	xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
368 	/* CR86 */
369 	xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
370 	xgifb_reg_set(P3d4, 0x82, 0x77);
371 	xgifb_reg_set(P3d4, 0x85, 0x00);
372 	xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
373 	xgifb_reg_set(P3d4, 0x85, 0x88);
374 	xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
375 	xgifb_reg_set(P3d4,
376 		      0x85,
377 		      pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
378 	if (HwDeviceExtension->jChipType == XG27)
379 		/* CR82 */
380 		xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
381 	else
382 		xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
383 
384 	xgifb_reg_set(P3d4, 0x98, 0x01);
385 	xgifb_reg_set(P3d4, 0x9A, 0x02);
386 	if (HwDeviceExtension->jChipType == XG27)
387 		XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
388 	else
389 		XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
390 }
391 
XGI_SetDRAM_Helper(unsigned long P3d4,u8 seed,u8 temp2,u8 reg,u8 shift_factor,u8 mask1,u8 mask2)392 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
393 			       u8 shift_factor, u8 mask1, u8 mask2)
394 {
395 	u8 j;
396 
397 	for (j = 0; j < 4; j++) {
398 		temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
399 		xgifb_reg_set(P3d4, reg, temp2);
400 		xgifb_reg_get(P3d4, reg);
401 		temp2 &= mask1;
402 		temp2 += mask2;
403 	}
404 }
405 
XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info * HwDeviceExtension,unsigned long Port,struct vb_device_info * pVBInfo)406 static void XGINew_SetDRAMDefaultRegister340(
407 		struct xgi_hw_device_info *HwDeviceExtension,
408 		unsigned long Port, struct vb_device_info *pVBInfo)
409 {
410 	unsigned char temp, temp1, temp2, temp3, j, k;
411 
412 	unsigned long P3d4 = Port, P3c4 = Port - 0x10;
413 
414 	xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
415 	xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
416 	xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
417 	xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
418 
419 	/* CR6B DQS fine tune delay */
420 	temp = 0xaa;
421 	XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
422 
423 	/* CR6E DQM fine tune delay */
424 	XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
425 
426 	temp3 = 0;
427 	for (k = 0; k < 4; k++) {
428 		/* CR6E_D[1:0] select channel */
429 		xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
430 		XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
431 		temp3 += 0x01;
432 	}
433 
434 	xgifb_reg_set(P3d4,
435 		      0x80,
436 		      pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
437 	xgifb_reg_set(P3d4,
438 		      0x81,
439 		      pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
440 
441 	temp2 = 0x80;
442 	/* CR89 terminator type select */
443 	XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
444 
445 	temp = 0;
446 	temp1 = temp & 0x03;
447 	temp2 |= temp1;
448 	xgifb_reg_set(P3d4, 0x89, temp2);
449 
450 	temp = pVBInfo->CR40[3][pVBInfo->ram_type];
451 	temp1 = temp & 0x0F;
452 	temp2 = (temp >> 4) & 0x07;
453 	temp3 = temp & 0x80;
454 	xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
455 	xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
456 	xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
457 	xgifb_reg_set(P3d4,
458 		      0x41,
459 		      pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
460 
461 	if (HwDeviceExtension->jChipType == XG27)
462 		xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
463 
464 	for (j = 0; j <= 6; j++) /* CR90 - CR96 */
465 		xgifb_reg_set(P3d4, (0x90 + j),
466 			      pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
467 
468 	for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
469 		xgifb_reg_set(P3d4, (0xC3 + j),
470 			      pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
471 
472 	for (j = 0; j < 2; j++) /* CR8A - CR8B */
473 		xgifb_reg_set(P3d4, (0x8A + j),
474 			      pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
475 
476 	if (HwDeviceExtension->jChipType == XG42)
477 		xgifb_reg_set(P3d4, 0x8C, 0x87);
478 
479 	xgifb_reg_set(P3d4,
480 		      0x59,
481 		      pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
482 
483 	xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
484 	xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
485 	xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
486 	if (pVBInfo->ram_type) {
487 		xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
488 		if (HwDeviceExtension->jChipType == XG27)
489 			xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
490 
491 	} else {
492 		xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
493 	}
494 	xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
495 
496 	temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
497 	if (temp == 0) {
498 		XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
499 	} else {
500 		xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
501 		XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
502 	}
503 	xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
504 }
505 
XGINew_SetDRAMSize20Reg(unsigned short dram_size,struct vb_device_info * pVBInfo)506 static unsigned short XGINew_SetDRAMSize20Reg(
507 		unsigned short dram_size,
508 		struct vb_device_info *pVBInfo)
509 {
510 	unsigned short data = 0, memsize = 0;
511 	int RankSize;
512 	unsigned char ChannelNo;
513 
514 	RankSize = dram_size * pVBInfo->ram_bus / 8;
515 	data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
516 	data &= 0x80;
517 
518 	if (data == 0x80)
519 		RankSize *= 2;
520 
521 	data = 0;
522 
523 	if (pVBInfo->ram_channel == 3)
524 		ChannelNo = 4;
525 	else
526 		ChannelNo = pVBInfo->ram_channel;
527 
528 	if (ChannelNo * RankSize <= 256) {
529 		while ((RankSize >>= 1) > 0)
530 			data += 0x10;
531 
532 		memsize = data >> 4;
533 
534 		/* Fix DRAM Sizing Error */
535 		xgifb_reg_set(pVBInfo->P3c4,
536 			      0x14,
537 			      (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
538 				(data & 0xF0));
539 		usleep_range(15, 1015);
540 	}
541 	return memsize;
542 }
543 
XGINew_ReadWriteRest(unsigned short StopAddr,unsigned short StartAddr,struct vb_device_info * pVBInfo)544 static int XGINew_ReadWriteRest(unsigned short StopAddr,
545 				unsigned short StartAddr,
546 				struct vb_device_info *pVBInfo)
547 {
548 	int i;
549 	unsigned long Position = 0;
550 	void __iomem *fbaddr = pVBInfo->FBAddr;
551 
552 	writel(Position, fbaddr + Position);
553 
554 	for (i = StartAddr; i <= StopAddr; i++) {
555 		Position = 1 << i;
556 		writel(Position, fbaddr + Position);
557 	}
558 
559 	/* Fix #1759 Memory Size error in Multi-Adapter. */
560 	usleep_range(500, 1500);
561 
562 	Position = 0;
563 
564 	if (readl(fbaddr + Position) != Position)
565 		return 0;
566 
567 	for (i = StartAddr; i <= StopAddr; i++) {
568 		Position = 1 << i;
569 		if (readl(fbaddr + Position) != Position)
570 			return 0;
571 	}
572 	return 1;
573 }
574 
XGINew_CheckFrequence(struct vb_device_info * pVBInfo)575 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
576 {
577 	unsigned char data;
578 
579 	data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
580 
581 	if ((data & 0x10) == 0) {
582 		data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
583 		return (data & 0x02) >> 1;
584 	}
585 	return data & 0x01;
586 }
587 
XGINew_CheckChannel(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)588 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
589 				struct vb_device_info *pVBInfo)
590 {
591 	unsigned char data;
592 
593 	switch (HwDeviceExtension->jChipType) {
594 	case XG20:
595 	case XG21:
596 		data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
597 		data = data & 0x01;
598 		pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
599 
600 		if (data == 0) { /* Single_32_16 */
601 
602 			if ((HwDeviceExtension->ulVideoMemorySize - 1)
603 					> 0x1000000) {
604 				pVBInfo->ram_bus = 32; /* 32 bits */
605 				/* 22bit + 2 rank + 32bit */
606 				xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
607 				xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
608 				usleep_range(15, 1015);
609 
610 				if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
611 					return;
612 
613 				if ((HwDeviceExtension->ulVideoMemorySize - 1) >
614 				    0x800000) {
615 					/* 22bit + 1 rank + 32bit */
616 					xgifb_reg_set(pVBInfo->P3c4,
617 						      0x13,
618 						      0x31);
619 					xgifb_reg_set(pVBInfo->P3c4,
620 						      0x14,
621 						      0x42);
622 					usleep_range(15, 1015);
623 
624 					if (XGINew_ReadWriteRest(23,
625 								 23,
626 								 pVBInfo) == 1)
627 						return;
628 				}
629 			}
630 
631 			if ((HwDeviceExtension->ulVideoMemorySize - 1) >
632 			    0x800000) {
633 				pVBInfo->ram_bus = 16; /* 16 bits */
634 				/* 22bit + 2 rank + 16bit */
635 				xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
636 				xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
637 				usleep_range(15, 1015);
638 
639 				if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
640 					return;
641 				xgifb_reg_set(pVBInfo->P3c4,
642 					      0x13,
643 					      0x31);
644 				usleep_range(15, 1015);
645 			}
646 
647 		} else { /* Dual_16_8 */
648 			if ((HwDeviceExtension->ulVideoMemorySize - 1) >
649 			    0x800000) {
650 				pVBInfo->ram_bus = 16; /* 16 bits */
651 				/* (0x31:12x8x2) 22bit + 2 rank */
652 				xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
653 				/* 0x41:16Mx16 bit */
654 				xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
655 				usleep_range(15, 1015);
656 
657 				if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
658 					return;
659 
660 				if ((HwDeviceExtension->ulVideoMemorySize - 1) >
661 				    0x400000) {
662 					/* (0x31:12x8x2) 22bit + 1 rank */
663 					xgifb_reg_set(pVBInfo->P3c4,
664 						      0x13,
665 						      0x31);
666 					/* 0x31:8Mx16 bit */
667 					xgifb_reg_set(pVBInfo->P3c4,
668 						      0x14,
669 						      0x31);
670 					usleep_range(15, 1015);
671 
672 					if (XGINew_ReadWriteRest(22,
673 								 22,
674 								 pVBInfo) == 1)
675 						return;
676 				}
677 			}
678 
679 			if ((HwDeviceExtension->ulVideoMemorySize - 1) >
680 			    0x400000) {
681 				pVBInfo->ram_bus = 8; /* 8 bits */
682 				/* (0x31:12x8x2) 22bit + 2 rank */
683 				xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
684 				/* 0x30:8Mx8 bit */
685 				xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
686 				usleep_range(15, 1015);
687 
688 				if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
689 					return;
690 
691 				/* (0x31:12x8x2) 22bit + 1 rank */
692 				xgifb_reg_set(pVBInfo->P3c4,
693 					      0x13,
694 					      0x31);
695 				usleep_range(15, 1015);
696 			}
697 		}
698 		break;
699 
700 	case XG27:
701 		pVBInfo->ram_bus = 16; /* 16 bits */
702 		pVBInfo->ram_channel = 1; /* Single channel */
703 		xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit */
704 		break;
705 	case XG42:
706 		/*
707 		 * XG42 SR14 D[3] Reserve
708 		 * D[2] = 1, Dual Channel
709 		 * = 0, Single Channel
710 		 *
711 		 * It's Different from Other XG40 Series.
712 		 */
713 		if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
714 			pVBInfo->ram_bus = 32; /* 32 bits */
715 			pVBInfo->ram_channel = 2; /* 2 Channel */
716 			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
717 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
718 
719 			if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
720 				return;
721 
722 			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
723 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
724 			if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
725 				return;
726 
727 			pVBInfo->ram_channel = 1; /* Single Channel */
728 			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
729 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
730 
731 			if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
732 				return;
733 			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
734 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
735 		} else { /* DDR */
736 			pVBInfo->ram_bus = 64; /* 64 bits */
737 			pVBInfo->ram_channel = 1; /* 1 channels */
738 			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
739 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
740 
741 			if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
742 				return;
743 			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
744 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
745 		}
746 
747 		break;
748 
749 	default: /* XG40 */
750 
751 		if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
752 			pVBInfo->ram_bus = 32; /* 32 bits */
753 			pVBInfo->ram_channel = 3;
754 			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
755 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
756 
757 			if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
758 				return;
759 
760 			pVBInfo->ram_channel = 2; /* 2 channels */
761 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
762 
763 			if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
764 				return;
765 
766 			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
767 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
768 
769 			if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
770 				pVBInfo->ram_channel = 3; /* 4 channels */
771 			} else {
772 				pVBInfo->ram_channel = 2; /* 2 channels */
773 				xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
774 			}
775 		} else { /* DDR */
776 			pVBInfo->ram_bus = 64; /* 64 bits */
777 			pVBInfo->ram_channel = 2; /* 2 channels */
778 			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
779 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
780 
781 			if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
782 				return;
783 			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
784 			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
785 		}
786 		break;
787 	}
788 }
789 
XGINew_DDRSizing340(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)790 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
791 			       struct vb_device_info *pVBInfo)
792 {
793 	u8 i, size;
794 	unsigned short memsize, start_addr;
795 	const unsigned short (*dram_table)[2];
796 
797 	xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
798 	xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
799 	XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
800 
801 	if (HwDeviceExtension->jChipType >= XG20) {
802 		dram_table = XGINew_DDRDRAM_TYPE20;
803 		size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
804 		start_addr = 5;
805 	} else {
806 		dram_table = XGINew_DDRDRAM_TYPE340;
807 		size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
808 		start_addr = 9;
809 	}
810 
811 	for (i = 0; i < size; i++) {
812 		/* SetDRAMSizingType */
813 		xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
814 		usleep_range(50, 1050); /* should delay 50 ns */
815 
816 		memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
817 
818 		if (memsize == 0)
819 			continue;
820 
821 		memsize += (pVBInfo->ram_channel - 2) + 20;
822 		if ((HwDeviceExtension->ulVideoMemorySize - 1) <
823 			(unsigned long)(1 << memsize))
824 			continue;
825 
826 		if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
827 			return 1;
828 	}
829 	return 0;
830 }
831 
XGINew_SetDRAMSize_340(struct xgifb_video_info * xgifb_info,struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)832 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
833 				   struct xgi_hw_device_info *HwDeviceExtension,
834 				   struct vb_device_info *pVBInfo)
835 {
836 	unsigned short data;
837 
838 	pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
839 
840 	XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
841 
842 	data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
843 	/* disable read cache */
844 	xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF));
845 	XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
846 
847 	XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
848 	data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
849 	/* enable read cache */
850 	xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20));
851 }
852 
xgifb_copy_rom(struct pci_dev * dev,size_t * rom_size)853 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
854 {
855 	void __iomem *rom_address;
856 	u8 *rom_copy;
857 
858 	rom_address = pci_map_rom(dev, rom_size);
859 	if (!rom_address)
860 		return NULL;
861 
862 	rom_copy = vzalloc(XGIFB_ROM_SIZE);
863 	if (!rom_copy)
864 		goto done;
865 
866 	*rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
867 	memcpy_fromio(rom_copy, rom_address, *rom_size);
868 
869 done:
870 	pci_unmap_rom(dev, rom_address);
871 	return rom_copy;
872 }
873 
xgifb_read_vbios(struct pci_dev * pdev)874 static bool xgifb_read_vbios(struct pci_dev *pdev)
875 {
876 	struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
877 	u8 *vbios;
878 	unsigned long i;
879 	unsigned char j;
880 	struct XGI21_LVDSCapStruct *lvds;
881 	size_t vbios_size;
882 	int entry;
883 
884 	vbios = xgifb_copy_rom(pdev, &vbios_size);
885 	if (!vbios) {
886 		dev_err(&pdev->dev, "Video BIOS not available\n");
887 		return false;
888 	}
889 	if (vbios_size <= 0x65)
890 		goto error;
891 	/*
892 	 * The user can ignore the LVDS bit in the BIOS and force the display
893 	 * type.
894 	 */
895 	if (!(vbios[0x65] & 0x1) &&
896 	    (!xgifb_info->display2_force ||
897 	     xgifb_info->display2 != XGIFB_DISP_LCD)) {
898 		vfree(vbios);
899 		return false;
900 	}
901 	if (vbios_size <= 0x317)
902 		goto error;
903 	i = vbios[0x316] | (vbios[0x317] << 8);
904 	if (vbios_size <= i - 1)
905 		goto error;
906 	j = vbios[i - 1];
907 	if (j == 0)
908 		goto error;
909 	if (j == 0xff)
910 		j = 1;
911 
912 	/* Read the LVDS table index scratch register set by the BIOS. */
913 
914 	entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
915 	if (entry >= j)
916 		entry = 0;
917 	i += entry * 25;
918 	lvds = &xgifb_info->lvds_data;
919 	if (vbios_size <= i + 24)
920 		goto error;
921 	lvds->LVDS_Capability	= vbios[i]	| (vbios[i + 1] << 8);
922 	lvds->LVDSHT		= vbios[i + 2]	| (vbios[i + 3] << 8);
923 	lvds->LVDSVT		= vbios[i + 4]	| (vbios[i + 5] << 8);
924 	lvds->LVDSHDE		= vbios[i + 6]	| (vbios[i + 7] << 8);
925 	lvds->LVDSVDE		= vbios[i + 8]	| (vbios[i + 9] << 8);
926 	lvds->LVDSHFP		= vbios[i + 10]	| (vbios[i + 11] << 8);
927 	lvds->LVDSVFP		= vbios[i + 12]	| (vbios[i + 13] << 8);
928 	lvds->LVDSHSYNC		= vbios[i + 14]	| (vbios[i + 15] << 8);
929 	lvds->LVDSVSYNC		= vbios[i + 16]	| (vbios[i + 17] << 8);
930 	lvds->VCLKData1		= vbios[i + 18];
931 	lvds->VCLKData2		= vbios[i + 19];
932 	lvds->PSC_S1		= vbios[i + 20];
933 	lvds->PSC_S2		= vbios[i + 21];
934 	lvds->PSC_S3		= vbios[i + 22];
935 	lvds->PSC_S4		= vbios[i + 23];
936 	lvds->PSC_S5		= vbios[i + 24];
937 	vfree(vbios);
938 	return true;
939 error:
940 	dev_err(&pdev->dev, "Video BIOS corrupted\n");
941 	vfree(vbios);
942 	return false;
943 }
944 
XGINew_ChkSenseStatus(struct vb_device_info * pVBInfo)945 static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
946 {
947 	unsigned short tempbx = 0, temp, tempcx, CR3CData;
948 
949 	temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
950 
951 	if (temp & Monitor1Sense)
952 		tempbx |= ActiveCRT1;
953 	if (temp & LCDSense)
954 		tempbx |= ActiveLCD;
955 	if (temp & Monitor2Sense)
956 		tempbx |= ActiveCRT2;
957 	if (temp & TVSense) {
958 		tempbx |= ActiveTV;
959 		if (temp & AVIDEOSense)
960 			tempbx |= (ActiveAVideo << 8);
961 		if (temp & SVIDEOSense)
962 			tempbx |= (ActiveSVideo << 8);
963 		if (temp & SCARTSense)
964 			tempbx |= (ActiveSCART << 8);
965 		if (temp & HiTVSense)
966 			tempbx |= (ActiveHiTV << 8);
967 		if (temp & YPbPrSense)
968 			tempbx |= (ActiveYPbPr << 8);
969 	}
970 
971 	tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
972 	tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
973 
974 	if (tempbx & tempcx) {
975 		CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
976 		if (!(CR3CData & DisplayDeviceFromCMOS))
977 			tempcx = 0x1FF0;
978 	} else {
979 		tempcx = 0x1FF0;
980 	}
981 
982 	tempbx &= tempcx;
983 	xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
984 	xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
985 }
986 
XGINew_SetModeScratch(struct vb_device_info * pVBInfo)987 static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
988 {
989 	unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
990 
991 	temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
992 	temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
993 	temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
994 
995 	if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
996 		if (temp & ActiveCRT2)
997 			tempcl = SetCRT2ToRAMDAC;
998 	}
999 
1000 	if (temp & ActiveLCD) {
1001 		tempcl |= SetCRT2ToLCD;
1002 		if (temp & DriverMode) {
1003 			if (temp & ActiveTV) {
1004 				tempch = SetToLCDA | EnableDualEdge;
1005 				temp ^= SetCRT2ToLCD;
1006 
1007 				if ((temp >> 8) & ActiveAVideo)
1008 					tempcl |= SetCRT2ToAVIDEO;
1009 				if ((temp >> 8) & ActiveSVideo)
1010 					tempcl |= SetCRT2ToSVIDEO;
1011 				if ((temp >> 8) & ActiveSCART)
1012 					tempcl |= SetCRT2ToSCART;
1013 
1014 				if (pVBInfo->IF_DEF_HiVision == 1) {
1015 					if ((temp >> 8) & ActiveHiTV)
1016 						tempcl |= SetCRT2ToHiVision;
1017 				}
1018 
1019 				if (pVBInfo->IF_DEF_YPbPr == 1) {
1020 					if ((temp >> 8) & ActiveYPbPr)
1021 						tempch |= SetYPbPr;
1022 				}
1023 			}
1024 		}
1025 	} else {
1026 		if ((temp >> 8) & ActiveAVideo)
1027 			tempcl |= SetCRT2ToAVIDEO;
1028 		if ((temp >> 8) & ActiveSVideo)
1029 			tempcl |= SetCRT2ToSVIDEO;
1030 		if ((temp >> 8) & ActiveSCART)
1031 			tempcl |= SetCRT2ToSCART;
1032 
1033 		if (pVBInfo->IF_DEF_HiVision == 1) {
1034 			if ((temp >> 8) & ActiveHiTV)
1035 				tempcl |= SetCRT2ToHiVision;
1036 		}
1037 
1038 		if (pVBInfo->IF_DEF_YPbPr == 1) {
1039 			if ((temp >> 8) & ActiveYPbPr)
1040 				tempch |= SetYPbPr;
1041 		}
1042 	}
1043 
1044 	tempcl |= SetSimuScanMode;
1045 	if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) ||
1046 				       (temp & ActiveTV) ||
1047 				       (temp & ActiveCRT2)))
1048 		tempcl ^= (SetSimuScanMode | SwitchCRT2);
1049 	if ((temp & ActiveLCD) && (temp & ActiveTV))
1050 		tempcl ^= (SetSimuScanMode | SwitchCRT2);
1051 	xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1052 
1053 	CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1054 	CR31Data &= ~(SetNotSimuMode >> 8);
1055 	if (!(temp & ActiveCRT1))
1056 		CR31Data |= (SetNotSimuMode >> 8);
1057 	CR31Data &= ~(DisableCRT2Display >> 8);
1058 	if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1059 		CR31Data |= (DisableCRT2Display >> 8);
1060 	xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1061 
1062 	CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1063 	CR38Data &= ~SetYPbPr;
1064 	CR38Data |= tempch;
1065 	xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1066 }
1067 
XGINew_SenseLCD(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)1068 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1069 							*HwDeviceExtension,
1070 				      struct vb_device_info *pVBInfo)
1071 {
1072 	unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1073 
1074 	switch (HwDeviceExtension->ulCRT2LCDType) {
1075 	case LCD_640x480:
1076 	case LCD_1024x600:
1077 	case LCD_1152x864:
1078 	case LCD_1280x960:
1079 	case LCD_1152x768:
1080 	case LCD_1920x1440:
1081 	case LCD_2048x1536:
1082 		temp = 0; /* overwrite used ulCRT2LCDType */
1083 		break;
1084 	case LCD_UNKNOWN: /* unknown lcd, do nothing */
1085 		return 0;
1086 	}
1087 	xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1088 	return 1;
1089 }
1090 
XGINew_GetXG21Sense(struct pci_dev * pdev,struct vb_device_info * pVBInfo)1091 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1092 				struct vb_device_info *pVBInfo)
1093 {
1094 	struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1095 	unsigned char Temp;
1096 
1097 	if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
1098 		xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1099 		/* LVDS on chip */
1100 		xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1101 	} else {
1102 		/* Enable GPIOA/B read */
1103 		xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1104 		Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1105 		if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1106 			XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1107 			xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1108 			/* Enable read GPIOF */
1109 			xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1110 			if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1111 				Temp = 0xA0; /* Only DVO on chip */
1112 			else
1113 				Temp = 0x80; /* TMDS on chip */
1114 			xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
1115 			/* Disable read GPIOF */
1116 			xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1117 		}
1118 	}
1119 }
1120 
XGINew_GetXG27Sense(struct vb_device_info * pVBInfo)1121 static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
1122 {
1123 	unsigned char Temp, bCR4A;
1124 
1125 	bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1126 	/* Enable GPIOA/B/C read */
1127 	xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1128 	Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1129 	xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1130 
1131 	if (Temp <= 0x02) {
1132 		/* LVDS setting */
1133 		xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1134 		xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1135 	} else {
1136 		/* TMDS/DVO setting */
1137 		xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1138 	}
1139 	xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1140 }
1141 
GetXG21FPBits(struct vb_device_info * pVBInfo)1142 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1143 {
1144 	unsigned char CR38, CR4A, temp;
1145 
1146 	CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1147 	/* enable GPIOE read */
1148 	xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1149 	CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1150 	temp = 0;
1151 	if ((CR38 & 0xE0) > 0x80) {
1152 		temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1153 		temp &= 0x08;
1154 		temp >>= 3;
1155 	}
1156 
1157 	xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1158 
1159 	return temp;
1160 }
1161 
GetXG27FPBits(struct vb_device_info * pVBInfo)1162 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1163 {
1164 	unsigned char CR4A, temp;
1165 
1166 	CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1167 	/* enable GPIOA/B/C read */
1168 	xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1169 	temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1170 	if (temp > 2)
1171 		temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1172 
1173 	xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1174 
1175 	return temp;
1176 }
1177 
xgifb_bridge_is_on(struct vb_device_info * vb_info)1178 static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1179 {
1180 	u8 flag;
1181 
1182 	flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1183 	return flag == 1 || flag == 2;
1184 }
1185 
XGIInitNew(struct pci_dev * pdev)1186 unsigned char XGIInitNew(struct pci_dev *pdev)
1187 {
1188 	struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1189 	struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1190 	struct vb_device_info VBINF;
1191 	struct vb_device_info *pVBInfo = &VBINF;
1192 	unsigned char i, temp = 0, temp1;
1193 
1194 	pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1195 
1196 	if (!pVBInfo->FBAddr) {
1197 		dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1198 		return 0;
1199 	}
1200 
1201 	XGIRegInit(pVBInfo, xgifb_info->vga_base);
1202 
1203 	outb(0x67, pVBInfo->P3c2);
1204 
1205 	InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1206 
1207 	/* Openkey */
1208 	xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1209 
1210 	/* GetXG21Sense (GPIO) */
1211 	if (HwDeviceExtension->jChipType == XG21)
1212 		XGINew_GetXG21Sense(pdev, pVBInfo);
1213 
1214 	if (HwDeviceExtension->jChipType == XG27)
1215 		XGINew_GetXG27Sense(pVBInfo);
1216 
1217 	/* Reset Extended register */
1218 
1219 	for (i = 0x06; i < 0x20; i++)
1220 		xgifb_reg_set(pVBInfo->P3c4, i, 0);
1221 
1222 	for (i = 0x21; i <= 0x27; i++)
1223 		xgifb_reg_set(pVBInfo->P3c4, i, 0);
1224 
1225 	for (i = 0x31; i <= 0x3B; i++)
1226 		xgifb_reg_set(pVBInfo->P3c4, i, 0);
1227 
1228 	/* Auto over driver for XG42 */
1229 	if (HwDeviceExtension->jChipType == XG42)
1230 		xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1231 
1232 	for (i = 0x79; i <= 0x7C; i++)
1233 		xgifb_reg_set(pVBInfo->P3d4, i, 0);
1234 
1235 	if (HwDeviceExtension->jChipType >= XG20)
1236 		xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1237 
1238 	/* SetDefExt1Regs begin */
1239 	xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1240 	if (HwDeviceExtension->jChipType == XG27) {
1241 		xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1242 		xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1243 	}
1244 	xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1245 	xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1246 	/* Frame buffer can read/write SR20 */
1247 	xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1248 	/* H/W request for slow corner chip */
1249 	xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1250 	if (HwDeviceExtension->jChipType == XG27)
1251 		xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1252 
1253 	if (HwDeviceExtension->jChipType < XG20) {
1254 		u32 Temp;
1255 
1256 		/* Set AGP customize registers (in SetDefAGPRegs) Start */
1257 		for (i = 0x47; i <= 0x4C; i++)
1258 			xgifb_reg_set(pVBInfo->P3d4,
1259 				      i,
1260 				      XGI340_AGPReg[i - 0x47]);
1261 
1262 		for (i = 0x70; i <= 0x71; i++)
1263 			xgifb_reg_set(pVBInfo->P3d4,
1264 				      i,
1265 				      XGI340_AGPReg[6 + i - 0x70]);
1266 
1267 		for (i = 0x74; i <= 0x77; i++)
1268 			xgifb_reg_set(pVBInfo->P3d4,
1269 				      i,
1270 				      XGI340_AGPReg[8 + i - 0x74]);
1271 
1272 		pci_read_config_dword(pdev, 0x50, &Temp);
1273 		Temp >>= 20;
1274 		Temp &= 0xF;
1275 
1276 		if (Temp == 1)
1277 			xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1278 	} /* != XG20 */
1279 
1280 	/* Set PCI */
1281 	xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1282 	xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1283 	xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1284 
1285 	if (HwDeviceExtension->jChipType < XG20) {
1286 		/* Set VB */
1287 		XGI_UnLockCRT2(pVBInfo);
1288 		/* disable VideoCapture */
1289 		xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1290 		xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1291 		/* chk if BCLK>=100MHz */
1292 		temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1293 
1294 		xgifb_reg_set(pVBInfo->Part1Port,
1295 			      0x02, XGI330_CRT2Data_1_2);
1296 
1297 		xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1298 	} /* != XG20 */
1299 
1300 	xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1301 
1302 	if ((HwDeviceExtension->jChipType == XG42) &&
1303 	    XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1304 		/* Not DDR */
1305 		xgifb_reg_set(pVBInfo->P3c4,
1306 			      0x31,
1307 			      (XGI330_SR31 & 0x3F) | 0x40);
1308 		xgifb_reg_set(pVBInfo->P3c4,
1309 			      0x32,
1310 			      (XGI330_SR32 & 0xFC) | 0x01);
1311 	} else {
1312 		xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1313 		xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1314 	}
1315 	xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1316 
1317 	if (HwDeviceExtension->jChipType < XG20) {
1318 		if (xgifb_bridge_is_on(pVBInfo)) {
1319 			xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1320 			xgifb_reg_set(pVBInfo->Part4Port,
1321 				      0x0D, XGI330_CRT2Data_4_D);
1322 			xgifb_reg_set(pVBInfo->Part4Port,
1323 				      0x0E, XGI330_CRT2Data_4_E);
1324 			xgifb_reg_set(pVBInfo->Part4Port,
1325 				      0x10, XGI330_CRT2Data_4_10);
1326 			xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1327 			XGI_LockCRT2(pVBInfo);
1328 		}
1329 	} /* != XG20 */
1330 
1331 	XGI_SenseCRT1(pVBInfo);
1332 
1333 	if (HwDeviceExtension->jChipType == XG21) {
1334 		xgifb_reg_and_or(pVBInfo->P3d4,
1335 				 0x32,
1336 				 ~Monitor1Sense,
1337 				 Monitor1Sense); /* Z9 default has CRT */
1338 		temp = GetXG21FPBits(pVBInfo);
1339 		xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1340 	}
1341 	if (HwDeviceExtension->jChipType == XG27) {
1342 		xgifb_reg_and_or(pVBInfo->P3d4,
1343 				 0x32,
1344 				 ~Monitor1Sense,
1345 				 Monitor1Sense); /* Z9 default has CRT */
1346 		temp = GetXG27FPBits(pVBInfo);
1347 		xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1348 	}
1349 
1350 	pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1351 
1352 	XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1353 					 pVBInfo->P3d4,
1354 					 pVBInfo);
1355 
1356 	XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1357 
1358 	xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1359 	xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1360 
1361 	XGINew_ChkSenseStatus(pVBInfo);
1362 	XGINew_SetModeScratch(pVBInfo);
1363 
1364 	xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1365 
1366 	return 1;
1367 } /* end of init */
1368