1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4 * All rights reserved.
5 */
6
7 #include <linux/mmc/sdio_func.h>
8 #include <linux/mmc/host.h>
9
10 #include "wilc_wfi_netdevice.h"
11
12 #define SDIO_MODALIAS "wilc1000_sdio"
13
14 #define SDIO_VENDOR_ID_WILC 0x0296
15 #define SDIO_DEVICE_ID_WILC 0x5347
16
17 static const struct sdio_device_id wilc_sdio_ids[] = {
18 { SDIO_DEVICE(SDIO_VENDOR_ID_WILC, SDIO_DEVICE_ID_WILC) },
19 { },
20 };
21
22 #define WILC_SDIO_BLOCK_SIZE 512
23
24 struct wilc_sdio {
25 bool irq_gpio;
26 u32 block_size;
27 int nint;
28 /* Max num interrupts allowed in registers 0xf7, 0xf8 */
29 #define MAX_NUN_INT_THRPT_ENH2 (5)
30 int has_thrpt_enh3;
31 };
32
33 static struct wilc_sdio g_sdio;
34 static const struct wilc_hif_func wilc_hif_sdio;
35
36 static int sdio_write_reg(struct wilc *wilc, u32 addr, u32 data);
37 static int sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data);
38 static int sdio_init(struct wilc *wilc, bool resume);
39
wilc_sdio_interrupt(struct sdio_func * func)40 static void wilc_sdio_interrupt(struct sdio_func *func)
41 {
42 sdio_release_host(func);
43 wilc_handle_isr(sdio_get_drvdata(func));
44 sdio_claim_host(func);
45 }
46
wilc_sdio_cmd52(struct wilc * wilc,struct sdio_cmd52 * cmd)47 static int wilc_sdio_cmd52(struct wilc *wilc, struct sdio_cmd52 *cmd)
48 {
49 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
50 int ret;
51 u8 data;
52
53 sdio_claim_host(func);
54
55 func->num = cmd->function;
56 if (cmd->read_write) { /* write */
57 if (cmd->raw) {
58 sdio_writeb(func, cmd->data, cmd->address, &ret);
59 data = sdio_readb(func, cmd->address, &ret);
60 cmd->data = data;
61 } else {
62 sdio_writeb(func, cmd->data, cmd->address, &ret);
63 }
64 } else { /* read */
65 data = sdio_readb(func, cmd->address, &ret);
66 cmd->data = data;
67 }
68
69 sdio_release_host(func);
70
71 if (ret)
72 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
73 return ret;
74 }
75
wilc_sdio_cmd53(struct wilc * wilc,struct sdio_cmd53 * cmd)76 static int wilc_sdio_cmd53(struct wilc *wilc, struct sdio_cmd53 *cmd)
77 {
78 struct sdio_func *func = container_of(wilc->dev, struct sdio_func, dev);
79 int size, ret;
80
81 sdio_claim_host(func);
82
83 func->num = cmd->function;
84 func->cur_blksize = cmd->block_size;
85 if (cmd->block_mode)
86 size = cmd->count * cmd->block_size;
87 else
88 size = cmd->count;
89
90 if (cmd->read_write) { /* write */
91 ret = sdio_memcpy_toio(func, cmd->address,
92 (void *)cmd->buffer, size);
93 } else { /* read */
94 ret = sdio_memcpy_fromio(func, (void *)cmd->buffer,
95 cmd->address, size);
96 }
97
98 sdio_release_host(func);
99
100 if (ret)
101 dev_err(&func->dev, "%s..failed, err(%d)\n", __func__, ret);
102
103 return ret;
104 }
105
linux_sdio_probe(struct sdio_func * func,const struct sdio_device_id * id)106 static int linux_sdio_probe(struct sdio_func *func,
107 const struct sdio_device_id *id)
108 {
109 struct wilc *wilc;
110 int ret;
111 struct gpio_desc *gpio = NULL;
112
113 if (IS_ENABLED(CONFIG_WILC1000_HW_OOB_INTR)) {
114 gpio = gpiod_get(&func->dev, "irq", GPIOD_IN);
115 if (IS_ERR(gpio)) {
116 /* get the GPIO descriptor from hardcode GPIO number */
117 gpio = gpio_to_desc(GPIO_NUM);
118 if (!gpio)
119 dev_err(&func->dev, "failed to get irq gpio\n");
120 }
121 }
122
123 dev_dbg(&func->dev, "Initializing netdev\n");
124 ret = wilc_netdev_init(&wilc, &func->dev, HIF_SDIO, &wilc_hif_sdio);
125 if (ret) {
126 dev_err(&func->dev, "Couldn't initialize netdev\n");
127 return ret;
128 }
129 sdio_set_drvdata(func, wilc);
130 wilc->dev = &func->dev;
131 wilc->gpio_irq = gpio;
132
133 dev_info(&func->dev, "Driver Initializing success\n");
134 return 0;
135 }
136
linux_sdio_remove(struct sdio_func * func)137 static void linux_sdio_remove(struct sdio_func *func)
138 {
139 struct wilc *wilc = sdio_get_drvdata(func);
140
141 /* free the GPIO in module remove */
142 if (wilc->gpio_irq)
143 gpiod_put(wilc->gpio_irq);
144 wilc_netdev_cleanup(wilc);
145 }
146
sdio_reset(struct wilc * wilc)147 static int sdio_reset(struct wilc *wilc)
148 {
149 struct sdio_cmd52 cmd;
150 int ret;
151 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
152
153 cmd.read_write = 1;
154 cmd.function = 0;
155 cmd.raw = 0;
156 cmd.address = 0x6;
157 cmd.data = 0x8;
158 ret = wilc_sdio_cmd52(wilc, &cmd);
159 if (ret) {
160 dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n");
161 return ret;
162 }
163 return 0;
164 }
165
wilc_sdio_suspend(struct device * dev)166 static int wilc_sdio_suspend(struct device *dev)
167 {
168 struct sdio_func *func = dev_to_sdio_func(dev);
169 struct wilc *wilc = sdio_get_drvdata(func);
170 int ret;
171
172 dev_info(dev, "sdio suspend\n");
173 chip_wakeup(wilc);
174
175 if (!wilc->suspend_event) {
176 wilc_chip_sleep_manually(wilc);
177 } else {
178 host_sleep_notify(wilc);
179 chip_allow_sleep(wilc);
180 }
181
182 ret = sdio_reset(wilc);
183 if (ret) {
184 dev_err(&func->dev, "Fail reset sdio\n");
185 return ret;
186 }
187 sdio_claim_host(func);
188
189 return 0;
190 }
191
wilc_sdio_resume(struct device * dev)192 static int wilc_sdio_resume(struct device *dev)
193 {
194 struct sdio_func *func = dev_to_sdio_func(dev);
195 struct wilc *wilc = sdio_get_drvdata(func);
196
197 dev_info(dev, "sdio resume\n");
198 sdio_release_host(func);
199 chip_wakeup(wilc);
200 sdio_init(wilc, true);
201
202 if (wilc->suspend_event)
203 host_wakeup_notify(wilc);
204
205 chip_allow_sleep(wilc);
206
207 return 0;
208 }
209
210 static const struct of_device_id wilc_of_match[] = {
211 { .compatible = "microchip,wilc1000-sdio", },
212 { /* sentinel */ }
213 };
214 MODULE_DEVICE_TABLE(of, wilc_of_match);
215
216 static const struct dev_pm_ops wilc_sdio_pm_ops = {
217 .suspend = wilc_sdio_suspend,
218 .resume = wilc_sdio_resume,
219 };
220
221 static struct sdio_driver wilc_sdio_driver = {
222 .name = SDIO_MODALIAS,
223 .id_table = wilc_sdio_ids,
224 .probe = linux_sdio_probe,
225 .remove = linux_sdio_remove,
226 .drv = {
227 .pm = &wilc_sdio_pm_ops,
228 .of_match_table = wilc_of_match,
229 }
230 };
231 module_driver(wilc_sdio_driver,
232 sdio_register_driver,
233 sdio_unregister_driver);
234 MODULE_LICENSE("GPL");
235
wilc_sdio_enable_interrupt(struct wilc * dev)236 static int wilc_sdio_enable_interrupt(struct wilc *dev)
237 {
238 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
239 int ret = 0;
240
241 sdio_claim_host(func);
242 ret = sdio_claim_irq(func, wilc_sdio_interrupt);
243 sdio_release_host(func);
244
245 if (ret < 0) {
246 dev_err(&func->dev, "can't claim sdio_irq, err(%d)\n", ret);
247 ret = -EIO;
248 }
249 return ret;
250 }
251
wilc_sdio_disable_interrupt(struct wilc * dev)252 static void wilc_sdio_disable_interrupt(struct wilc *dev)
253 {
254 struct sdio_func *func = container_of(dev->dev, struct sdio_func, dev);
255 int ret;
256
257 sdio_claim_host(func);
258 ret = sdio_release_irq(func);
259 if (ret < 0)
260 dev_err(&func->dev, "can't release sdio_irq, err(%d)\n", ret);
261 sdio_release_host(func);
262 }
263
264 /********************************************
265 *
266 * Function 0
267 *
268 ********************************************/
269
sdio_set_func0_csa_address(struct wilc * wilc,u32 adr)270 static int sdio_set_func0_csa_address(struct wilc *wilc, u32 adr)
271 {
272 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
273 struct sdio_cmd52 cmd;
274 int ret;
275
276 /**
277 * Review: BIG ENDIAN
278 **/
279 cmd.read_write = 1;
280 cmd.function = 0;
281 cmd.raw = 0;
282 cmd.address = 0x10c;
283 cmd.data = (u8)adr;
284 ret = wilc_sdio_cmd52(wilc, &cmd);
285 if (ret) {
286 dev_err(&func->dev, "Failed cmd52, set 0x10c data...\n");
287 goto fail;
288 }
289
290 cmd.address = 0x10d;
291 cmd.data = (u8)(adr >> 8);
292 ret = wilc_sdio_cmd52(wilc, &cmd);
293 if (ret) {
294 dev_err(&func->dev, "Failed cmd52, set 0x10d data...\n");
295 goto fail;
296 }
297
298 cmd.address = 0x10e;
299 cmd.data = (u8)(adr >> 16);
300 ret = wilc_sdio_cmd52(wilc, &cmd);
301 if (ret) {
302 dev_err(&func->dev, "Failed cmd52, set 0x10e data...\n");
303 goto fail;
304 }
305
306 return 1;
307 fail:
308 return 0;
309 }
310
sdio_set_func0_block_size(struct wilc * wilc,u32 block_size)311 static int sdio_set_func0_block_size(struct wilc *wilc, u32 block_size)
312 {
313 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
314 struct sdio_cmd52 cmd;
315 int ret;
316
317 cmd.read_write = 1;
318 cmd.function = 0;
319 cmd.raw = 0;
320 cmd.address = 0x10;
321 cmd.data = (u8)block_size;
322 ret = wilc_sdio_cmd52(wilc, &cmd);
323 if (ret) {
324 dev_err(&func->dev, "Failed cmd52, set 0x10 data...\n");
325 goto fail;
326 }
327
328 cmd.address = 0x11;
329 cmd.data = (u8)(block_size >> 8);
330 ret = wilc_sdio_cmd52(wilc, &cmd);
331 if (ret) {
332 dev_err(&func->dev, "Failed cmd52, set 0x11 data...\n");
333 goto fail;
334 }
335
336 return 1;
337 fail:
338 return 0;
339 }
340
341 /********************************************
342 *
343 * Function 1
344 *
345 ********************************************/
346
sdio_set_func1_block_size(struct wilc * wilc,u32 block_size)347 static int sdio_set_func1_block_size(struct wilc *wilc, u32 block_size)
348 {
349 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
350 struct sdio_cmd52 cmd;
351 int ret;
352
353 cmd.read_write = 1;
354 cmd.function = 0;
355 cmd.raw = 0;
356 cmd.address = 0x110;
357 cmd.data = (u8)block_size;
358 ret = wilc_sdio_cmd52(wilc, &cmd);
359 if (ret) {
360 dev_err(&func->dev, "Failed cmd52, set 0x110 data...\n");
361 goto fail;
362 }
363 cmd.address = 0x111;
364 cmd.data = (u8)(block_size >> 8);
365 ret = wilc_sdio_cmd52(wilc, &cmd);
366 if (ret) {
367 dev_err(&func->dev, "Failed cmd52, set 0x111 data...\n");
368 goto fail;
369 }
370
371 return 1;
372 fail:
373 return 0;
374 }
375
376 /********************************************
377 *
378 * Sdio interfaces
379 *
380 ********************************************/
sdio_write_reg(struct wilc * wilc,u32 addr,u32 data)381 static int sdio_write_reg(struct wilc *wilc, u32 addr, u32 data)
382 {
383 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
384 int ret;
385
386 cpu_to_le32s(&data);
387
388 if (addr >= 0xf0 && addr <= 0xff) {
389 struct sdio_cmd52 cmd;
390
391 cmd.read_write = 1;
392 cmd.function = 0;
393 cmd.raw = 0;
394 cmd.address = addr;
395 cmd.data = data;
396 ret = wilc_sdio_cmd52(wilc, &cmd);
397 if (ret) {
398 dev_err(&func->dev,
399 "Failed cmd 52, read reg (%08x) ...\n", addr);
400 goto fail;
401 }
402 } else {
403 struct sdio_cmd53 cmd;
404
405 /**
406 * set the AHB address
407 **/
408 if (!sdio_set_func0_csa_address(wilc, addr))
409 goto fail;
410
411 cmd.read_write = 1;
412 cmd.function = 0;
413 cmd.address = 0x10f;
414 cmd.block_mode = 0;
415 cmd.increment = 1;
416 cmd.count = 4;
417 cmd.buffer = (u8 *)&data;
418 cmd.block_size = g_sdio.block_size;
419 ret = wilc_sdio_cmd53(wilc, &cmd);
420 if (ret) {
421 dev_err(&func->dev,
422 "Failed cmd53, write reg (%08x)...\n", addr);
423 goto fail;
424 }
425 }
426
427 return 1;
428
429 fail:
430
431 return 0;
432 }
433
sdio_write(struct wilc * wilc,u32 addr,u8 * buf,u32 size)434 static int sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
435 {
436 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
437 u32 block_size = g_sdio.block_size;
438 struct sdio_cmd53 cmd;
439 int nblk, nleft, ret;
440
441 cmd.read_write = 1;
442 if (addr > 0) {
443 /**
444 * has to be word aligned...
445 **/
446 if (size & 0x3) {
447 size += 4;
448 size &= ~0x3;
449 }
450
451 /**
452 * func 0 access
453 **/
454 cmd.function = 0;
455 cmd.address = 0x10f;
456 } else {
457 /**
458 * has to be word aligned...
459 **/
460 if (size & 0x3) {
461 size += 4;
462 size &= ~0x3;
463 }
464
465 /**
466 * func 1 access
467 **/
468 cmd.function = 1;
469 cmd.address = 0;
470 }
471
472 nblk = size / block_size;
473 nleft = size % block_size;
474
475 if (nblk > 0) {
476 cmd.block_mode = 1;
477 cmd.increment = 1;
478 cmd.count = nblk;
479 cmd.buffer = buf;
480 cmd.block_size = block_size;
481 if (addr > 0) {
482 if (!sdio_set_func0_csa_address(wilc, addr))
483 goto fail;
484 }
485 ret = wilc_sdio_cmd53(wilc, &cmd);
486 if (ret) {
487 dev_err(&func->dev,
488 "Failed cmd53 [%x], block send...\n", addr);
489 goto fail;
490 }
491 if (addr > 0)
492 addr += nblk * block_size;
493 buf += nblk * block_size;
494 }
495
496 if (nleft > 0) {
497 cmd.block_mode = 0;
498 cmd.increment = 1;
499 cmd.count = nleft;
500 cmd.buffer = buf;
501
502 cmd.block_size = block_size;
503
504 if (addr > 0) {
505 if (!sdio_set_func0_csa_address(wilc, addr))
506 goto fail;
507 }
508 ret = wilc_sdio_cmd53(wilc, &cmd);
509 if (ret) {
510 dev_err(&func->dev,
511 "Failed cmd53 [%x], bytes send...\n", addr);
512 goto fail;
513 }
514 }
515
516 return 1;
517
518 fail:
519
520 return 0;
521 }
522
sdio_read_reg(struct wilc * wilc,u32 addr,u32 * data)523 static int sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data)
524 {
525 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
526 int ret;
527
528 if (addr >= 0xf0 && addr <= 0xff) {
529 struct sdio_cmd52 cmd;
530
531 cmd.read_write = 0;
532 cmd.function = 0;
533 cmd.raw = 0;
534 cmd.address = addr;
535 ret = wilc_sdio_cmd52(wilc, &cmd);
536 if (ret) {
537 dev_err(&func->dev,
538 "Failed cmd 52, read reg (%08x) ...\n", addr);
539 goto fail;
540 }
541 *data = cmd.data;
542 } else {
543 struct sdio_cmd53 cmd;
544
545 if (!sdio_set_func0_csa_address(wilc, addr))
546 goto fail;
547
548 cmd.read_write = 0;
549 cmd.function = 0;
550 cmd.address = 0x10f;
551 cmd.block_mode = 0;
552 cmd.increment = 1;
553 cmd.count = 4;
554 cmd.buffer = (u8 *)data;
555
556 cmd.block_size = g_sdio.block_size;
557 ret = wilc_sdio_cmd53(wilc, &cmd);
558 if (ret) {
559 dev_err(&func->dev,
560 "Failed cmd53, read reg (%08x)...\n", addr);
561 goto fail;
562 }
563 }
564
565 le32_to_cpus(data);
566
567 return 1;
568
569 fail:
570
571 return 0;
572 }
573
sdio_read(struct wilc * wilc,u32 addr,u8 * buf,u32 size)574 static int sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
575 {
576 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
577 u32 block_size = g_sdio.block_size;
578 struct sdio_cmd53 cmd;
579 int nblk, nleft, ret;
580
581 cmd.read_write = 0;
582 if (addr > 0) {
583 /**
584 * has to be word aligned...
585 **/
586 if (size & 0x3) {
587 size += 4;
588 size &= ~0x3;
589 }
590
591 /**
592 * func 0 access
593 **/
594 cmd.function = 0;
595 cmd.address = 0x10f;
596 } else {
597 /**
598 * has to be word aligned...
599 **/
600 if (size & 0x3) {
601 size += 4;
602 size &= ~0x3;
603 }
604
605 /**
606 * func 1 access
607 **/
608 cmd.function = 1;
609 cmd.address = 0;
610 }
611
612 nblk = size / block_size;
613 nleft = size % block_size;
614
615 if (nblk > 0) {
616 cmd.block_mode = 1;
617 cmd.increment = 1;
618 cmd.count = nblk;
619 cmd.buffer = buf;
620 cmd.block_size = block_size;
621 if (addr > 0) {
622 if (!sdio_set_func0_csa_address(wilc, addr))
623 goto fail;
624 }
625 ret = wilc_sdio_cmd53(wilc, &cmd);
626 if (ret) {
627 dev_err(&func->dev,
628 "Failed cmd53 [%x], block read...\n", addr);
629 goto fail;
630 }
631 if (addr > 0)
632 addr += nblk * block_size;
633 buf += nblk * block_size;
634 } /* if (nblk > 0) */
635
636 if (nleft > 0) {
637 cmd.block_mode = 0;
638 cmd.increment = 1;
639 cmd.count = nleft;
640 cmd.buffer = buf;
641
642 cmd.block_size = block_size;
643
644 if (addr > 0) {
645 if (!sdio_set_func0_csa_address(wilc, addr))
646 goto fail;
647 }
648 ret = wilc_sdio_cmd53(wilc, &cmd);
649 if (ret) {
650 dev_err(&func->dev,
651 "Failed cmd53 [%x], bytes read...\n", addr);
652 goto fail;
653 }
654 }
655
656 return 1;
657
658 fail:
659
660 return 0;
661 }
662
663 /********************************************
664 *
665 * Bus interfaces
666 *
667 ********************************************/
668
sdio_deinit(struct wilc * wilc)669 static int sdio_deinit(struct wilc *wilc)
670 {
671 return 1;
672 }
673
sdio_init(struct wilc * wilc,bool resume)674 static int sdio_init(struct wilc *wilc, bool resume)
675 {
676 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
677 struct sdio_cmd52 cmd;
678 int loop, ret;
679 u32 chipid;
680
681 if (!resume) {
682 memset(&g_sdio, 0, sizeof(struct wilc_sdio));
683 g_sdio.irq_gpio = wilc->dev_irq_num;
684 }
685
686 /**
687 * function 0 csa enable
688 **/
689 cmd.read_write = 1;
690 cmd.function = 0;
691 cmd.raw = 1;
692 cmd.address = 0x100;
693 cmd.data = 0x80;
694 ret = wilc_sdio_cmd52(wilc, &cmd);
695 if (ret) {
696 dev_err(&func->dev, "Fail cmd 52, enable csa...\n");
697 goto fail;
698 }
699
700 /**
701 * function 0 block size
702 **/
703 if (!sdio_set_func0_block_size(wilc, WILC_SDIO_BLOCK_SIZE)) {
704 dev_err(&func->dev, "Fail cmd 52, set func 0 block size...\n");
705 goto fail;
706 }
707 g_sdio.block_size = WILC_SDIO_BLOCK_SIZE;
708
709 /**
710 * enable func1 IO
711 **/
712 cmd.read_write = 1;
713 cmd.function = 0;
714 cmd.raw = 1;
715 cmd.address = 0x2;
716 cmd.data = 0x2;
717 ret = wilc_sdio_cmd52(wilc, &cmd);
718 if (ret) {
719 dev_err(&func->dev,
720 "Fail cmd 52, set IOE register...\n");
721 goto fail;
722 }
723
724 /**
725 * make sure func 1 is up
726 **/
727 cmd.read_write = 0;
728 cmd.function = 0;
729 cmd.raw = 0;
730 cmd.address = 0x3;
731 loop = 3;
732 do {
733 cmd.data = 0;
734 ret = wilc_sdio_cmd52(wilc, &cmd);
735 if (ret) {
736 dev_err(&func->dev,
737 "Fail cmd 52, get IOR register...\n");
738 goto fail;
739 }
740 if (cmd.data == 0x2)
741 break;
742 } while (loop--);
743
744 if (loop <= 0) {
745 dev_err(&func->dev, "Fail func 1 is not ready...\n");
746 goto fail;
747 }
748
749 /**
750 * func 1 is ready, set func 1 block size
751 **/
752 if (!sdio_set_func1_block_size(wilc, WILC_SDIO_BLOCK_SIZE)) {
753 dev_err(&func->dev, "Fail set func 1 block size...\n");
754 goto fail;
755 }
756
757 /**
758 * func 1 interrupt enable
759 **/
760 cmd.read_write = 1;
761 cmd.function = 0;
762 cmd.raw = 1;
763 cmd.address = 0x4;
764 cmd.data = 0x3;
765 ret = wilc_sdio_cmd52(wilc, &cmd);
766 if (ret) {
767 dev_err(&func->dev, "Fail cmd 52, set IEN register...\n");
768 goto fail;
769 }
770
771 /**
772 * make sure can read back chip id correctly
773 **/
774 if (!resume) {
775 if (!sdio_read_reg(wilc, 0x1000, &chipid)) {
776 dev_err(&func->dev, "Fail cmd read chip id...\n");
777 goto fail;
778 }
779 dev_err(&func->dev, "chipid (%08x)\n", chipid);
780 if ((chipid & 0xfff) > 0x2a0)
781 g_sdio.has_thrpt_enh3 = 1;
782 else
783 g_sdio.has_thrpt_enh3 = 0;
784 dev_info(&func->dev, "has_thrpt_enh3 = %d...\n",
785 g_sdio.has_thrpt_enh3);
786 }
787
788 return 1;
789
790 fail:
791
792 return 0;
793 }
794
sdio_read_size(struct wilc * wilc,u32 * size)795 static int sdio_read_size(struct wilc *wilc, u32 *size)
796 {
797 u32 tmp;
798 struct sdio_cmd52 cmd;
799
800 /**
801 * Read DMA count in words
802 **/
803 cmd.read_write = 0;
804 cmd.function = 0;
805 cmd.raw = 0;
806 cmd.address = 0xf2;
807 cmd.data = 0;
808 wilc_sdio_cmd52(wilc, &cmd);
809 tmp = cmd.data;
810
811 cmd.address = 0xf3;
812 cmd.data = 0;
813 wilc_sdio_cmd52(wilc, &cmd);
814 tmp |= (cmd.data << 8);
815
816 *size = tmp;
817 return 1;
818 }
819
sdio_read_int(struct wilc * wilc,u32 * int_status)820 static int sdio_read_int(struct wilc *wilc, u32 *int_status)
821 {
822 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
823 u32 tmp;
824 struct sdio_cmd52 cmd;
825
826 sdio_read_size(wilc, &tmp);
827
828 /**
829 * Read IRQ flags
830 **/
831 if (!g_sdio.irq_gpio) {
832 int i;
833
834 cmd.function = 1;
835 cmd.address = 0x04;
836 cmd.data = 0;
837 wilc_sdio_cmd52(wilc, &cmd);
838
839 if (cmd.data & BIT(0))
840 tmp |= INT_0;
841 if (cmd.data & BIT(2))
842 tmp |= INT_1;
843 if (cmd.data & BIT(3))
844 tmp |= INT_2;
845 if (cmd.data & BIT(4))
846 tmp |= INT_3;
847 if (cmd.data & BIT(5))
848 tmp |= INT_4;
849 if (cmd.data & BIT(6))
850 tmp |= INT_5;
851 for (i = g_sdio.nint; i < MAX_NUM_INT; i++) {
852 if ((tmp >> (IRG_FLAGS_OFFSET + i)) & 0x1) {
853 dev_err(&func->dev,
854 "Unexpected interrupt (1) : tmp=%x, data=%x\n",
855 tmp, cmd.data);
856 break;
857 }
858 }
859 } else {
860 u32 irq_flags;
861
862 cmd.read_write = 0;
863 cmd.function = 0;
864 cmd.raw = 0;
865 cmd.address = 0xf7;
866 cmd.data = 0;
867 wilc_sdio_cmd52(wilc, &cmd);
868 irq_flags = cmd.data & 0x1f;
869 tmp |= ((irq_flags >> 0) << IRG_FLAGS_OFFSET);
870 }
871
872 *int_status = tmp;
873
874 return 1;
875 }
876
sdio_clear_int_ext(struct wilc * wilc,u32 val)877 static int sdio_clear_int_ext(struct wilc *wilc, u32 val)
878 {
879 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
880 int ret;
881 int vmm_ctl;
882
883 if (g_sdio.has_thrpt_enh3) {
884 u32 reg;
885
886 if (g_sdio.irq_gpio) {
887 u32 flags;
888
889 flags = val & (BIT(MAX_NUN_INT_THRPT_ENH2) - 1);
890 reg = flags;
891 } else {
892 reg = 0;
893 }
894 /* select VMM table 0 */
895 if (val & SEL_VMM_TBL0)
896 reg |= BIT(5);
897 /* select VMM table 1 */
898 if (val & SEL_VMM_TBL1)
899 reg |= BIT(6);
900 /* enable VMM */
901 if (val & EN_VMM)
902 reg |= BIT(7);
903 if (reg) {
904 struct sdio_cmd52 cmd;
905
906 cmd.read_write = 1;
907 cmd.function = 0;
908 cmd.raw = 0;
909 cmd.address = 0xf8;
910 cmd.data = reg;
911
912 ret = wilc_sdio_cmd52(wilc, &cmd);
913 if (ret) {
914 dev_err(&func->dev,
915 "Failed cmd52, set 0xf8 data (%d) ...\n",
916 __LINE__);
917 goto fail;
918 }
919 }
920 return 1;
921 }
922 if (g_sdio.irq_gpio) {
923 /* has_thrpt_enh2 uses register 0xf8 to clear interrupts. */
924 /*
925 * Cannot clear multiple interrupts.
926 * Must clear each interrupt individually.
927 */
928 u32 flags;
929
930 flags = val & (BIT(MAX_NUM_INT) - 1);
931 if (flags) {
932 int i;
933
934 ret = 1;
935 for (i = 0; i < g_sdio.nint; i++) {
936 if (flags & 1) {
937 struct sdio_cmd52 cmd;
938
939 cmd.read_write = 1;
940 cmd.function = 0;
941 cmd.raw = 0;
942 cmd.address = 0xf8;
943 cmd.data = BIT(i);
944
945 ret = wilc_sdio_cmd52(wilc, &cmd);
946 if (ret) {
947 dev_err(&func->dev,
948 "Failed cmd52, set 0xf8 data (%d) ...\n",
949 __LINE__);
950 goto fail;
951 }
952 }
953 if (!ret)
954 break;
955 flags >>= 1;
956 }
957 if (!ret)
958 goto fail;
959 for (i = g_sdio.nint; i < MAX_NUM_INT; i++) {
960 if (flags & 1)
961 dev_err(&func->dev,
962 "Unexpected interrupt cleared %d...\n",
963 i);
964 flags >>= 1;
965 }
966 }
967 }
968
969 vmm_ctl = 0;
970 /* select VMM table 0 */
971 if (val & SEL_VMM_TBL0)
972 vmm_ctl |= BIT(0);
973 /* select VMM table 1 */
974 if (val & SEL_VMM_TBL1)
975 vmm_ctl |= BIT(1);
976 /* enable VMM */
977 if (val & EN_VMM)
978 vmm_ctl |= BIT(2);
979
980 if (vmm_ctl) {
981 struct sdio_cmd52 cmd;
982
983 cmd.read_write = 1;
984 cmd.function = 0;
985 cmd.raw = 0;
986 cmd.address = 0xf6;
987 cmd.data = vmm_ctl;
988 ret = wilc_sdio_cmd52(wilc, &cmd);
989 if (ret) {
990 dev_err(&func->dev,
991 "Failed cmd52, set 0xf6 data (%d) ...\n",
992 __LINE__);
993 goto fail;
994 }
995 }
996 return 1;
997 fail:
998 return 0;
999 }
1000
sdio_sync_ext(struct wilc * wilc,int nint)1001 static int sdio_sync_ext(struct wilc *wilc, int nint)
1002 {
1003 struct sdio_func *func = dev_to_sdio_func(wilc->dev);
1004 u32 reg;
1005
1006 if (nint > MAX_NUM_INT) {
1007 dev_err(&func->dev, "Too many interrupts (%d)...\n", nint);
1008 return 0;
1009 }
1010 if (nint > MAX_NUN_INT_THRPT_ENH2) {
1011 dev_err(&func->dev,
1012 "Cannot support more than 5 interrupts when has_thrpt_enh2=1.\n");
1013 return 0;
1014 }
1015
1016 g_sdio.nint = nint;
1017
1018 /**
1019 * Disable power sequencer
1020 **/
1021 if (!sdio_read_reg(wilc, WILC_MISC, ®)) {
1022 dev_err(&func->dev, "Failed read misc reg...\n");
1023 return 0;
1024 }
1025
1026 reg &= ~BIT(8);
1027 if (!sdio_write_reg(wilc, WILC_MISC, reg)) {
1028 dev_err(&func->dev, "Failed write misc reg...\n");
1029 return 0;
1030 }
1031
1032 if (g_sdio.irq_gpio) {
1033 u32 reg;
1034 int ret, i;
1035
1036 /**
1037 * interrupt pin mux select
1038 **/
1039 ret = sdio_read_reg(wilc, WILC_PIN_MUX_0, ®);
1040 if (!ret) {
1041 dev_err(&func->dev, "Failed read reg (%08x)...\n",
1042 WILC_PIN_MUX_0);
1043 return 0;
1044 }
1045 reg |= BIT(8);
1046 ret = sdio_write_reg(wilc, WILC_PIN_MUX_0, reg);
1047 if (!ret) {
1048 dev_err(&func->dev, "Failed write reg (%08x)...\n",
1049 WILC_PIN_MUX_0);
1050 return 0;
1051 }
1052
1053 /**
1054 * interrupt enable
1055 **/
1056 ret = sdio_read_reg(wilc, WILC_INTR_ENABLE, ®);
1057 if (!ret) {
1058 dev_err(&func->dev, "Failed read reg (%08x)...\n",
1059 WILC_INTR_ENABLE);
1060 return 0;
1061 }
1062
1063 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1064 reg |= BIT((27 + i));
1065 ret = sdio_write_reg(wilc, WILC_INTR_ENABLE, reg);
1066 if (!ret) {
1067 dev_err(&func->dev, "Failed write reg (%08x)...\n",
1068 WILC_INTR_ENABLE);
1069 return 0;
1070 }
1071 if (nint) {
1072 ret = sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1073 if (!ret) {
1074 dev_err(&func->dev,
1075 "Failed read reg (%08x)...\n",
1076 WILC_INTR2_ENABLE);
1077 return 0;
1078 }
1079
1080 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1081 reg |= BIT(i);
1082
1083 ret = sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1084 if (!ret) {
1085 dev_err(&func->dev,
1086 "Failed write reg (%08x)...\n",
1087 WILC_INTR2_ENABLE);
1088 return 0;
1089 }
1090 }
1091 }
1092 return 1;
1093 }
1094
1095 /* Global sdio HIF function table */
1096 static const struct wilc_hif_func wilc_hif_sdio = {
1097 .hif_init = sdio_init,
1098 .hif_deinit = sdio_deinit,
1099 .hif_read_reg = sdio_read_reg,
1100 .hif_write_reg = sdio_write_reg,
1101 .hif_block_rx = sdio_read,
1102 .hif_block_tx = sdio_write,
1103 .hif_read_int = sdio_read_int,
1104 .hif_clear_int_ext = sdio_clear_int_ext,
1105 .hif_read_size = sdio_read_size,
1106 .hif_block_tx_ext = sdio_write,
1107 .hif_block_rx_ext = sdio_read,
1108 .hif_sync_ext = sdio_sync_ext,
1109 .enable_interrupt = wilc_sdio_enable_interrupt,
1110 .disable_interrupt = wilc_sdio_disable_interrupt,
1111 };
1112
1113
