1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2016 Realtek Corporation.
5 *
6 * Contact Information:
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
9 * Hsinchu 300, Taiwan.
10 *
11 * Larry Finger <Larry.Finger@lwfinger.net>
12 *
13 *****************************************************************************/
14
15 #include "../wifi.h"
16 #include "../efuse.h"
17 #include "../base.h"
18 #include "../regd.h"
19 #include "../cam.h"
20 #include "../ps.h"
21 #include "../pci.h"
22 #include "reg.h"
23 #include "def.h"
24 #include "phy.h"
25 #include "fw.h"
26 #include "led.h"
27 #include "hw.h"
28
29 #define LLT_CONFIG 5
30
31 u8 rtl_channel5g[CHANNEL_MAX_NUMBER_5G] = {
32 36, 38, 40, 42, 44, 46, 48, /* Band 1 */
33 52, 54, 56, 58, 60, 62, 64, /* Band 2 */
34 100, 102, 104, 106, 108, 110, 112, /* Band 3 */
35 116, 118, 120, 122, 124, 126, 128, /* Band 3 */
36 132, 134, 136, 138, 140, 142, 144, /* Band 3 */
37 149, 151, 153, 155, 157, 159, 161, /* Band 4 */
38 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
39 u8 rtl_channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122,
40 138, 155, 171};
41
_rtl8822be_set_bcn_ctrl_reg(struct ieee80211_hw * hw,u8 set_bits,u8 clear_bits)42 static void _rtl8822be_set_bcn_ctrl_reg(struct ieee80211_hw *hw, u8 set_bits,
43 u8 clear_bits)
44 {
45 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47
48 rtlpci->reg_bcn_ctrl_val |= set_bits;
49 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
50
51 rtl_write_byte(rtlpriv, REG_BCN_CTRL_8822B,
52 (u8)rtlpci->reg_bcn_ctrl_val);
53 }
54
_rtl8822be_stop_tx_beacon(struct ieee80211_hw * hw)55 static void _rtl8822be_stop_tx_beacon(struct ieee80211_hw *hw)
56 {
57 struct rtl_priv *rtlpriv = rtl_priv(hw);
58 u8 tmp;
59
60 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2);
61 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2, tmp & (~BIT(6)));
62 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 1, 0x64);
63 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2);
64 tmp &= ~(BIT(0));
65 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2, tmp);
66 }
67
_rtl8822be_resume_tx_beacon(struct ieee80211_hw * hw)68 static void _rtl8822be_resume_tx_beacon(struct ieee80211_hw *hw)
69 {
70 struct rtl_priv *rtlpriv = rtl_priv(hw);
71 u8 tmp;
72
73 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2);
74 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2, tmp | BIT(6));
75 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 1, 0xff);
76 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2);
77 tmp |= BIT(0);
78 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT_8822B + 2, tmp);
79 }
80
_rtl8822be_enable_bcn_sub_func(struct ieee80211_hw * hw)81 static void _rtl8822be_enable_bcn_sub_func(struct ieee80211_hw *hw)
82 {
83 _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(1));
84 }
85
_rtl8822be_disable_bcn_sub_func(struct ieee80211_hw * hw)86 static void _rtl8822be_disable_bcn_sub_func(struct ieee80211_hw *hw)
87 {
88 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(1), 0);
89 }
90
_rtl8822be_set_fw_clock_on(struct ieee80211_hw * hw,u8 rpwm_val,bool b_need_turn_off_ckk)91 static void _rtl8822be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
92 bool b_need_turn_off_ckk)
93 {
94 struct rtl_priv *rtlpriv = rtl_priv(hw);
95 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
96 u32 count = 0, isr_regaddr, content;
97 bool b_schedule_timer = b_need_turn_off_ckk;
98
99 if (!rtlhal->fw_ready)
100 return;
101 if (!rtlpriv->psc.fw_current_inpsmode)
102 return;
103
104 while (1) {
105 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
106 if (rtlhal->fw_clk_change_in_progress) {
107 while (rtlhal->fw_clk_change_in_progress) {
108 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
109 count++;
110 udelay(100);
111 if (count > 1000)
112 return;
113 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
114 }
115 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
116 } else {
117 rtlhal->fw_clk_change_in_progress = false;
118 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
119 break;
120 }
121 }
122
123 if (IS_IN_LOW_POWER_STATE_8822B(rtlhal->fw_ps_state)) {
124 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
125 (u8 *)(&rpwm_val));
126 if (FW_PS_IS_ACK(rpwm_val)) {
127 isr_regaddr = REG_HISR0_8822B;
128 content = rtl_read_dword(rtlpriv, isr_regaddr);
129 while (!(content & IMR_CPWM) && (count < 500)) {
130 udelay(50);
131 count++;
132 content = rtl_read_dword(rtlpriv, isr_regaddr);
133 }
134
135 if (content & IMR_CPWM) {
136 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
137 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8822B;
138 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
139 "Receive CPWM INT!!! PSState = %X\n",
140 rtlhal->fw_ps_state);
141 }
142 }
143
144 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
145 rtlhal->fw_clk_change_in_progress = false;
146 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
147 if (b_schedule_timer) {
148 mod_timer(&rtlpriv->works.fw_clockoff_timer,
149 jiffies + MSECS(10));
150 }
151
152 } else {
153 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
154 rtlhal->fw_clk_change_in_progress = false;
155 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
156 }
157 }
158
_rtl8822be_set_fw_clock_off(struct ieee80211_hw * hw,u8 rpwm_val)159 static void _rtl8822be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
160 {
161 struct rtl_priv *rtlpriv = rtl_priv(hw);
162 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
163 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
164 struct rtl8192_tx_ring *ring;
165 enum rf_pwrstate rtstate;
166 bool b_schedule_timer = false;
167 u8 queue;
168
169 if (!rtlhal->fw_ready)
170 return;
171 if (!rtlpriv->psc.fw_current_inpsmode)
172 return;
173 if (!rtlhal->allow_sw_to_change_hwclc)
174 return;
175
176 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
177 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
178 return;
179
180 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
181 ring = &rtlpci->tx_ring[queue];
182 if (skb_queue_len(&ring->queue)) {
183 b_schedule_timer = true;
184 break;
185 }
186 }
187
188 if (b_schedule_timer) {
189 mod_timer(&rtlpriv->works.fw_clockoff_timer,
190 jiffies + MSECS(10));
191 return;
192 }
193
194 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
195 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
196 if (!rtlhal->fw_clk_change_in_progress) {
197 rtlhal->fw_clk_change_in_progress = true;
198 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
199 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
200 rtl_write_word(rtlpriv, REG_HISR0_8822B, 0x0100);
201 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
202 (u8 *)(&rpwm_val));
203 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
204 rtlhal->fw_clk_change_in_progress = false;
205 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
206 } else {
207 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
208 mod_timer(&rtlpriv->works.fw_clockoff_timer,
209 jiffies + MSECS(10));
210 }
211 }
212 }
213
_rtl8822be_set_fw_ps_rf_on(struct ieee80211_hw * hw)214 static void _rtl8822be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
215 {
216 u8 rpwm_val = 0;
217
218 rpwm_val |= (FW_PS_STATE_RF_OFF_8822B | FW_PS_ACK);
219 _rtl8822be_set_fw_clock_on(hw, rpwm_val, true);
220 }
221
_rtl8822be_set_fw_ps_rf_off_low_power(struct ieee80211_hw * hw)222 static void _rtl8822be_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
223 {
224 u8 rpwm_val = 0;
225
226 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR;
227 _rtl8822be_set_fw_clock_off(hw, rpwm_val);
228 }
229
rtl8822be_fw_clk_off_timer_callback(unsigned long data)230 void rtl8822be_fw_clk_off_timer_callback(unsigned long data)
231 {
232 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
233
234 _rtl8822be_set_fw_ps_rf_off_low_power(hw);
235 }
236
_rtl8822be_fwlps_leave(struct ieee80211_hw * hw)237 static void _rtl8822be_fwlps_leave(struct ieee80211_hw *hw)
238 {
239 struct rtl_priv *rtlpriv = rtl_priv(hw);
240 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
241 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
242 bool fw_current_inps = false;
243 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
244
245 if (ppsc->low_power_enable) {
246 rpwm_val = (FW_PS_STATE_ALL_ON_8822B | FW_PS_ACK); /* RF on */
247 _rtl8822be_set_fw_clock_on(hw, rpwm_val, false);
248 rtlhal->allow_sw_to_change_hwclc = false;
249 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
250 (u8 *)(&fw_pwrmode));
251 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
252 (u8 *)(&fw_current_inps));
253 } else {
254 rpwm_val = FW_PS_STATE_ALL_ON_8822B; /* RF on */
255 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
256 (u8 *)(&rpwm_val));
257 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
258 (u8 *)(&fw_pwrmode));
259 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
260 (u8 *)(&fw_current_inps));
261 }
262 }
263
_rtl8822be_fwlps_enter(struct ieee80211_hw * hw)264 static void _rtl8822be_fwlps_enter(struct ieee80211_hw *hw)
265 {
266 struct rtl_priv *rtlpriv = rtl_priv(hw);
267 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
268 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
269 bool fw_current_inps = true;
270 u8 rpwm_val;
271
272 if (ppsc->low_power_enable) {
273 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */
274 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
275 (u8 *)(&fw_current_inps));
276 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
277 (u8 *)(&ppsc->fwctrl_psmode));
278 rtlhal->allow_sw_to_change_hwclc = true;
279 _rtl8822be_set_fw_clock_off(hw, rpwm_val);
280 } else {
281 rpwm_val = FW_PS_STATE_RF_OFF_8822B; /* RF off */
282 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
283 (u8 *)(&fw_current_inps));
284 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
285 (u8 *)(&ppsc->fwctrl_psmode));
286 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
287 (u8 *)(&rpwm_val));
288 }
289 }
290
rtl8822be_get_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)291 void rtl8822be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
292 {
293 struct rtl_priv *rtlpriv = rtl_priv(hw);
294 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
295 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
296
297 switch (variable) {
298 case HW_VAR_RCR:
299 *((u32 *)(val)) = rtlpci->receive_config;
300 break;
301 case HW_VAR_RF_STATE:
302 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
303 break;
304 case HW_VAR_FWLPS_RF_ON: {
305 enum rf_pwrstate rf_state;
306 u32 val_rcr;
307
308 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
309 (u8 *)(&rf_state));
310 if (rf_state == ERFOFF) {
311 *((bool *)(val)) = true;
312 } else {
313 val_rcr = rtl_read_dword(rtlpriv, REG_RCR_8822B);
314 val_rcr &= 0x00070000;
315 if (val_rcr)
316 *((bool *)(val)) = false;
317 else
318 *((bool *)(val)) = true;
319 }
320 } break;
321 case HW_VAR_FW_PSMODE_STATUS:
322 *((bool *)(val)) = ppsc->fw_current_inpsmode;
323 break;
324 case HW_VAR_CORRECT_TSF: {
325 u64 tsf;
326 u32 *ptsf_low = (u32 *)&tsf;
327 u32 *ptsf_high = ((u32 *)&tsf) + 1;
328
329 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR_8822B + 4));
330 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR_8822B);
331
332 *((u64 *)(val)) = tsf;
333
334 } break;
335 default:
336 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
337 "switch case not process %x\n", variable);
338 break;
339 }
340 }
341
_rtl8822be_download_rsvd_page(struct ieee80211_hw * hw)342 static void _rtl8822be_download_rsvd_page(struct ieee80211_hw *hw)
343 {
344 struct rtl_priv *rtlpriv = rtl_priv(hw);
345 u8 tmp_regcr, tmp_reg422;
346 u8 bcnvalid_reg /*, txbc_reg*/;
347 u8 count = 0, dlbcn_count = 0;
348 bool b_recover = false;
349
350 /*Set REG_CR_8822B bit 8. DMA beacon by SW.*/
351 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR_8822B + 1);
352 rtl_write_byte(rtlpriv, REG_CR_8822B + 1, tmp_regcr | BIT(0));
353
354 /* Disable Hw protection for a time which revserd for Hw sending beacon.
355 * Fix download reserved page packet fail
356 * that access collision with the protection time.
357 * 2010.05.11. Added by tynli.
358 */
359 _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(3));
360 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(4), 0);
361
362 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to
363 * tell Hw the packet is not a real beacon frame.
364 */
365 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2);
366 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2,
367 tmp_reg422 & (~BIT(6)));
368
369 if (tmp_reg422 & BIT(6))
370 b_recover = true;
371
372 do {
373 /* Clear beacon valid check bit */
374 bcnvalid_reg =
375 rtl_read_byte(rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1);
376 bcnvalid_reg = bcnvalid_reg | BIT(7);
377 rtl_write_byte(rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1,
378 bcnvalid_reg);
379
380 /* download rsvd page */
381 rtl8822be_set_fw_rsvdpagepkt(hw, false);
382
383 /* check rsvd page download OK. */
384 bcnvalid_reg =
385 rtl_read_byte(rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1);
386
387 count = 0;
388 while (!(BIT(7) & bcnvalid_reg) && count < 20) {
389 count++;
390 udelay(50);
391 bcnvalid_reg = rtl_read_byte(
392 rtlpriv, REG_FIFOPAGE_CTRL_2_8822B + 1);
393 }
394
395 dlbcn_count++;
396 } while (!(BIT(7) & bcnvalid_reg) && dlbcn_count < 5);
397
398 if (!(BIT(7) & bcnvalid_reg))
399 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
400 "Download RSVD page failed!\n");
401
402 /* Enable Bcn */
403 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(3), 0);
404 _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(4));
405
406 if (b_recover)
407 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL_8822B + 2,
408 tmp_reg422);
409 }
410
rtl8822be_set_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)411 void rtl8822be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
412 {
413 struct rtl_priv *rtlpriv = rtl_priv(hw);
414 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
415 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
416 struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw));
417 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
418
419 switch (variable) {
420 case HW_VAR_ETHER_ADDR:
421 rtlpriv->halmac.ops->halmac_set_mac_address(rtlpriv, 0, val);
422 break;
423 case HW_VAR_BASIC_RATE: {
424 u16 b_rate_cfg = ((u16 *)val)[0];
425
426 b_rate_cfg = b_rate_cfg & 0x15f;
427 b_rate_cfg |= 0x01;
428 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1));
429 rtl_write_byte(rtlpriv, REG_RRSR_8822B, b_rate_cfg & 0xff);
430 rtl_write_byte(rtlpriv, REG_RRSR_8822B + 1,
431 (b_rate_cfg >> 8) & 0xff);
432 } break;
433 case HW_VAR_BSSID:
434 rtlpriv->halmac.ops->halmac_set_bssid(rtlpriv, 0, val);
435 break;
436 case HW_VAR_SIFS:
437 rtl_write_byte(rtlpriv, REG_SIFS_8822B + 1, val[0]);
438 rtl_write_byte(rtlpriv, REG_SIFS_TRX_8822B + 1, val[1]);
439
440 rtl_write_byte(rtlpriv, REG_SPEC_SIFS_8822B + 1, val[0]);
441 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS_8822B + 1, val[0]);
442
443 if (!mac->ht_enable)
444 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM_8822B,
445 0x0e0e);
446 else
447 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM_8822B,
448 *((u16 *)val));
449 break;
450 case HW_VAR_SLOT_TIME: {
451 u8 e_aci;
452
453 RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE, "HW_VAR_SLOT_TIME %x\n",
454 val[0]);
455
456 rtl_write_byte(rtlpriv, REG_SLOT_8822B, val[0]);
457
458 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
459 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
460 (u8 *)(&e_aci));
461 }
462 } break;
463 case HW_VAR_ACK_PREAMBLE: {
464 u8 reg_tmp;
465 u8 short_preamble = (bool)(*(u8 *)val);
466
467 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5;
468 if (short_preamble)
469 reg_tmp |= 0x80;
470 rtl_write_byte(rtlpriv, REG_RRSR_8822B + 2, reg_tmp);
471 rtlpriv->mac80211.short_preamble = short_preamble;
472 } break;
473 case HW_VAR_WPA_CONFIG:
474 rtl_write_byte(rtlpriv, REG_SECCFG_8822B, *((u8 *)val));
475 break;
476 case HW_VAR_AMPDU_FACTOR: {
477 u32 ampdu_len = (*((u8 *)val));
478
479 ampdu_len = (0x2000 << ampdu_len) - 1;
480 rtl_write_dword(rtlpriv, REG_AMPDU_MAX_LENGTH_8822B, ampdu_len);
481 } break;
482 case HW_VAR_AC_PARAM: {
483 u8 e_aci = *((u8 *)val);
484
485 if (mac->vif && mac->vif->bss_conf.assoc && !mac->act_scanning)
486 rtl8822be_set_qos(hw, e_aci);
487
488 if (rtlpci->acm_method != EACMWAY2_SW)
489 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
490 (u8 *)(&e_aci));
491 } break;
492 case HW_VAR_ACM_CTRL: {
493 u8 e_aci = *((u8 *)val);
494 union aci_aifsn *aifs = (union aci_aifsn *)&mac->ac[0].aifs;
495
496 u8 acm = aifs->f.acm;
497 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL_8822B);
498
499 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
500
501 if (acm) {
502 switch (e_aci) {
503 case AC0_BE:
504 acm_ctrl |= ACMHW_BEQ_EN;
505 break;
506 case AC2_VI:
507 acm_ctrl |= ACMHW_VIQ_EN;
508 break;
509 case AC3_VO:
510 acm_ctrl |= ACMHW_VOQ_EN;
511 break;
512 default:
513 RT_TRACE(
514 rtlpriv, COMP_ERR, DBG_WARNING,
515 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
516 acm);
517 break;
518 }
519 } else {
520 switch (e_aci) {
521 case AC0_BE:
522 acm_ctrl &= (~ACMHW_BEQ_EN);
523 break;
524 case AC2_VI:
525 acm_ctrl &= (~ACMHW_VIQ_EN);
526 break;
527 case AC3_VO:
528 acm_ctrl &= (~ACMHW_VOQ_EN);
529 break;
530 default:
531 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
532 "switch case not process\n");
533 break;
534 }
535 }
536
537 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
538 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
539 acm_ctrl);
540 rtl_write_byte(rtlpriv, REG_ACMHWCTRL_8822B, acm_ctrl);
541 } break;
542 case HW_VAR_RCR: {
543 rtl_write_dword(rtlpriv, REG_RCR_8822B, ((u32 *)(val))[0]);
544 rtlpci->receive_config = ((u32 *)(val))[0];
545 } break;
546 case HW_VAR_RETRY_LIMIT: {
547 u8 retry_limit = ((u8 *)(val))[0];
548
549 rtl_write_word(rtlpriv, REG_RETRY_LIMIT_8822B,
550 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
551 retry_limit << RETRY_LIMIT_LONG_SHIFT);
552 } break;
553 case HW_VAR_DUAL_TSF_RST:
554 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST_8822B,
555 (BIT(0) | BIT(1)));
556 break;
557 case HW_VAR_EFUSE_BYTES:
558 efuse->efuse_usedbytes = *((u16 *)val);
559 break;
560 case HW_VAR_EFUSE_USAGE:
561 efuse->efuse_usedpercentage = *((u8 *)val);
562 break;
563 case HW_VAR_IO_CMD:
564 rtl8822be_phy_set_io_cmd(hw, (*(enum io_type *)val));
565 break;
566 case HW_VAR_SET_RPWM:
567 break;
568 case HW_VAR_H2C_FW_PWRMODE:
569 rtl8822be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
570 break;
571 case HW_VAR_FW_PSMODE_STATUS:
572 ppsc->fw_current_inpsmode = *((bool *)val);
573 break;
574 case HW_VAR_RESUME_CLK_ON:
575 _rtl8822be_set_fw_ps_rf_on(hw);
576 break;
577 case HW_VAR_FW_LPS_ACTION: {
578 bool b_enter_fwlps = *((bool *)val);
579
580 if (b_enter_fwlps)
581 _rtl8822be_fwlps_enter(hw);
582 else
583 _rtl8822be_fwlps_leave(hw);
584 } break;
585 case HW_VAR_H2C_FW_JOINBSSRPT: {
586 u8 mstatus = (*(u8 *)val);
587
588 if (mstatus == RT_MEDIA_CONNECT) {
589 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
590 _rtl8822be_download_rsvd_page(hw);
591 }
592 rtl8822be_set_default_port_id_cmd(hw);
593 rtl8822be_set_fw_media_status_rpt_cmd(hw, mstatus);
594 } break;
595 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
596 rtl8822be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
597 break;
598 case HW_VAR_AID: {
599 u16 u2btmp;
600
601 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT_8822B);
602 u2btmp &= 0xC000;
603 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT_8822B,
604 (u2btmp | mac->assoc_id));
605 } break;
606 case HW_VAR_CORRECT_TSF: {
607 u8 btype_ibss = ((u8 *)(val))[0];
608
609 if (btype_ibss)
610 _rtl8822be_stop_tx_beacon(hw);
611
612 _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(3));
613
614 rtl_write_dword(rtlpriv, REG_TSFTR_8822B,
615 (u32)(mac->tsf & 0xffffffff));
616 rtl_write_dword(rtlpriv, REG_TSFTR_8822B + 4,
617 (u32)((mac->tsf >> 32) & 0xffffffff));
618
619 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(3), 0);
620
621 if (btype_ibss)
622 _rtl8822be_resume_tx_beacon(hw);
623 } break;
624 case HW_VAR_KEEP_ALIVE: {
625 u8 array[2];
626
627 array[0] = 0xff;
628 array[1] = *((u8 *)val);
629 rtl8822be_fill_h2c_cmd(hw, H2C_8822B_KEEP_ALIVE_CTRL, 2, array);
630 } break;
631 default:
632 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
633 "switch case not process %x\n", variable);
634 break;
635 }
636 }
637
_rtl8822be_gen_refresh_led_state(struct ieee80211_hw * hw)638 static void _rtl8822be_gen_refresh_led_state(struct ieee80211_hw *hw)
639 {
640 struct rtl_priv *rtlpriv = rtl_priv(hw);
641 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
642 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
643 struct rtl_led *led0 = &pcipriv->ledctl.sw_led0;
644
645 if (rtlpriv->rtlhal.up_first_time)
646 return;
647
648 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
649 rtl8822be_sw_led_on(hw, led0);
650 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
651 rtl8822be_sw_led_on(hw, led0);
652 else
653 rtl8822be_sw_led_off(hw, led0);
654 }
655
_rtl8822be_init_trxbd(struct ieee80211_hw * hw)656 static bool _rtl8822be_init_trxbd(struct ieee80211_hw *hw)
657 {
658 struct rtl_priv *rtlpriv = rtl_priv(hw);
659 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
660 /*struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));*/
661
662 u8 bytetmp;
663 /*u16 wordtmp;*/
664 u32 dwordtmp;
665
666 /* Set TX/RX descriptor physical address -- HI part */
667 if (!rtlpriv->cfg->mod_params->dma64)
668 goto dma64_end;
669
670 rtl_write_dword(rtlpriv, REG_H2CQ_TXBD_DESA_8822B + 4,
671 ((u64)rtlpci->tx_ring[H2C_QUEUE].buffer_desc_dma) >>
672 32);
673 rtl_write_dword(rtlpriv, REG_BCNQ_TXBD_DESA_8822B + 4,
674 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) >>
675 32);
676 rtl_write_dword(rtlpriv, REG_MGQ_TXBD_DESA_8822B + 4,
677 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma >> 32);
678 rtl_write_dword(rtlpriv, REG_VOQ_TXBD_DESA_8822B + 4,
679 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma >> 32);
680 rtl_write_dword(rtlpriv, REG_VIQ_TXBD_DESA_8822B + 4,
681 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma >> 32);
682 rtl_write_dword(rtlpriv, REG_BEQ_TXBD_DESA_8822B + 4,
683 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma >> 32);
684 rtl_write_dword(rtlpriv, REG_BKQ_TXBD_DESA_8822B + 4,
685 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma >> 32);
686 rtl_write_dword(rtlpriv, REG_HI0Q_TXBD_DESA_8822B + 4,
687 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma >> 32);
688
689 rtl_write_dword(rtlpriv, REG_RXQ_RXBD_DESA_8822B + 4,
690 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma >> 32);
691
692 dma64_end:
693 /* Set TX/RX descriptor physical address(from OS API). */
694 rtl_write_dword(rtlpriv, REG_H2CQ_TXBD_DESA_8822B,
695 ((u64)rtlpci->tx_ring[H2C_QUEUE].buffer_desc_dma) &
696 DMA_BIT_MASK(32));
697 rtl_write_dword(rtlpriv, REG_BCNQ_TXBD_DESA_8822B,
698 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
699 DMA_BIT_MASK(32));
700 rtl_write_dword(rtlpriv, REG_MGQ_TXBD_DESA_8822B,
701 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma &
702 DMA_BIT_MASK(32));
703 rtl_write_dword(rtlpriv, REG_VOQ_TXBD_DESA_8822B,
704 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma &
705 DMA_BIT_MASK(32));
706 rtl_write_dword(rtlpriv, REG_VIQ_TXBD_DESA_8822B,
707 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma &
708 DMA_BIT_MASK(32));
709 rtl_write_dword(rtlpriv, REG_BEQ_TXBD_DESA_8822B,
710 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma &
711 DMA_BIT_MASK(32));
712 dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_TXBD_DESA_8822B); /* need? */
713 rtl_write_dword(rtlpriv, REG_BKQ_TXBD_DESA_8822B,
714 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma &
715 DMA_BIT_MASK(32));
716 rtl_write_dword(rtlpriv, REG_HI0Q_TXBD_DESA_8822B,
717 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma &
718 DMA_BIT_MASK(32));
719
720 rtl_write_dword(rtlpriv, REG_RXQ_RXBD_DESA_8822B,
721 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
722 DMA_BIT_MASK(32));
723
724 /* Reset R/W point */
725 rtl_write_dword(rtlpriv, REG_BD_RWPTR_CLR_8822B, 0x3fffffff);
726
727 /* Reset the H2CQ R/W point index to 0 */
728 dwordtmp = rtl_read_dword(rtlpriv, REG_H2CQ_CSR_8822B);
729 rtl_write_dword(rtlpriv, REG_H2CQ_CSR_8822B,
730 (dwordtmp | BIT(8) | BIT(16)));
731
732 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_8822B + 3);
733 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 3, bytetmp | 0xF7);
734
735 rtl_write_dword(rtlpriv, REG_INT_MIG_8822B, 0);
736
737 rtl_write_dword(rtlpriv, REG_MCUTST_I_8822B, 0x0);
738
739 rtl_write_word(rtlpriv, REG_H2CQ_TXBD_NUM_8822B,
740 TX_DESC_NUM_8822B |
741 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
742 rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM_8822B,
743 TX_DESC_NUM_8822B |
744 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
745 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM_8822B,
746 TX_DESC_NUM_8822B |
747 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
748 rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM_8822B,
749 TX_DESC_NUM_8822B |
750 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
751 rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM_8822B,
752 TX_DESC_NUM_8822B |
753 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
754 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM_8822B,
755 TX_DESC_NUM_8822B |
756 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
757 rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM_8822B,
758 TX_DESC_NUM_8822B |
759 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
760 rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM_8822B,
761 TX_DESC_NUM_8822B |
762 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
763 rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM_8822B,
764 TX_DESC_NUM_8822B |
765 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
766 rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM_8822B,
767 TX_DESC_NUM_8822B |
768 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
769 rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM_8822B,
770 TX_DESC_NUM_8822B |
771 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
772 rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM_8822B,
773 TX_DESC_NUM_8822B |
774 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
775 rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM_8822B,
776 TX_DESC_NUM_8822B |
777 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
778 rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM_8822B,
779 TX_DESC_NUM_8822B |
780 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
781 rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM_8822B,
782 TX_DESC_NUM_8822B |
783 ((RTL8822BE_SEG_NUM << 12) & 0x3000));
784 /*Rx*/
785 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM_8822B,
786 RX_DESC_NUM_8822BE |
787 ((RTL8822BE_SEG_NUM << 13) & 0x6000) | 0x8000);
788
789 rtl_write_dword(rtlpriv, REG_BD_RWPTR_CLR_8822B, 0XFFFFFFFF);
790
791 _rtl8822be_gen_refresh_led_state(hw);
792
793 return true;
794 }
795
_rtl8822be_enable_aspm_back_door(struct ieee80211_hw * hw)796 static void _rtl8822be_enable_aspm_back_door(struct ieee80211_hw *hw)
797 {
798 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
799 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
800 u8 tmp;
801
802 if (!ppsc->support_backdoor)
803 return;
804
805 pci_read_config_byte(rtlpci->pdev, 0x70f, &tmp);
806 pci_write_config_byte(rtlpci->pdev, 0x70f, tmp | ASPM_L1_LATENCY << 3);
807
808 pci_read_config_byte(rtlpci->pdev, 0x719, &tmp);
809 pci_write_config_byte(rtlpci->pdev, 0x719, tmp | BIT(3) | BIT(4));
810 }
811
rtl8822be_enable_hw_security_config(struct ieee80211_hw * hw)812 void rtl8822be_enable_hw_security_config(struct ieee80211_hw *hw)
813 {
814 struct rtl_priv *rtlpriv = rtl_priv(hw);
815 u8 sec_reg_value;
816 u8 tmp;
817
818 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
819 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
820 rtlpriv->sec.pairwise_enc_algorithm,
821 rtlpriv->sec.group_enc_algorithm);
822
823 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
824 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
825 "not open hw encryption\n");
826 return;
827 }
828
829 sec_reg_value = SCR_TX_ENC_ENABLE | SRC_RX_DEC_ENABLE;
830
831 if (rtlpriv->sec.use_defaultkey) {
832 sec_reg_value |= SCR_TX_USE_DK;
833 sec_reg_value |= SCR_RX_USE_DK;
834 }
835
836 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
837
838 tmp = rtl_read_byte(rtlpriv, REG_CR_8822B + 1);
839 rtl_write_byte(rtlpriv, REG_CR_8822B + 1, tmp | BIT(1));
840
841 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "The SECR-value %x\n",
842 sec_reg_value);
843
844 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
845 }
846
_rtl8822be_check_pcie_dma_hang(struct rtl_priv * rtlpriv)847 static bool _rtl8822be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
848 {
849 u8 tmp;
850
851 /* write reg 0x350 Bit[26]=1. Enable debug port. */
852 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG_V1_8822B + 3);
853 if (!(tmp & BIT(2))) {
854 rtl_write_byte(rtlpriv, REG_DBI_FLAG_V1_8822B + 3,
855 (tmp | BIT(2)));
856 mdelay(100); /* Suggested by DD Justin_tsai. */
857 }
858
859 /* read reg 0x350 Bit[25] if 1 : RX hang
860 * read reg 0x350 Bit[24] if 1 : TX hang
861 */
862 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG_V1_8822B + 3);
863 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
864 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
865 "CheckPcieDMAHang8822BE(): true!!\n");
866 return true;
867 } else {
868 return false;
869 }
870 }
871
_rtl8822be_reset_pcie_interface_dma(struct rtl_priv * rtlpriv,bool mac_power_on)872 static void _rtl8822be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
873 bool mac_power_on)
874 {
875 u8 tmp;
876 bool release_mac_rx_pause;
877 u8 backup_pcie_dma_pause;
878
879 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
880 "ResetPcieInterfaceDMA8822BE()\n");
881
882 /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
883 * released by SD1 Alan.
884 * 2013.05.07, by tynli.
885 */
886
887 /* 1. disable register write lock
888 * write 0x1C bit[1:0] = 2'h0
889 * write 0xCC bit[2] = 1'b1
890 */
891 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL_8822B);
892 tmp &= ~(BIT(1) | BIT(0));
893 rtl_write_byte(rtlpriv, REG_RSV_CTRL_8822B, tmp);
894 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B);
895 tmp |= BIT(2);
896 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B, tmp);
897
898 /* 2. Check and pause TRX DMA
899 * write 0x284 bit[18] = 1'b1
900 * write 0x301 = 0xFF
901 */
902 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL_8822B);
903 if (tmp & BIT(2)) {
904 /* Already pause before the function for another purpose. */
905 release_mac_rx_pause = false;
906 } else {
907 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL_8822B,
908 (tmp | BIT(2)));
909 release_mac_rx_pause = true;
910 }
911
912 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_8822B + 1);
913 if (backup_pcie_dma_pause != 0xFF)
914 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 1, 0xFF);
915
916 if (mac_power_on) {
917 /* 3. reset TRX function
918 * write 0x100 = 0x00
919 */
920 rtl_write_byte(rtlpriv, REG_CR_8822B, 0);
921 }
922
923 /* 4. Reset PCIe DMA
924 * write 0x003 bit[0] = 0
925 */
926 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1);
927 tmp &= ~(BIT(0));
928 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1, tmp);
929
930 /* 5. Enable PCIe DMA
931 * write 0x003 bit[0] = 1
932 */
933 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1);
934 tmp |= BIT(0);
935 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN_8822B + 1, tmp);
936
937 if (mac_power_on) {
938 /* 6. enable TRX function
939 * write 0x100 = 0xFF
940 */
941 rtl_write_byte(rtlpriv, REG_CR_8822B, 0xFF);
942
943 /* We should init LLT & RQPN and
944 * prepare Tx/Rx descrptor address later
945 * because MAC function is reset.
946 */
947 }
948
949 /* 7. Restore PCIe autoload down bit
950 * write 0xF8 bit[17] = 1'b1
951 */
952 tmp = rtl_read_byte(rtlpriv, REG_SYS_STATUS2_8822B + 2);
953 tmp |= BIT(1);
954 rtl_write_byte(rtlpriv, REG_SYS_STATUS2_8822B + 2, tmp);
955
956 /* In MAC power on state, BB and RF maybe in ON state,
957 * if we release TRx DMA here
958 * it will cause packets to be started to Tx/Rx,
959 * so we release Tx/Rx DMA later.
960 */
961 if (!mac_power_on) {
962 /* 8. release TRX DMA
963 * write 0x284 bit[18] = 1'b0
964 * write 0x301 = 0x00
965 */
966 if (release_mac_rx_pause) {
967 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL_8822B);
968 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL_8822B,
969 (tmp & (~BIT(2))));
970 }
971 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 1,
972 backup_pcie_dma_pause);
973 }
974
975 /* 9. lock system register
976 * write 0xCC bit[2] = 1'b0
977 */
978 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B);
979 tmp &= ~(BIT(2));
980 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2_8822B, tmp);
981 }
982
rtl8822be_hw_init(struct ieee80211_hw * hw)983 int rtl8822be_hw_init(struct ieee80211_hw *hw)
984 {
985 struct rtl_priv *rtlpriv = rtl_priv(hw);
986 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
987 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
988 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
989 struct rtl_phy *rtlphy = &rtlpriv->phy;
990 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
991 int err = 0;
992 u8 tmp_u1b;
993
994 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8822BE hw init\n");
995 rtlpriv->rtlhal.being_init_adapter = true;
996 rtlpriv->intf_ops->disable_aspm(hw);
997
998 if (_rtl8822be_check_pcie_dma_hang(rtlpriv)) {
999 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "8822be dma hang!\n");
1000 _rtl8822be_reset_pcie_interface_dma(rtlpriv,
1001 rtlhal->mac_func_enable);
1002 rtlhal->mac_func_enable = false;
1003 }
1004
1005 /* init TRX BD */
1006 _rtl8822be_init_trxbd(hw);
1007
1008 /* use halmac to init */
1009 err = rtlpriv->halmac.ops->halmac_init_hal(rtlpriv);
1010 if (err) {
1011 pr_err("halmac_init_hal failed\n");
1012 rtlhal->fw_ready = false;
1013 return err;
1014 }
1015
1016 rtlhal->fw_ready = true;
1017
1018 /* have to init after halmac init */
1019 tmp_u1b = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_8822B + 2);
1020 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_8822B + 2, (tmp_u1b | BIT(4)));
1021
1022 /*rtl_write_word(rtlpriv, REG_PCIE_CTRL_8822B, 0x8000);*/
1023 rtlhal->rx_tag = 0;
1024
1025 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ_8822B, 0x4);
1026
1027 /*fw related variable initialize */
1028 ppsc->fw_current_inpsmode = false;
1029 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8822B;
1030 rtlhal->fw_clk_change_in_progress = false;
1031 rtlhal->allow_sw_to_change_hwclc = false;
1032 rtlhal->last_hmeboxnum = 0;
1033
1034 rtlphy->rfreg_chnlval[0] =
1035 rtl_get_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK);
1036 rtlphy->rfreg_chnlval[1] =
1037 rtl_get_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK);
1038 rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
1039 RFREG_OFFSET_MASK);
1040 rtlphy->rfreg_chnlval[0] =
1041 (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) | BIT(10) | BIT(11);
1042
1043 rtlhal->mac_func_enable = true;
1044
1045 if (rtlpriv->cfg->ops->get_btc_status())
1046 rtlpriv->btcoexist.btc_ops->btc_power_on_setting(rtlpriv);
1047
1048 /* reset cam / set security */
1049 rtl_cam_reset_all_entry(hw);
1050 rtl8822be_enable_hw_security_config(hw);
1051
1052 /* check RCR/ICV bit */
1053 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1054 rtl_write_dword(rtlpriv, REG_RCR_8822B, rtlpci->receive_config);
1055
1056 /* clear rx ctrl frame */
1057 rtl_write_word(rtlpriv, REG_RXFLTMAP1_8822B, 0);
1058
1059 ppsc->rfpwr_state = ERFON;
1060
1061 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1062 _rtl8822be_enable_aspm_back_door(hw);
1063 rtlpriv->intf_ops->enable_aspm(hw);
1064
1065 if (rtlpriv->cfg->ops->get_btc_status())
1066 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
1067 else
1068 rtlpriv->btcoexist.btc_ops->btc_init_hw_config_wifi_only(
1069 rtlpriv);
1070
1071 rtlpriv->rtlhal.being_init_adapter = false;
1072
1073 rtlpriv->phydm.ops->phydm_init_dm(rtlpriv);
1074
1075 /* clear ISR, and IMR will be on later */
1076 rtl_write_dword(rtlpriv, REG_HISR0_8822B,
1077 rtl_read_dword(rtlpriv, REG_HISR0_8822B));
1078
1079 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "end of Rtl8822BE hw init %x\n",
1080 err);
1081 return 0;
1082 }
1083
_rtl8822be_read_chip_version(struct ieee80211_hw * hw)1084 static u32 _rtl8822be_read_chip_version(struct ieee80211_hw *hw)
1085 {
1086 struct rtl_priv *rtlpriv = rtl_priv(hw);
1087 struct rtl_phy *rtlphy = &rtlpriv->phy;
1088 /*enum version_8822b version = VERSION_UNKNOWN;*/
1089 u32 version;
1090 u32 value32;
1091
1092 rtlphy->rf_type = RF_2T2R;
1093
1094 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1_8822B);
1095
1096 version = value32;
1097
1098 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1099 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
1100
1101 return version;
1102 }
1103
_rtl8822be_set_media_status(struct ieee80211_hw * hw,enum nl80211_iftype type)1104 static int _rtl8822be_set_media_status(struct ieee80211_hw *hw,
1105 enum nl80211_iftype type)
1106 {
1107 struct rtl_priv *rtlpriv = rtl_priv(hw);
1108 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1109 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1110 u8 mode = MSR_NOLINK;
1111
1112 bt_msr &= 0xfc;
1113
1114 switch (type) {
1115 case NL80211_IFTYPE_UNSPECIFIED:
1116 mode = MSR_NOLINK;
1117 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1118 "Set Network type to NO LINK!\n");
1119 break;
1120 case NL80211_IFTYPE_ADHOC:
1121 case NL80211_IFTYPE_MESH_POINT:
1122 mode = MSR_ADHOC;
1123 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1124 "Set Network type to Ad Hoc!\n");
1125 break;
1126 case NL80211_IFTYPE_STATION:
1127 mode = MSR_INFRA;
1128 ledaction = LED_CTL_LINK;
1129 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1130 "Set Network type to STA!\n");
1131 break;
1132 case NL80211_IFTYPE_AP:
1133 mode = MSR_AP;
1134 ledaction = LED_CTL_LINK;
1135 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1136 "Set Network type to AP!\n");
1137 break;
1138 default:
1139 pr_err("Network type %d not support!\n", type);
1140 return 1;
1141 }
1142
1143 /* MSR_INFRA == Link in infrastructure network;
1144 * MSR_ADHOC == Link in ad hoc network;
1145 * Therefore, check link state is necessary.
1146 *
1147 * MSR_AP == AP mode; link state is not cared here.
1148 */
1149 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1150 mode = MSR_NOLINK;
1151 ledaction = LED_CTL_NO_LINK;
1152 }
1153
1154 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1155 _rtl8822be_stop_tx_beacon(hw);
1156 _rtl8822be_enable_bcn_sub_func(hw);
1157 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1158 _rtl8822be_resume_tx_beacon(hw);
1159 _rtl8822be_disable_bcn_sub_func(hw);
1160 } else {
1161 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1162 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1163 mode);
1164 }
1165
1166 rtl_write_byte(rtlpriv, (MSR), bt_msr | mode);
1167 rtlpriv->cfg->ops->led_control(hw, ledaction);
1168 if (mode == MSR_AP)
1169 rtl_write_byte(rtlpriv, REG_BCNTCFG_8822B + 1, 0x00);
1170 else
1171 rtl_write_byte(rtlpriv, REG_BCNTCFG_8822B + 1, 0x66);
1172 return 0;
1173 }
1174
rtl8822be_set_check_bssid(struct ieee80211_hw * hw,bool check_bssid)1175 void rtl8822be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1176 {
1177 struct rtl_priv *rtlpriv = rtl_priv(hw);
1178 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1179 u32 reg_rcr = rtlpci->receive_config;
1180
1181 if (rtlpriv->psc.rfpwr_state != ERFON)
1182 return;
1183
1184 if (check_bssid) {
1185 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1186 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1187 _rtl8822be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1188 } else if (!check_bssid) {
1189 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1190 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1191 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1192 }
1193 }
1194
rtl8822be_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)1195 int rtl8822be_set_network_type(struct ieee80211_hw *hw,
1196 enum nl80211_iftype type)
1197 {
1198 struct rtl_priv *rtlpriv = rtl_priv(hw);
1199
1200 if (_rtl8822be_set_media_status(hw, type))
1201 return -EOPNOTSUPP;
1202
1203 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1204 if (type != NL80211_IFTYPE_AP &&
1205 type != NL80211_IFTYPE_MESH_POINT)
1206 rtl8822be_set_check_bssid(hw, true);
1207 } else {
1208 rtl8822be_set_check_bssid(hw, false);
1209 }
1210
1211 return 0;
1212 }
1213
rtl8822be_set_qos(struct ieee80211_hw * hw,int aci)1214 void rtl8822be_set_qos(struct ieee80211_hw *hw, int aci)
1215 {
1216 struct rtl_priv *rtlpriv = rtl_priv(hw);
1217 struct rtl_mac *mac = rtl_mac(rtlpriv);
1218 u32 ac_param;
1219
1220 ac_param = rtl_get_hal_edca_param(hw, mac->vif, mac->mode,
1221 &mac->edca_param[aci]);
1222
1223 switch (aci) {
1224 case AC1_BK:
1225 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM_8822B, ac_param);
1226 break;
1227 case AC0_BE:
1228 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM_8822B, ac_param);
1229 break;
1230 case AC2_VI:
1231 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM_8822B, ac_param);
1232 break;
1233 case AC3_VO:
1234 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM_8822B, ac_param);
1235 break;
1236 default:
1237 WARN_ONCE(true, "invalid aci: %d !\n", aci);
1238 break;
1239 }
1240 }
1241
rtl8822be_enable_interrupt(struct ieee80211_hw * hw)1242 void rtl8822be_enable_interrupt(struct ieee80211_hw *hw)
1243 {
1244 struct rtl_priv *rtlpriv = rtl_priv(hw);
1245 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1246
1247 rtl_write_dword(rtlpriv, REG_HIMR0_8822B,
1248 rtlpci->irq_mask[0] & 0xFFFFFFFF);
1249 rtl_write_dword(rtlpriv, REG_HIMR1_8822B,
1250 rtlpci->irq_mask[1] & 0xFFFFFFFF);
1251 rtl_write_dword(rtlpriv, REG_HIMR3_8822B,
1252 rtlpci->irq_mask[3] & 0xFFFFFFFF);
1253 rtlpci->irq_enabled = true;
1254 }
1255
rtl8822be_disable_interrupt(struct ieee80211_hw * hw)1256 void rtl8822be_disable_interrupt(struct ieee80211_hw *hw)
1257 {
1258 struct rtl_priv *rtlpriv = rtl_priv(hw);
1259 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1260
1261 rtl_write_dword(rtlpriv, REG_HIMR0_8822B, IMR_DISABLED);
1262 rtl_write_dword(rtlpriv, REG_HIMR1_8822B, IMR_DISABLED);
1263 rtl_write_dword(rtlpriv, REG_HIMR3_8822B, IMR_DISABLED);
1264 rtlpci->irq_enabled = false;
1265 /*synchronize_irq(rtlpci->pdev->irq);*/
1266 }
1267
rtl8822be_card_disable(struct ieee80211_hw * hw)1268 void rtl8822be_card_disable(struct ieee80211_hw *hw)
1269 {
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1272 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1273 enum nl80211_iftype opmode;
1274
1275 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8822be card disable\n");
1276
1277 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1278
1279 mac->link_state = MAC80211_NOLINK;
1280 opmode = NL80211_IFTYPE_UNSPECIFIED;
1281
1282 _rtl8822be_set_media_status(hw, opmode);
1283
1284 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1285 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1286 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1287
1288 rtlpriv->phydm.ops->phydm_deinit_dm(rtlpriv);
1289
1290 rtlpriv->halmac.ops->halmac_deinit_hal(rtlpriv);
1291
1292 /* after power off we should do iqk again */
1293 if (!rtlpriv->cfg->ops->get_btc_status())
1294 rtlpriv->phy.iqk_initialized = false;
1295 }
1296
rtl8822be_interrupt_recognized(struct ieee80211_hw * hw,u32 * p_inta,u32 * p_intb,u32 * p_intc,u32 * p_intd)1297 void rtl8822be_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1298 u32 *p_intb, u32 *p_intc, u32 *p_intd)
1299 {
1300 struct rtl_priv *rtlpriv = rtl_priv(hw);
1301 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1302
1303 *p_inta =
1304 rtl_read_dword(rtlpriv, REG_HISR0_8822B) & rtlpci->irq_mask[0];
1305 rtl_write_dword(rtlpriv, REG_HISR0_8822B, *p_inta);
1306
1307 *p_intb =
1308 rtl_read_dword(rtlpriv, REG_HISR1_8822B) & rtlpci->irq_mask[1];
1309 rtl_write_dword(rtlpriv, REG_HISR1_8822B, *p_intb);
1310
1311 *p_intd =
1312 rtl_read_dword(rtlpriv, REG_HISR3_8822B) & rtlpci->irq_mask[3];
1313 rtl_write_dword(rtlpriv, REG_HISR3_8822B, *p_intd);
1314 }
1315
rtl8822be_set_beacon_related_registers(struct ieee80211_hw * hw)1316 void rtl8822be_set_beacon_related_registers(struct ieee80211_hw *hw)
1317 {
1318 struct rtl_priv *rtlpriv = rtl_priv(hw);
1319 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1320 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1321 u16 bcn_interval, atim_window;
1322
1323 bcn_interval = mac->beacon_interval;
1324 atim_window = 2; /*FIX MERGE */
1325 rtl8822be_disable_interrupt(hw);
1326 rtl_write_word(rtlpriv, REG_ATIMWND_8822B, atim_window);
1327 rtl_write_word(rtlpriv, REG_MBSSID_BCN_SPACE_8822B, bcn_interval);
1328 rtl_write_word(rtlpriv, REG_BCNTCFG_8822B, 0x660f);
1329 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK_8822B, 0x18);
1330 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM_8822B, 0x18);
1331 rtl_write_byte(rtlpriv, 0x606, 0x30);
1332 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1333 rtl_write_byte(rtlpriv, REG_BCN_CTRL_8822B,
1334 (u8)rtlpci->reg_bcn_ctrl_val);
1335 }
1336
rtl8822be_set_beacon_interval(struct ieee80211_hw * hw)1337 void rtl8822be_set_beacon_interval(struct ieee80211_hw *hw)
1338 {
1339 struct rtl_priv *rtlpriv = rtl_priv(hw);
1340 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1341 u16 bcn_interval = mac->beacon_interval;
1342
1343 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1344 bcn_interval);
1345 rtl_write_word(rtlpriv, REG_MBSSID_BCN_SPACE_8822B, bcn_interval);
1346 }
1347
rtl8822be_update_interrupt_mask(struct ieee80211_hw * hw,u32 add_msr,u32 rm_msr)1348 void rtl8822be_update_interrupt_mask(struct ieee80211_hw *hw, u32 add_msr,
1349 u32 rm_msr)
1350 {
1351 struct rtl_priv *rtlpriv = rtl_priv(hw);
1352 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1353
1354 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1355 add_msr, rm_msr);
1356
1357 if (add_msr)
1358 rtlpci->irq_mask[0] |= add_msr;
1359 if (rm_msr)
1360 rtlpci->irq_mask[0] &= (~rm_msr);
1361 rtl8822be_disable_interrupt(hw);
1362 rtl8822be_enable_interrupt(hw);
1363 }
1364
_rtl8822be_get_chnl_group(u8 chnl,u8 * group)1365 static bool _rtl8822be_get_chnl_group(u8 chnl, u8 *group)
1366 {
1367 bool in_24g;
1368
1369 if (chnl <= 14) {
1370 in_24g = true;
1371
1372 if (chnl >= 1 && chnl <= 2)
1373 *group = 0;
1374 else if (chnl >= 3 && chnl <= 5)
1375 *group = 1;
1376 else if (chnl >= 6 && chnl <= 8)
1377 *group = 2;
1378 else if (chnl >= 9 && chnl <= 11)
1379 *group = 3;
1380 else if (chnl >= 12 && chnl <= 14)
1381 *group = 4;
1382 } else {
1383 in_24g = false;
1384
1385 if (chnl >= 36 && chnl <= 42)
1386 *group = 0;
1387 else if (chnl >= 44 && chnl <= 48)
1388 *group = 1;
1389 else if (chnl >= 50 && chnl <= 58)
1390 *group = 2;
1391 else if (chnl >= 60 && chnl <= 64)
1392 *group = 3;
1393 else if (chnl >= 100 && chnl <= 106)
1394 *group = 4;
1395 else if (chnl >= 108 && chnl <= 114)
1396 *group = 5;
1397 else if (chnl >= 116 && chnl <= 122)
1398 *group = 6;
1399 else if (chnl >= 124 && chnl <= 130)
1400 *group = 7;
1401 else if (chnl >= 132 && chnl <= 138)
1402 *group = 8;
1403 else if (chnl >= 140 && chnl <= 144)
1404 *group = 9;
1405 else if (chnl >= 149 && chnl <= 155)
1406 *group = 10;
1407 else if (chnl >= 157 && chnl <= 161)
1408 *group = 11;
1409 else if (chnl >= 165 && chnl <= 171)
1410 *group = 12;
1411 else if (chnl >= 173 && chnl <= 177)
1412 *group = 13;
1413 }
1414 return in_24g;
1415 }
1416
power_valid(u8 power)1417 static inline bool power_valid(u8 power)
1418 {
1419 if (power <= 63)
1420 return true;
1421
1422 return false;
1423 }
1424
power_diff(s8 diff)1425 static inline s8 power_diff(s8 diff)
1426 {
1427 /* bit sign number to 8 bit sign number */
1428 if (diff & BIT(3))
1429 diff |= 0xF0;
1430
1431 return diff;
1432 }
1433
_rtl8822be_read_power_value_fromprom(struct ieee80211_hw * hw,struct txpower_info_2g * pwr2g,struct txpower_info_5g * pwr5g,bool autoload_fail,u8 * hwinfo)1434 static void _rtl8822be_read_power_value_fromprom(struct ieee80211_hw *hw,
1435 struct txpower_info_2g *pwr2g,
1436 struct txpower_info_5g *pwr5g,
1437 bool autoload_fail, u8 *hwinfo)
1438 {
1439 struct rtl_priv *rtlpriv = rtl_priv(hw);
1440 u32 rf, addr = EEPROM_TX_PWR_INX_8822B, group, i = 0;
1441 u8 power;
1442 s8 diff;
1443
1444 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1445 "hal_ReadPowerValueFromPROM8822B(): PROMContent[0x%x]=0x%x\n",
1446 (addr + 1), hwinfo[addr + 1]);
1447 if (hwinfo[addr + 1] == 0xFF) /*YJ,add,120316*/
1448 autoload_fail = true;
1449
1450 memset(pwr2g, 0, sizeof(struct txpower_info_2g));
1451 memset(pwr5g, 0, sizeof(struct txpower_info_5g));
1452
1453 if (autoload_fail) {
1454 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1455 "auto load fail : Use Default value!\n");
1456 for (rf = 0; rf < MAX_RF_PATH; rf++) {
1457 /* 2.4G default value */
1458 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1459 pwr2g->index_cck_base[rf][group] = 0x2D;
1460 pwr2g->index_bw40_base[rf][group] = 0x2D;
1461 }
1462 for (i = 0; i < MAX_TX_COUNT; i++) {
1463 if (i == 0) {
1464 pwr2g->bw20_diff[rf][0] = 0x02;
1465 pwr2g->ofdm_diff[rf][0] = 0x04;
1466 } else {
1467 pwr2g->bw20_diff[rf][i] = 0xFE;
1468 pwr2g->bw40_diff[rf][i] = 0xFE;
1469 pwr2g->cck_diff[rf][i] = 0xFE;
1470 pwr2g->ofdm_diff[rf][i] = 0xFE;
1471 }
1472 }
1473
1474 /*5G default value*/
1475 for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
1476 pwr5g->index_bw40_base[rf][group] = 0x2A;
1477
1478 for (i = 0; i < MAX_TX_COUNT; i++) {
1479 if (i == 0) {
1480 pwr5g->ofdm_diff[rf][0] = 0x04;
1481 pwr5g->bw20_diff[rf][0] = 0x00;
1482 pwr5g->bw80_diff[rf][0] = 0xFE;
1483 pwr5g->bw160_diff[rf][0] = 0xFE;
1484 } else {
1485 pwr5g->ofdm_diff[rf][i] = 0xFE;
1486 pwr5g->bw20_diff[rf][i] = 0xFE;
1487 pwr5g->bw40_diff[rf][i] = 0xFE;
1488 pwr5g->bw80_diff[rf][i] = 0xFE;
1489 pwr5g->bw160_diff[rf][i] = 0xFE;
1490 }
1491 }
1492 }
1493 return;
1494 }
1495
1496 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
1497
1498 for (rf = 0; rf < 2 /*MAX_RF_PATH*/; rf++) {
1499 /*2.4G default value*/
1500 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1501 power = hwinfo[addr++];
1502 if (power_valid(power))
1503 pwr2g->index_cck_base[rf][group] = power;
1504 }
1505 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1506 power = hwinfo[addr++];
1507 if (power_valid(power))
1508 pwr2g->index_bw40_base[rf][group] = power;
1509 }
1510 for (i = 0; i < MAX_TX_COUNT; i++) {
1511 if (i == 0) {
1512 pwr2g->bw40_diff[rf][i] = 0;
1513
1514 diff = (hwinfo[addr] & 0xF0) >> 4;
1515 pwr2g->bw20_diff[rf][i] = power_diff(diff);
1516
1517 diff = hwinfo[addr] & 0x0F;
1518 pwr2g->ofdm_diff[rf][i] = power_diff(diff);
1519
1520 pwr2g->cck_diff[rf][i] = 0;
1521
1522 addr++;
1523 } else {
1524 diff = (hwinfo[addr] & 0xF0) >> 4;
1525 pwr2g->bw40_diff[rf][i] = power_diff(diff);
1526
1527 diff = hwinfo[addr] & 0x0F;
1528 pwr2g->bw20_diff[rf][i] = power_diff(diff);
1529
1530 addr++;
1531
1532 diff = (hwinfo[addr] & 0xF0) >> 4;
1533 pwr2g->ofdm_diff[rf][i] = power_diff(diff);
1534
1535 diff = hwinfo[addr] & 0x0F;
1536 pwr2g->cck_diff[rf][i] = power_diff(diff);
1537
1538 addr++;
1539 }
1540 }
1541
1542 /*5G default value*/
1543 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1544 power = hwinfo[addr++];
1545 if (power_valid(power))
1546 pwr5g->index_bw40_base[rf][group] = power;
1547 }
1548
1549 for (i = 0; i < MAX_TX_COUNT; i++) {
1550 if (i == 0) {
1551 pwr5g->bw40_diff[rf][i] = 0;
1552
1553 diff = (hwinfo[addr] & 0xF0) >> 4;
1554 pwr5g->bw20_diff[rf][i] = power_diff(diff);
1555
1556 diff = hwinfo[addr] & 0x0F;
1557 pwr5g->ofdm_diff[rf][i] = power_diff(diff);
1558
1559 addr++;
1560 } else {
1561 diff = (hwinfo[addr] & 0xF0) >> 4;
1562 pwr5g->bw40_diff[rf][i] = power_diff(diff);
1563
1564 diff = hwinfo[addr] & 0x0F;
1565 pwr5g->bw20_diff[rf][i] = power_diff(diff);
1566
1567 addr++;
1568 }
1569 }
1570
1571 diff = (hwinfo[addr] & 0xF0) >> 4;
1572 pwr5g->ofdm_diff[rf][1] = power_diff(diff);
1573
1574 diff = hwinfo[addr] & 0x0F;
1575 pwr5g->ofdm_diff[rf][2] = power_diff(diff);
1576
1577 addr++;
1578
1579 diff = hwinfo[addr] & 0x0F;
1580 pwr5g->ofdm_diff[rf][3] = power_diff(diff);
1581
1582 addr++;
1583
1584 for (i = 0; i < MAX_TX_COUNT; i++) {
1585 diff = (hwinfo[addr] & 0xF0) >> 4;
1586 pwr5g->bw80_diff[rf][i] = power_diff(diff);
1587
1588 diff = hwinfo[addr] & 0x0F;
1589 pwr5g->bw160_diff[rf][i] = power_diff(diff);
1590
1591 addr++;
1592 }
1593 }
1594 }
1595
_rtl8822be_read_txpower_info_from_hwpg(struct ieee80211_hw * hw,bool autoload_fail,u8 * hwinfo)1596 static void _rtl8822be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1597 bool autoload_fail,
1598 u8 *hwinfo)
1599 {
1600 struct rtl_priv *rtlpriv = rtl_priv(hw);
1601 struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw));
1602 struct txpower_info_2g pwr2g;
1603 struct txpower_info_5g pwr5g;
1604 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
1605 36, 38, 40, 42, 44, 46, 48, /* Band 1 */
1606 52, 54, 56, 58, 60, 62, 64, /* Band 2 */
1607 100, 102, 104, 106, 108, 110, 112, /* Band 3 */
1608 116, 118, 120, 122, 124, 126, 128, /* Band 3 */
1609 132, 134, 136, 138, 140, 142, 144, /* Band 3 */
1610 149, 151, 153, 155, 157, 159, 161, /* Band 4 */
1611 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
1612 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122,
1613 138, 155, 171};
1614 u8 rf, group;
1615 u8 i;
1616
1617 _rtl8822be_read_power_value_fromprom(hw, &pwr2g, &pwr5g, autoload_fail,
1618 hwinfo);
1619
1620 for (rf = 0; rf < MAX_RF_PATH; rf++) {
1621 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
1622 _rtl8822be_get_chnl_group(i + 1, &group);
1623
1624 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
1625 efu->txpwrlevel_cck[rf][i] =
1626 pwr2g.index_cck_base[rf][5];
1627 efu->txpwrlevel_ht40_1s[rf][i] =
1628 pwr2g.index_bw40_base[rf][group];
1629 } else {
1630 efu->txpwrlevel_cck[rf][i] =
1631 pwr2g.index_cck_base[rf][group];
1632 efu->txpwrlevel_ht40_1s[rf][i] =
1633 pwr2g.index_bw40_base[rf][group];
1634 }
1635 }
1636 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
1637 _rtl8822be_get_chnl_group(channel5g[i], &group);
1638 efu->txpwr_5g_bw40base[rf][i] =
1639 pwr5g.index_bw40_base[rf][group];
1640 }
1641 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
1642 u8 upper, lower;
1643
1644 _rtl8822be_get_chnl_group(channel5g_80m[i], &group);
1645 upper = pwr5g.index_bw40_base[rf][group];
1646 lower = pwr5g.index_bw40_base[rf][group + 1];
1647
1648 efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;
1649 }
1650 for (i = 0; i < MAX_TX_COUNT; i++) {
1651 efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i];
1652 efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i];
1653 efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i];
1654 efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i];
1655
1656 efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i];
1657 efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i];
1658 efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i];
1659 efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i];
1660 }
1661 }
1662
1663 if (!autoload_fail)
1664 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_8822B];
1665 else
1666 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1667
1668 if (efu->eeprom_thermalmeter == 0xff || autoload_fail) {
1669 efu->apk_thermalmeterignore = true;
1670 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1671 }
1672
1673 efu->thermalmeter[0] = efu->eeprom_thermalmeter;
1674 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "thermalmeter = 0x%x\n",
1675 efu->eeprom_thermalmeter);
1676
1677 if (!autoload_fail) {
1678 efu->eeprom_regulatory =
1679 hwinfo[EEPROM_RF_BOARD_OPTION_8822B] & 0x07;
1680 if (hwinfo[EEPROM_RF_BOARD_OPTION_8822B] == 0xFF)
1681 efu->eeprom_regulatory = 0;
1682 } else {
1683 efu->eeprom_regulatory = 0;
1684 }
1685 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "eeprom_regulatory = 0x%x\n",
1686 efu->eeprom_regulatory);
1687 }
1688
_rtl8822be_read_pa_type(struct ieee80211_hw * hw,u8 * hwinfo,bool autoload_fail)1689 static void _rtl8822be_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
1690 bool autoload_fail)
1691 {
1692 struct rtl_priv *rtlpriv = rtl_priv(hw);
1693 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1694
1695 if (!autoload_fail) {
1696 rtlhal->pa_type_2g = hwinfo[EEPROM_2G_5G_PA_TYPE_8822B];
1697 rtlhal->lna_type_2g =
1698 hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B];
1699 if (rtlhal->pa_type_2g == 0xFF)
1700 rtlhal->pa_type_2g = 0;
1701 if (rtlhal->lna_type_2g == 0xFF)
1702 rtlhal->lna_type_2g = 0;
1703
1704 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(4)) ? 1 : 0;
1705 rtlhal->external_lna_2g =
1706 (rtlhal->lna_type_2g & BIT(3)) ? 1 : 0;
1707
1708 rtlhal->pa_type_5g = hwinfo[EEPROM_2G_5G_PA_TYPE_8822B];
1709 rtlhal->lna_type_5g =
1710 hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B];
1711 if (rtlhal->pa_type_5g == 0xFF)
1712 rtlhal->pa_type_5g = 0;
1713 if (rtlhal->lna_type_5g == 0xFF)
1714 rtlhal->lna_type_5g = 0;
1715
1716 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(0)) ? 1 : 0;
1717 rtlhal->external_lna_5g =
1718 (rtlhal->lna_type_5g & BIT(3)) ? 1 : 0;
1719 } else {
1720 rtlhal->external_pa_2g = 0;
1721 rtlhal->external_lna_2g = 0;
1722 rtlhal->external_pa_5g = 0;
1723 rtlhal->external_lna_5g = 0;
1724 }
1725 }
1726
_rtl8822be_read_amplifier_type(struct ieee80211_hw * hw,u8 * hwinfo,bool autoload_fail)1727 static void _rtl8822be_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo,
1728 bool autoload_fail)
1729 {
1730 struct rtl_priv *rtlpriv = rtl_priv(hw);
1731 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1732
1733 u8 ext_type_pa_2g_a =
1734 (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(2)) >>
1735 2; /* 0xBD[2] */
1736 u8 ext_type_pa_2g_b =
1737 (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(6)) >>
1738 6; /* 0xBD[6] */
1739 u8 ext_type_pa_5g_a =
1740 (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(2)) >>
1741 2; /* 0xBF[2] */
1742 u8 ext_type_pa_5g_b =
1743 (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT(6)) >>
1744 6; /* 0xBF[6] */
1745 u8 ext_type_lna_2g_a = (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] &
1746 (BIT(1) | BIT(0))) >>
1747 0; /* 0xBD[1:0] */
1748 u8 ext_type_lna_2g_b = (hwinfo[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] &
1749 (BIT(5) | BIT(4))) >>
1750 4; /* 0xBD[5:4] */
1751 u8 ext_type_lna_5g_a = (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] &
1752 (BIT(1) | BIT(0))) >>
1753 0; /* 0xBF[1:0] */
1754 u8 ext_type_lna_5g_b = (hwinfo[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] &
1755 (BIT(5) | BIT(4))) >>
1756 4; /* 0xBF[5:4] */
1757
1758 _rtl8822be_read_pa_type(hw, hwinfo, autoload_fail);
1759
1760 /* [2.4G] Path A and B are both extPA */
1761 if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4)))
1762 rtlhal->type_gpa = ext_type_pa_2g_b << 2 | ext_type_pa_2g_a;
1763
1764 /* [5G] Path A and B are both extPA */
1765 if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0)))
1766 rtlhal->type_apa = ext_type_pa_5g_b << 2 | ext_type_pa_5g_a;
1767
1768 /* [2.4G] Path A and B are both extLNA */
1769 if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
1770 rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a;
1771
1772 /* [5G] Path A and B are both extLNA */
1773 if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
1774 rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a;
1775 }
1776
_rtl8822be_read_rfe_type(struct ieee80211_hw * hw,u8 * hwinfo,bool autoload_fail)1777 static void _rtl8822be_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
1778 bool autoload_fail)
1779 {
1780 struct rtl_priv *rtlpriv = rtl_priv(hw);
1781 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1782
1783 if (!autoload_fail)
1784 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION_8822B];
1785 else
1786 rtlhal->rfe_type = 0;
1787
1788 if (rtlhal->rfe_type == 0xFF)
1789 rtlhal->rfe_type = 0;
1790
1791 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RFE Type: 0x%2x\n",
1792 rtlhal->rfe_type);
1793 }
1794
_rtl8822be_read_adapter_info(struct ieee80211_hw * hw)1795 static void _rtl8822be_read_adapter_info(struct ieee80211_hw *hw)
1796 {
1797 struct rtl_priv *rtlpriv = rtl_priv(hw);
1798 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1799 struct rtl_halmac_ops *halmac_ops = rtlpriv->halmac.ops;
1800 u16 i, usvalue;
1801 u8 *hwinfo;
1802 u16 eeprom_id;
1803 u32 efuse_size;
1804 int err;
1805
1806 if (rtlefuse->epromtype != EEPROM_BOOT_EFUSE) {
1807 pr_err("RTL8822B Not boot from efuse!!");
1808 return;
1809 }
1810
1811 /* read logical efuse size (normalely, 0x0300) */
1812 err = halmac_ops->halmac_get_logical_efuse_size(rtlpriv, &efuse_size);
1813
1814 if (err || !efuse_size) {
1815 pr_err("halmac_get_logical_efuse_size err=%d efuse_size=0x%X",
1816 err, efuse_size);
1817 efuse_size = HWSET_MAX_SIZE;
1818 }
1819
1820 if (efuse_size > HWSET_MAX_SIZE) {
1821 pr_err("halmac_get_logical_efuse_size efuse_size=0x%X > 0x%X",
1822 efuse_size, HWSET_MAX_SIZE);
1823 efuse_size = HWSET_MAX_SIZE;
1824 }
1825
1826 /* read efuse */
1827 hwinfo = kzalloc(efuse_size, GFP_KERNEL);
1828
1829 err = halmac_ops->halmac_read_logical_efuse_map(rtlpriv, hwinfo,
1830 efuse_size);
1831 if (err) {
1832 pr_err("%s: <ERROR> fail to get efuse map!\n", __func__);
1833 goto label_end;
1834 }
1835
1836 /* copy to efuse_map (need?) */
1837 memcpy(&rtlefuse->efuse_map[EFUSE_INIT_MAP][0], hwinfo,
1838 EFUSE_MAX_LOGICAL_SIZE);
1839 memcpy(&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0], hwinfo,
1840 EFUSE_MAX_LOGICAL_SIZE);
1841
1842 /* parse content */
1843 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n", hwinfo,
1844 HWSET_MAX_SIZE);
1845
1846 eeprom_id = *((u16 *)&hwinfo[0]);
1847 if (eeprom_id != RTL8822B_EEPROM_ID) {
1848 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1849 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1850 rtlefuse->autoload_failflag = true;
1851 } else {
1852 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1853 rtlefuse->autoload_failflag = false;
1854 }
1855
1856 if (rtlefuse->autoload_failflag)
1857 goto label_end;
1858
1859 /*VID DID SVID SDID*/
1860 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1861 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1862 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1863 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1864 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
1865 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM VID = 0x%4x\n",
1866 rtlefuse->eeprom_vid);
1867 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM DID = 0x%4x\n",
1868 rtlefuse->eeprom_did);
1869 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM SVID = 0x%4x\n",
1870 rtlefuse->eeprom_svid);
1871 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM SMID = 0x%4x\n",
1872 rtlefuse->eeprom_smid);
1873 /*customer ID*/
1874 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOM_ID_8822B];
1875 if (rtlefuse->eeprom_oemid == 0xFF)
1876 rtlefuse->eeprom_oemid = 0;
1877
1878 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
1879 rtlefuse->eeprom_oemid);
1880 /*EEPROM version*/
1881 rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION_8822B];
1882 /*mac address*/
1883 for (i = 0; i < 6; i += 2) {
1884 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_8822BE + i];
1885 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
1886 }
1887
1888 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "dev_addr: %pM\n",
1889 rtlefuse->dev_addr);
1890
1891 /* channel plan */
1892 rtlefuse->eeprom_channelplan =
1893 *(u8 *)&hwinfo[EEPROM_CHANNEL_PLAN_8822B];
1894
1895 /* set channel plan from efuse */
1896 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
1897 if (rtlefuse->channel_plan == 0xFF)
1898 rtlefuse->channel_plan = 0x7f; /* use 2G + 5G as default */
1899
1900 /*tx power*/
1901 _rtl8822be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1902 hwinfo);
1903
1904 rtl8822be_read_bt_coexist_info_from_hwpg(
1905 hw, rtlefuse->autoload_failflag, hwinfo);
1906
1907 /*amplifier type*/
1908 _rtl8822be_read_amplifier_type(hw, hwinfo, rtlefuse->autoload_failflag);
1909
1910 /*rfe type*/
1911 _rtl8822be_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
1912
1913 /*board type*/
1914 rtlefuse->board_type =
1915 (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_8822B]) & 0xE0) >> 5);
1916 if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_8822B]) == 0xFF)
1917 rtlefuse->board_type = 0;
1918
1919 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
1920 rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */
1921
1922 /* phydm maintain rtlhal->board_type and rtlhal->package_type */
1923 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "board_type = 0x%x\n",
1924 rtlefuse->board_type);
1925 /*parse xtal*/
1926 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8822B];
1927 if (hwinfo[EEPROM_XTAL_8822B] == 0xFF)
1928 rtlefuse->crystalcap = 0; /*0x20;*/
1929
1930 /*antenna diversity*/
1931 rtlefuse->antenna_div_type = 0;
1932 rtlefuse->antenna_div_cfg = 0;
1933
1934 label_end:
1935 kfree(hwinfo);
1936 }
1937
_rtl8822be_hal_customized_behavior(struct ieee80211_hw * hw)1938 static void _rtl8822be_hal_customized_behavior(struct ieee80211_hw *hw)
1939 {
1940 struct rtl_priv *rtlpriv = rtl_priv(hw);
1941 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1942 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1943
1944 pcipriv->ledctl.led_opendrain = true;
1945
1946 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
1947 rtlhal->oem_id);
1948 }
1949
_rtl8822be_read_pa_bias(struct ieee80211_hw * hw,struct rtl_phydm_params * params)1950 static void _rtl8822be_read_pa_bias(struct ieee80211_hw *hw,
1951 struct rtl_phydm_params *params)
1952 {
1953 struct rtl_priv *rtlpriv = rtl_priv(hw);
1954 struct rtl_halmac_ops *halmac_ops = rtlpriv->halmac.ops;
1955 u32 size;
1956 u8 *map = NULL;
1957
1958 /* fill default values */
1959 params->efuse0x3d7 = 0xFF;
1960 params->efuse0x3d8 = 0xFF;
1961
1962 if (halmac_ops->halmac_get_physical_efuse_size(rtlpriv, &size))
1963 goto err;
1964
1965 map = kmalloc(size, GFP_KERNEL);
1966 if (!map)
1967 goto err;
1968
1969 if (halmac_ops->halmac_read_physical_efuse_map(rtlpriv, map, size))
1970 goto err;
1971
1972 params->efuse0x3d7 = map[0x3d7];
1973 params->efuse0x3d8 = map[0x3d8];
1974
1975 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1976 "efuse0x3d7 = 0x%2x, efuse0x3d8 = 0x%2x\n",
1977 params->efuse0x3d7, params->efuse0x3d8);
1978
1979 err:
1980 kfree(map);
1981 }
1982
rtl8822be_read_eeprom_info(struct ieee80211_hw * hw,struct rtl_phydm_params * params)1983 void rtl8822be_read_eeprom_info(struct ieee80211_hw *hw,
1984 struct rtl_phydm_params *params)
1985 {
1986 struct rtl_priv *rtlpriv = rtl_priv(hw);
1987 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1988 struct rtl_phy *rtlphy = &rtlpriv->phy;
1989 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1990 u8 tmp_u1b;
1991
1992 rtlhal->version = _rtl8822be_read_chip_version(hw);
1993
1994 params->mp_chip = (rtlhal->version & BIT_RTL_ID_8822B) ? 0 : 1;
1995 params->fab_ver = BIT_GET_VENDOR_ID_8822B(rtlhal->version) >> 2;
1996 params->cut_ver = BIT_GET_CHIP_VER_8822B(rtlhal->version);
1997
1998 /* fab_ver mapping */
1999 if (params->fab_ver == 2)
2000 params->fab_ver = 1;
2001 else if (params->fab_ver == 1)
2002 params->fab_ver = 2;
2003
2004 /* read PA bias: params->efuse0x3d7/efuse0x3d8 */
2005 _rtl8822be_read_pa_bias(hw, params);
2006
2007 if (get_rf_type(rtlphy) == RF_1T1R)
2008 rtlpriv->dm.rfpath_rxenable[0] = true;
2009 else
2010 rtlpriv->dm.rfpath_rxenable[0] =
2011 rtlpriv->dm.rfpath_rxenable[1] = true;
2012 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2013 rtlhal->version);
2014 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_EEPROM_CTRL_8822B);
2015 if (tmp_u1b & BIT(4)) {
2016 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2017 rtlefuse->epromtype = EEPROM_93C46;
2018 } else {
2019 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2020 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2021 }
2022 if (tmp_u1b & BIT(5)) {
2023 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2024 rtlefuse->autoload_failflag = false;
2025 _rtl8822be_read_adapter_info(hw);
2026 } else {
2027 pr_err("Autoload ERR!!\n");
2028 }
2029 _rtl8822be_hal_customized_behavior(hw);
2030
2031 rtlphy->rfpath_rx_enable[0] = true;
2032 if (rtlphy->rf_type == RF_2T2R)
2033 rtlphy->rfpath_rx_enable[1] = true;
2034 }
2035
rtl8822be_read_eeprom_info_dummy(struct ieee80211_hw * hw)2036 void rtl8822be_read_eeprom_info_dummy(struct ieee80211_hw *hw)
2037 {
2038 /*
2039 * 8822b use halmac, so
2040 * move rtl8822be_read_eeprom_info() to rtl8822be_init_sw_vars()
2041 * after halmac_init_adapter().
2042 */
2043 }
2044
_rtl8822be_rate_to_bitmap_2ssvht(__le16 vht_rate)2045 static u32 _rtl8822be_rate_to_bitmap_2ssvht(__le16 vht_rate)
2046 {
2047 u8 i, j, tmp_rate;
2048 u32 rate_bitmap = 0;
2049
2050 for (i = j = 0; i < 4; i += 2, j += 10) {
2051 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
2052
2053 switch (tmp_rate) {
2054 case 2:
2055 rate_bitmap = rate_bitmap | (0x03ff << j);
2056 break;
2057
2058 case 1:
2059 rate_bitmap = rate_bitmap | (0x01ff << j);
2060 break;
2061
2062 case 0:
2063 rate_bitmap = rate_bitmap | (0x00ff << j);
2064 break;
2065
2066 default:
2067 break;
2068 }
2069 }
2070
2071 return rate_bitmap;
2072 }
2073
_rtl8822be_get_vht_en(enum wireless_mode wirelessmode,u32 ratr_bitmap)2074 static u8 _rtl8822be_get_vht_en(enum wireless_mode wirelessmode,
2075 u32 ratr_bitmap)
2076 {
2077 u8 ret = 0;
2078
2079 if (wirelessmode < WIRELESS_MODE_N_24G) {
2080 ret = 0;
2081 } else if (wirelessmode == WIRELESS_MODE_AC_24G) {
2082 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */
2083 ret = 3;
2084 else /* Mix, 1SS */
2085 ret = 2;
2086 } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
2087 ret = 1;
2088 } /* VHT */
2089
2090 return ret << 4;
2091 }
2092
_rtl8822be_get_ra_ldpc(struct ieee80211_hw * hw,u8 mac_id,struct rtl_sta_info * sta_entry,enum wireless_mode wirelessmode)2093 static u8 _rtl8822be_get_ra_ldpc(struct ieee80211_hw *hw, u8 mac_id,
2094 struct rtl_sta_info *sta_entry,
2095 enum wireless_mode wirelessmode)
2096 {
2097 u8 b_ldpc = 0;
2098 /*not support ldpc, do not open*/
2099 return b_ldpc << 2;
2100 }
2101
_rtl8822be_get_ra_rftype(struct ieee80211_hw * hw,enum wireless_mode wirelessmode,u32 ratr_bitmap)2102 static u8 _rtl8822be_get_ra_rftype(struct ieee80211_hw *hw,
2103 enum wireless_mode wirelessmode,
2104 u32 ratr_bitmap)
2105 {
2106 struct rtl_priv *rtlpriv = rtl_priv(hw);
2107 struct rtl_phy *rtlphy = &rtlpriv->phy;
2108 u8 rf_type = RF_1T1R;
2109
2110 if (rtlphy->rf_type == RF_1T1R) {
2111 rf_type = RF_1T1R;
2112 } else if (wirelessmode == WIRELESS_MODE_AC_5G ||
2113 wirelessmode == WIRELESS_MODE_AC_24G ||
2114 wirelessmode == WIRELESS_MODE_AC_ONLY) {
2115 if (ratr_bitmap & 0xffc00000)
2116 rf_type = RF_2T2R;
2117 } else if (wirelessmode == WIRELESS_MODE_N_5G ||
2118 wirelessmode == WIRELESS_MODE_N_24G) {
2119 if (ratr_bitmap & 0xfff00000)
2120 rf_type = RF_2T2R;
2121 }
2122
2123 return rf_type;
2124 }
2125
_rtl8822be_get_ra_shortgi(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 mac_id)2126 static bool _rtl8822be_get_ra_shortgi(struct ieee80211_hw *hw,
2127 struct ieee80211_sta *sta, u8 mac_id)
2128 {
2129 bool b_short_gi = false;
2130 u8 b_curshortgi_40mhz =
2131 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1 : 0;
2132 u8 b_curshortgi_20mhz =
2133 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1 : 0;
2134 u8 b_curshortgi_80mhz = 0;
2135
2136 b_curshortgi_80mhz =
2137 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
2138
2139 if (mac_id == 99 /*MAC_ID_STATIC_FOR_BROADCAST_MULTICAST*/)
2140 b_short_gi = false;
2141
2142 if (b_curshortgi_40mhz || b_curshortgi_80mhz || b_curshortgi_20mhz)
2143 b_short_gi = true;
2144
2145 return b_short_gi;
2146 }
2147
rtl8822be_update_hal_rate_mask(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)2148 static void rtl8822be_update_hal_rate_mask(struct ieee80211_hw *hw,
2149 struct ieee80211_sta *sta,
2150 u8 rssi_level, bool update_bw)
2151 {
2152 struct rtl_priv *rtlpriv = rtl_priv(hw);
2153 struct rtl_phy *rtlphy = &rtlpriv->phy;
2154 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2155 struct rtl_sta_info *sta_entry = NULL;
2156 u32 ratr_bitmap, ratr_bitmap_msb = 0;
2157 u8 ratr_index;
2158 enum wireless_mode wirelessmode = 0;
2159 u8 curtxbw_40mhz =
2160 (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2161 bool b_shortgi = false;
2162 u8 rate_mask[7];
2163 u8 macid = 0;
2164 u8 rf_type;
2165
2166 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2167 wirelessmode = sta_entry->wireless_mode;
2168
2169 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, "wireless mode = 0x%x\n",
2170 wirelessmode);
2171 if (mac->opmode == NL80211_IFTYPE_STATION ||
2172 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2173 curtxbw_40mhz = mac->bw_40;
2174 } else if (mac->opmode == NL80211_IFTYPE_AP ||
2175 mac->opmode == NL80211_IFTYPE_ADHOC)
2176 macid = sta->aid + 1;
2177 if (wirelessmode == WIRELESS_MODE_N_5G ||
2178 wirelessmode == WIRELESS_MODE_AC_5G ||
2179 wirelessmode == WIRELESS_MODE_A)
2180 ratr_bitmap = (sta->supp_rates[NL80211_BAND_5GHZ]) << 4;
2181 else
2182 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
2183
2184 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2185 ratr_bitmap = 0xfff;
2186
2187 if (wirelessmode == WIRELESS_MODE_N_24G ||
2188 wirelessmode == WIRELESS_MODE_N_5G)
2189 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2190 sta->ht_cap.mcs.rx_mask[0] << 12);
2191 else if (wirelessmode == WIRELESS_MODE_AC_24G ||
2192 wirelessmode == WIRELESS_MODE_AC_5G ||
2193 wirelessmode == WIRELESS_MODE_AC_ONLY)
2194 ratr_bitmap |= _rtl8822be_rate_to_bitmap_2ssvht(
2195 sta->vht_cap.vht_mcs.rx_mcs_map)
2196 << 12;
2197
2198 b_shortgi = _rtl8822be_get_ra_shortgi(hw, sta, macid);
2199 rf_type = _rtl8822be_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
2200
2201 ratr_index = rtlpriv->phydm.ops->phydm_rate_id_mapping(
2202 rtlpriv, wirelessmode, rf_type, rtlphy->current_chan_bw);
2203 sta_entry->ratr_index = ratr_index;
2204
2205 rtlpriv->phydm.ops->phydm_get_ra_bitmap(
2206 rtlpriv, wirelessmode, rf_type, rtlphy->current_chan_bw,
2207 rssi_level, &ratr_bitmap_msb, &ratr_bitmap);
2208
2209 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, "ratr_bitmap :%x\n",
2210 ratr_bitmap);
2211
2212 rate_mask[0] = macid;
2213 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
2214 rate_mask[2] =
2215 rtlphy->current_chan_bw | ((!update_bw) << 3) |
2216 _rtl8822be_get_vht_en(wirelessmode, ratr_bitmap) |
2217 _rtl8822be_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
2218
2219 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2220 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2221 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2222 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2223
2224 RT_TRACE(
2225 rtlpriv, COMP_RATR, DBG_DMESG,
2226 "Rate_index:%x, ratr_val:%08x, %02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
2227 ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2228 rate_mask[2], rate_mask[3], rate_mask[4], rate_mask[5],
2229 rate_mask[6]);
2230 rtl8822be_fill_h2c_cmd(hw, H2C_8822B_MACID_CFG, 7, rate_mask);
2231
2232 /* for h2c cmd 0x46, only modify cmd id & ra mask */
2233 /* Keep rate_mask0~2 of cmd 0x40, but clear byte3 and later */
2234 /* 8822B has no 3SS, so keep it zeros. */
2235 memset(rate_mask + 3, 0, 4);
2236
2237 rtl8822be_fill_h2c_cmd(hw, H2C_8822B_MACID_CFG_3SS, 7, rate_mask);
2238
2239 _rtl8822be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2240 }
2241
rtl8822be_update_hal_rate_tbl(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)2242 void rtl8822be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2243 struct ieee80211_sta *sta, u8 rssi_level,
2244 bool update_bw)
2245 {
2246 struct rtl_priv *rtlpriv = rtl_priv(hw);
2247
2248 if (rtlpriv->dm.useramask)
2249 rtl8822be_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2250 }
2251
rtl8822be_update_channel_access_setting(struct ieee80211_hw * hw)2252 void rtl8822be_update_channel_access_setting(struct ieee80211_hw *hw)
2253 {
2254 struct rtl_priv *rtlpriv = rtl_priv(hw);
2255 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2256 u16 sifs_timer;
2257
2258 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2259 (u8 *)&mac->slot_time);
2260 if (!mac->ht_enable)
2261 sifs_timer = 0x0a0a;
2262 else
2263 sifs_timer = 0x0e0e;
2264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2265 }
2266
rtl8822be_gpio_radio_on_off_checking(struct ieee80211_hw * hw,u8 * valid)2267 bool rtl8822be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2268 {
2269 *valid = 1;
2270 return true;
2271 }
2272
rtl8822be_set_key(struct ieee80211_hw * hw,u32 key_index,u8 * p_macaddr,bool is_group,u8 enc_algo,bool is_wepkey,bool clear_all)2273 void rtl8822be_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2274 bool is_group, u8 enc_algo, bool is_wepkey,
2275 bool clear_all)
2276 {
2277 struct rtl_priv *rtlpriv = rtl_priv(hw);
2278 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2279 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2280 u8 *macaddr = p_macaddr;
2281 u32 entry_id = 0;
2282 bool is_pairwise = false;
2283
2284 static u8 cam_const_addr[4][6] = {
2285 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2286 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2287 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2288 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03},
2289 };
2290 static u8 cam_const_broad[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2291
2292 if (clear_all) {
2293 u8 idx = 0;
2294 u8 cam_offset = 0;
2295 u8 clear_number = 5;
2296
2297 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2298
2299 for (idx = 0; idx < clear_number; idx++) {
2300 rtl_cam_mark_invalid(hw, cam_offset + idx);
2301 rtl_cam_empty_entry(hw, cam_offset + idx);
2302
2303 if (idx < 5) {
2304 memset(rtlpriv->sec.key_buf[idx], 0,
2305 MAX_KEY_LEN);
2306 rtlpriv->sec.key_len[idx] = 0;
2307 }
2308 }
2309
2310 return;
2311 }
2312
2313 switch (enc_algo) {
2314 case WEP40_ENCRYPTION:
2315 enc_algo = CAM_WEP40;
2316 break;
2317 case WEP104_ENCRYPTION:
2318 enc_algo = CAM_WEP104;
2319 break;
2320 case TKIP_ENCRYPTION:
2321 enc_algo = CAM_TKIP;
2322 break;
2323 case AESCCMP_ENCRYPTION:
2324 enc_algo = CAM_AES;
2325 break;
2326 default:
2327 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2328 "switch case %#x not processed\n", enc_algo);
2329 enc_algo = CAM_TKIP;
2330 break;
2331 }
2332
2333 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2334 macaddr = cam_const_addr[key_index];
2335 entry_id = key_index;
2336 } else {
2337 if (is_group) {
2338 macaddr = cam_const_broad;
2339 entry_id = key_index;
2340 } else {
2341 if (mac->opmode == NL80211_IFTYPE_AP) {
2342 entry_id =
2343 rtl_cam_get_free_entry(hw, p_macaddr);
2344 if (entry_id >= TOTAL_CAM_ENTRY) {
2345 pr_err("Can not find free hwsecurity cam entry\n");
2346 return;
2347 }
2348 } else {
2349 entry_id = CAM_PAIRWISE_KEY_POSITION;
2350 }
2351
2352 key_index = PAIRWISE_KEYIDX;
2353 is_pairwise = true;
2354 }
2355 }
2356
2357 if (rtlpriv->sec.key_len[key_index] == 0) {
2358 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2359 "delete one entry, entry_id is %d\n", entry_id);
2360 if (mac->opmode == NL80211_IFTYPE_AP)
2361 rtl_cam_del_entry(hw, p_macaddr);
2362 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2363 } else {
2364 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "add one entry\n");
2365 if (is_pairwise) {
2366 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2367 "set Pairwise key\n");
2368
2369 rtl_cam_add_one_entry(hw, macaddr, key_index, entry_id,
2370 enc_algo, CAM_CONFIG_NO_USEDK,
2371 rtlpriv->sec.key_buf[key_index]);
2372 } else {
2373 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2374 "set group key\n");
2375
2376 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2377 rtl_cam_add_one_entry(
2378 hw, rtlefuse->dev_addr, PAIRWISE_KEYIDX,
2379 CAM_PAIRWISE_KEY_POSITION, enc_algo,
2380 CAM_CONFIG_NO_USEDK,
2381 rtlpriv->sec.key_buf[entry_id]);
2382 }
2383
2384 rtl_cam_add_one_entry(hw, macaddr, key_index, entry_id,
2385 enc_algo, CAM_CONFIG_NO_USEDK,
2386 rtlpriv->sec.key_buf[entry_id]);
2387 }
2388 }
2389 }
2390
rtl8822be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw * hw,bool auto_load_fail,u8 * hwinfo)2391 void rtl8822be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2392 bool auto_load_fail, u8 *hwinfo)
2393 {
2394 struct rtl_priv *rtlpriv = rtl_priv(hw);
2395 u8 value;
2396 u32 val32;
2397
2398 val32 = rtl_read_dword(rtlpriv, REG_WL_BT_PWR_CTRL_8822B);
2399 if (val32 & BIT_BT_FUNC_EN_8822B)
2400 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2401 else
2402 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2403
2404 if (!auto_load_fail) {
2405 value = hwinfo[EEPROM_RF_BT_SETTING_8822B];
2406
2407 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8822B;
2408 rtlpriv->btcoexist.btc_info.ant_num =
2409 (value & BIT(0) ? ANT_TOTAL_X1 : ANT_TOTAL_X2);
2410 } else {
2411 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8822B;
2412 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2;
2413 }
2414 }
2415
rtl8822be_bt_reg_init(struct ieee80211_hw * hw)2416 void rtl8822be_bt_reg_init(struct ieee80211_hw *hw)
2417 {
2418 struct rtl_priv *rtlpriv = rtl_priv(hw);
2419
2420 /* 0:Low, 1:High, 2:From Efuse. */
2421 rtlpriv->btcoexist.reg_bt_iso = 2;
2422 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2423 rtlpriv->btcoexist.reg_bt_sco = 3;
2424 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2425 rtlpriv->btcoexist.reg_bt_sco = 0;
2426 }
2427
rtl8822be_suspend(struct ieee80211_hw * hw)2428 void rtl8822be_suspend(struct ieee80211_hw *hw) {}
2429
rtl8822be_resume(struct ieee80211_hw * hw)2430 void rtl8822be_resume(struct ieee80211_hw *hw) {}
2431
