1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 /* include files */
9
10 #include "odm_precomp.h"
11 #include "phy.h"
12
13 u32 GlobalDebugLevel;
14
15 /* avoid to warn in FreeBSD ==> To DO modify */
16 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {
17 /* UL DL */
18 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
19 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */
20 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */
21 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */
22 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */
23 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */
24 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */
25 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */
26 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */
27 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */
28 };
29
30 /* Global var */
31 u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
32 0x7f8001fe, /* 0, +6.0dB */
33 0x788001e2, /* 1, +5.5dB */
34 0x71c001c7, /* 2, +5.0dB */
35 0x6b8001ae, /* 3, +4.5dB */
36 0x65400195, /* 4, +4.0dB */
37 0x5fc0017f, /* 5, +3.5dB */
38 0x5a400169, /* 6, +3.0dB */
39 0x55400155, /* 7, +2.5dB */
40 0x50800142, /* 8, +2.0dB */
41 0x4c000130, /* 9, +1.5dB */
42 0x47c0011f, /* 10, +1.0dB */
43 0x43c0010f, /* 11, +0.5dB */
44 0x40000100, /* 12, +0dB */
45 0x3c8000f2, /* 13, -0.5dB */
46 0x390000e4, /* 14, -1.0dB */
47 0x35c000d7, /* 15, -1.5dB */
48 0x32c000cb, /* 16, -2.0dB */
49 0x300000c0, /* 17, -2.5dB */
50 0x2d4000b5, /* 18, -3.0dB */
51 0x2ac000ab, /* 19, -3.5dB */
52 0x288000a2, /* 20, -4.0dB */
53 0x26000098, /* 21, -4.5dB */
54 0x24000090, /* 22, -5.0dB */
55 0x22000088, /* 23, -5.5dB */
56 0x20000080, /* 24, -6.0dB */
57 0x1e400079, /* 25, -6.5dB */
58 0x1c800072, /* 26, -7.0dB */
59 0x1b00006c, /* 27. -7.5dB */
60 0x19800066, /* 28, -8.0dB */
61 0x18000060, /* 29, -8.5dB */
62 0x16c0005b, /* 30, -9.0dB */
63 0x15800056, /* 31, -9.5dB */
64 0x14400051, /* 32, -10.0dB */
65 0x1300004c, /* 33, -10.5dB */
66 0x12000048, /* 34, -11.0dB */
67 0x11000044, /* 35, -11.5dB */
68 0x10000040, /* 36, -12.0dB */
69 0x0f00003c,/* 37, -12.5dB */
70 0x0e400039,/* 38, -13.0dB */
71 0x0d800036,/* 39, -13.5dB */
72 0x0cc00033,/* 40, -14.0dB */
73 0x0c000030,/* 41, -14.5dB */
74 0x0b40002d,/* 42, -15.0dB */
75 };
76
77 u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
78 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
79 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
80 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
81 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
82 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
83 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
84 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
85 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
86 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
87 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
88 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
89 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
90 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
91 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
92 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
93 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
94 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
95 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
96 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
97 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
98 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
99 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
100 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
101 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
102 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
103 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
104 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
105 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
106 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
107 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
108 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
109 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
110 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
111 };
112
113 u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
114 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
115 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
116 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
117 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
118 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
119 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
120 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
121 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
122 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
123 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
124 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
125 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
126 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
127 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
128 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
129 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
130 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
131 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
132 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
133 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
134 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
135 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
136 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
137 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
138 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
139 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
140 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
141 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
142 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
143 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
144 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
145 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
146 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
147 };
148
149 #define RxDefaultAnt1 0x65a9
150 #define RxDefaultAnt2 0x569a
151
ODM_InitDebugSetting(struct odm_dm_struct * pDM_Odm)152 void ODM_InitDebugSetting(struct odm_dm_struct *pDM_Odm)
153 {
154 pDM_Odm->DebugLevel = ODM_DBG_TRACE;
155
156 pDM_Odm->DebugComponents = 0;
157 }
158
159 /* 3 Export Interface */
160
161 /* 2011/09/21 MH Add to describe different team necessary resource allocate?? */
ODM_DMInit(struct odm_dm_struct * pDM_Odm)162 void ODM_DMInit(struct odm_dm_struct *pDM_Odm)
163 {
164 /* 2012.05.03 Luke: For all IC series */
165 odm_CommonInfoSelfInit(pDM_Odm);
166 odm_CmnInfoInit_Debug(pDM_Odm);
167 odm_DIGInit(pDM_Odm);
168 odm_RateAdaptiveMaskInit(pDM_Odm);
169
170 odm_DynamicTxPowerInit(pDM_Odm);
171 odm_TXPowerTrackingInit(pDM_Odm);
172 ODM_EdcaTurboInit(pDM_Odm);
173 ODM_RAInfo_Init_all(pDM_Odm);
174 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
175 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
176 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
177 odm_InitHybridAntDiv(pDM_Odm);
178 }
179
180 /* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
181 /* You can not add any dummy function here, be care, you can only use DM structure */
182 /* to perform any new ODM_DM. */
ODM_DMWatchdog(struct odm_dm_struct * pDM_Odm)183 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm)
184 {
185 /* 2012.05.03 Luke: For all IC series */
186 odm_CmnInfoHook_Debug(pDM_Odm);
187 odm_CmnInfoUpdate_Debug(pDM_Odm);
188 odm_CommonInfoSelfUpdate(pDM_Odm);
189 odm_FalseAlarmCounterStatistics(pDM_Odm);
190 odm_RSSIMonitorCheck(pDM_Odm);
191
192 /* Fix Leave LPS issue */
193 odm_DIG(pDM_Odm);
194 odm_CCKPacketDetectionThresh(pDM_Odm);
195
196 if (*(pDM_Odm->pbPowerSaving))
197 return;
198
199 odm_RefreshRateAdaptiveMask(pDM_Odm);
200
201 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
202 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
203 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
204 odm_HwAntDiv(pDM_Odm);
205
206 ODM_TXPowerTrackingCheck(pDM_Odm);
207 odm_EdcaTurboCheck(pDM_Odm);
208 }
209
ODM_CmnInfoPtrArrayHook(struct odm_dm_struct * pDM_Odm,enum odm_common_info_def CmnInfo,u16 Index,void * pValue)210 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue)
211 {
212 /* Hook call by reference pointer. */
213 switch (CmnInfo) {
214 /* Dynamic call by reference pointer. */
215 case ODM_CMNINFO_STA_STATUS:
216 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
217 break;
218 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
219 default:
220 /* do nothing */
221 break;
222 }
223 }
224
odm_CommonInfoSelfInit(struct odm_dm_struct * pDM_Odm)225 void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm)
226 {
227 struct adapter *adapter = pDM_Odm->Adapter;
228
229 pDM_Odm->bCckHighPower = (bool)phy_query_bb_reg(adapter, 0x824, BIT(9));
230 pDM_Odm->RFPathRxEnable = (u8)phy_query_bb_reg(adapter, 0xc04, 0x0F);
231
232 ODM_InitDebugSetting(pDM_Odm);
233 }
234
odm_CommonInfoSelfUpdate(struct odm_dm_struct * pDM_Odm)235 void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm)
236 {
237 u8 EntryCnt = 0;
238 u8 i;
239 struct sta_info *pEntry;
240
241 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) {
242 if (*(pDM_Odm->pSecChOffset) == 1)
243 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2;
244 else if (*(pDM_Odm->pSecChOffset) == 2)
245 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2;
246 } else {
247 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
248 }
249
250 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
251 pEntry = pDM_Odm->pODM_StaInfo[i];
252 if (IS_STA_VALID(pEntry))
253 EntryCnt++;
254 }
255 if (EntryCnt == 1)
256 pDM_Odm->bOneEntryOnly = true;
257 else
258 pDM_Odm->bOneEntryOnly = false;
259 }
260
odm_CmnInfoInit_Debug(struct odm_dm_struct * pDM_Odm)261 void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm)
262 {
263 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n"));
264 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform));
265 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility));
266 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface));
267 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType));
268 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion));
269 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType));
270 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA));
271 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA));
272 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW));
273 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID));
274 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest));
275 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest));
276 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent));
277 }
278
odm_CmnInfoHook_Debug(struct odm_dm_struct * pDM_Odm)279 void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm)
280 {
281 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n"));
282 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast)));
283 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast)));
284 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode)));
285 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset)));
286 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity)));
287 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth)));
288 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel)));
289
290 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess)));
291 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving)));
292 }
293
odm_CmnInfoUpdate_Debug(struct odm_dm_struct * pDM_Odm)294 void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm)
295 {
296 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n"));
297 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct));
298 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display));
299 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked));
300 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min));
301 }
302
ODM_Write_DIG(struct odm_dm_struct * pDM_Odm,u8 CurrentIGI)303 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI)
304 {
305 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
306 struct adapter *adapter = pDM_Odm->Adapter;
307
308 if (pDM_DigTable->CurIGValue != CurrentIGI) {
309 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI);
310 pDM_DigTable->CurIGValue = CurrentIGI;
311 }
312 }
313
odm_DIGInit(struct odm_dm_struct * pDM_Odm)314 void odm_DIGInit(struct odm_dm_struct *pDM_Odm)
315 {
316 struct adapter *adapter = pDM_Odm->Adapter;
317 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
318
319 pDM_DigTable->CurIGValue = (u8)phy_query_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N);
320 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW;
321 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH;
322 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW;
323 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH;
324 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
325 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
326 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
327 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
328 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
329 pDM_DigTable->PreCCK_CCAThres = 0xFF;
330 pDM_DigTable->CurCCK_CCAThres = 0x83;
331 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
332 pDM_DigTable->LargeFAHit = 0;
333 pDM_DigTable->Recover_cnt = 0;
334 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
335 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
336 pDM_DigTable->bMediaConnect_0 = false;
337 pDM_DigTable->bMediaConnect_1 = false;
338
339 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */
340 pDM_Odm->bDMInitialGainEnable = true;
341 }
342
odm_DIG(struct odm_dm_struct * pDM_Odm)343 void odm_DIG(struct odm_dm_struct *pDM_Odm)
344 {
345 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
346 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
347 u8 DIG_Dynamic_MIN;
348 u8 DIG_MaxOfMin;
349 bool FirstConnect, FirstDisConnect;
350 u8 dm_dig_max, dm_dig_min;
351 u8 CurrentIGI = pDM_DigTable->CurIGValue;
352
353 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
354 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
355 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
356 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
357 return;
358 }
359
360 if (*(pDM_Odm->pbScanInProcess)) {
361 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n"));
362 return;
363 }
364
365 /* add by Neil Chen to avoid PSD is processing */
366 if (!pDM_Odm->bDMInitialGainEnable) {
367 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n"));
368 return;
369 }
370
371 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
372 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
373 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
374
375 /* 1 Boundary Decision */
376 dm_dig_max = DM_DIG_MAX_NIC;
377 dm_dig_min = DM_DIG_MIN_NIC;
378 DIG_MaxOfMin = DM_DIG_MAX_AP;
379
380 if (pDM_Odm->bLinked) {
381 /* 2 Modify DIG upper bound */
382 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
383 pDM_DigTable->rx_gain_range_max = dm_dig_max;
384 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
385 pDM_DigTable->rx_gain_range_max = dm_dig_min;
386 else
387 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
388 /* 2 Modify DIG lower bound */
389 if (pDM_Odm->bOneEntryOnly) {
390 if (pDM_Odm->RSSI_Min < dm_dig_min)
391 DIG_Dynamic_MIN = dm_dig_min;
392 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
393 DIG_Dynamic_MIN = DIG_MaxOfMin;
394 else
395 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
396 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
397 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n",
398 DIG_Dynamic_MIN));
399 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
400 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n",
401 pDM_Odm->RSSI_Min));
402 } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) {
403 /* 1 Lower Bound for 88E AntDiv */
404 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
405 DIG_Dynamic_MIN = (u8)pDM_DigTable->AntDiv_RSSI_max;
406 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
407 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n",
408 pDM_DigTable->AntDiv_RSSI_max));
409 }
410 } else {
411 DIG_Dynamic_MIN = dm_dig_min;
412 }
413 } else {
414 pDM_DigTable->rx_gain_range_max = dm_dig_max;
415 DIG_Dynamic_MIN = dm_dig_min;
416 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n"));
417 }
418
419 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
420 if (pFalseAlmCnt->Cnt_all > 10000) {
421 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n"));
422
423 if (pDM_DigTable->LargeFAHit != 3)
424 pDM_DigTable->LargeFAHit++;
425 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
426 pDM_DigTable->ForbiddenIGI = CurrentIGI;
427 pDM_DigTable->LargeFAHit = 1;
428 }
429
430 if (pDM_DigTable->LargeFAHit >= 3) {
431 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
432 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
433 else
434 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
435 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */
436 }
437
438 } else {
439 /* Recovery mechanism for IGI lower bound */
440 if (pDM_DigTable->Recover_cnt != 0) {
441 pDM_DigTable->Recover_cnt--;
442 } else {
443 if (pDM_DigTable->LargeFAHit < 3) {
444 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */
445 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
446 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
447 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n"));
448 } else {
449 pDM_DigTable->ForbiddenIGI--;
450 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
451 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n"));
452 }
453 } else {
454 pDM_DigTable->LargeFAHit = 0;
455 }
456 }
457 }
458 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
459 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",
460 pDM_DigTable->LargeFAHit));
461
462 /* 1 Adjust initial gain by false alarm */
463 if (pDM_Odm->bLinked) {
464 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n"));
465 if (FirstConnect) {
466 CurrentIGI = pDM_Odm->RSSI_Min;
467 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
468 } else {
469 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
470 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
471 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
472 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
473 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
474 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
475 }
476 } else {
477 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n"));
478 if (FirstDisConnect) {
479 CurrentIGI = pDM_DigTable->rx_gain_range_min;
480 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n"));
481 } else {
482 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
483 if (pFalseAlmCnt->Cnt_all > 10000)
484 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
485 else if (pFalseAlmCnt->Cnt_all > 8000)
486 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
487 else if (pFalseAlmCnt->Cnt_all < 500)
488 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
489 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n"));
490 }
491 }
492 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n"));
493 /* 1 Check initial gain by upper/lower bound */
494 if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
495 CurrentIGI = pDM_DigTable->rx_gain_range_max;
496 if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
497 CurrentIGI = pDM_DigTable->rx_gain_range_min;
498
499 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
500 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
501 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
502 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all));
503 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI));
504
505 /* 2 High power RSSI threshold */
506
507 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
508 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
509 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
510 }
511
512 /* 3============================================================ */
513 /* 3 FASLE ALARM CHECK */
514 /* 3============================================================ */
515
odm_FalseAlarmCounterStatistics(struct odm_dm_struct * pDM_Odm)516 void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
517 {
518 struct adapter *adapter = pDM_Odm->Adapter;
519 u32 ret_value;
520 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
521
522 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
523 return;
524
525 /* hold ofdm counter */
526 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */
527 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */
528
529 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
530 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
531 FalseAlmCnt->Cnt_SB_Search_fail = (ret_value & 0xffff0000)>>16;
532 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
533 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
534 FalseAlmCnt->Cnt_Parity_Fail = (ret_value & 0xffff0000)>>16;
535 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
536 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
537 FalseAlmCnt->Cnt_Crc8_fail = (ret_value & 0xffff0000)>>16;
538 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
539 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
540
541 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
542 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
543 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
544
545 ret_value = phy_query_bb_reg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord);
546 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
547 FalseAlmCnt->Cnt_BW_USC = (ret_value & 0xffff0000)>>16;
548
549 /* hold cck counter */
550 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
551 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
552
553 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
554 FalseAlmCnt->Cnt_Cck_fail = ret_value;
555 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
556 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8;
557
558 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
559 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
560
561 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
562 FalseAlmCnt->Cnt_SB_Search_fail +
563 FalseAlmCnt->Cnt_Parity_Fail +
564 FalseAlmCnt->Cnt_Rate_Illegal +
565 FalseAlmCnt->Cnt_Crc8_fail +
566 FalseAlmCnt->Cnt_Mcs_fail +
567 FalseAlmCnt->Cnt_Cck_fail);
568
569 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
570
571 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
572 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
573 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
574 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
575 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
576 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
577 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
578 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
579 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
580 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
581 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail));
582 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
583 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all));
584 }
585
586 /* 3============================================================ */
587 /* 3 CCK Packet Detect Threshold */
588 /* 3============================================================ */
589
odm_CCKPacketDetectionThresh(struct odm_dm_struct * pDM_Odm)590 void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm)
591 {
592 u8 CurCCK_CCAThres;
593 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
594
595 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
596 return;
597 if (pDM_Odm->ExtLNA)
598 return;
599 if (pDM_Odm->bLinked) {
600 if (pDM_Odm->RSSI_Min > 25) {
601 CurCCK_CCAThres = 0xcd;
602 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
603 CurCCK_CCAThres = 0x83;
604 } else {
605 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
606 CurCCK_CCAThres = 0x83;
607 else
608 CurCCK_CCAThres = 0x40;
609 }
610 } else {
611 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
612 CurCCK_CCAThres = 0x83;
613 else
614 CurCCK_CCAThres = 0x40;
615 }
616 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
617 }
618
ODM_Write_CCK_CCA_Thres(struct odm_dm_struct * pDM_Odm,u8 CurCCK_CCAThres)619 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres)
620 {
621 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
622 struct adapter *adapt = pDM_Odm->Adapter;
623
624 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */
625 usb_write8(adapt, ODM_REG_CCK_CCA_11N, CurCCK_CCAThres);
626 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
627 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
628 }
629
ODM_RF_Saving(struct odm_dm_struct * pDM_Odm,u8 bForceInNormal)630 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
631 {
632 struct adapter *adapter = pDM_Odm->Adapter;
633 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
634 u8 Rssi_Up_bound = 30;
635 u8 Rssi_Low_bound = 25;
636
637 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
638 Rssi_Up_bound = 50;
639 Rssi_Low_bound = 45;
640 }
641 if (pDM_PSTable->initialize == 0) {
642 pDM_PSTable->Reg874 = (phy_query_bb_reg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14;
643 pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord) & BIT(3))>>3;
644 pDM_PSTable->Reg85C = (phy_query_bb_reg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24;
645 pDM_PSTable->RegA74 = (phy_query_bb_reg(adapter, 0xa74, bMaskDWord)&0xF000)>>12;
646 pDM_PSTable->initialize = 1;
647 }
648
649 if (!bForceInNormal) {
650 if (pDM_Odm->RSSI_Min != 0xFF) {
651 if (pDM_PSTable->PreRFState == RF_Normal) {
652 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
653 pDM_PSTable->CurRFState = RF_Save;
654 else
655 pDM_PSTable->CurRFState = RF_Normal;
656 } else {
657 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
658 pDM_PSTable->CurRFState = RF_Normal;
659 else
660 pDM_PSTable->CurRFState = RF_Save;
661 }
662 } else {
663 pDM_PSTable->CurRFState = RF_MAX;
664 }
665 } else {
666 pDM_PSTable->CurRFState = RF_Normal;
667 }
668
669 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
670 if (pDM_PSTable->CurRFState == RF_Save) {
671 phy_set_bb_reg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
672 phy_set_bb_reg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */
673 phy_set_bb_reg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
674 phy_set_bb_reg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
675 phy_set_bb_reg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
676 phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
677 phy_set_bb_reg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
678 } else {
679 phy_set_bb_reg(adapter, 0x874, 0x1CC000, pDM_PSTable->Reg874);
680 phy_set_bb_reg(adapter, 0xc70, BIT(3), pDM_PSTable->RegC70);
681 phy_set_bb_reg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
682 phy_set_bb_reg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74);
683 phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0);
684 }
685 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
686 }
687 }
688
689 /* 3============================================================ */
690 /* 3 RATR MASK */
691 /* 3============================================================ */
692 /* 3============================================================ */
693 /* 3 Rate Adaptive */
694 /* 3============================================================ */
695
odm_RateAdaptiveMaskInit(struct odm_dm_struct * pDM_Odm)696 void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm)
697 {
698 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
699
700 pOdmRA->Type = DM_Type_ByDriver;
701 if (pOdmRA->Type == DM_Type_ByDriver)
702 pDM_Odm->bUseRAMask = true;
703 else
704 pDM_Odm->bUseRAMask = false;
705
706 pOdmRA->RATRState = DM_RATR_STA_INIT;
707 pOdmRA->HighRSSIThresh = 50;
708 pOdmRA->LowRSSIThresh = 20;
709 }
710
ODM_Get_Rate_Bitmap(struct odm_dm_struct * pDM_Odm,u32 macid,u32 ra_mask,u8 rssi_level)711 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level)
712 {
713 struct sta_info *pEntry;
714 u32 rate_bitmap = 0x0fffffff;
715 u8 WirelessMode;
716
717 pEntry = pDM_Odm->pODM_StaInfo[macid];
718 if (!IS_STA_VALID(pEntry))
719 return ra_mask;
720
721 WirelessMode = pEntry->wireless_mode;
722
723 switch (WirelessMode) {
724 case ODM_WM_B:
725 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */
726 rate_bitmap = 0x0000000d;
727 else
728 rate_bitmap = 0x0000000f;
729 break;
730 case (ODM_WM_A|ODM_WM_G):
731 if (rssi_level == DM_RATR_STA_HIGH)
732 rate_bitmap = 0x00000f00;
733 else
734 rate_bitmap = 0x00000ff0;
735 break;
736 case (ODM_WM_B|ODM_WM_G):
737 if (rssi_level == DM_RATR_STA_HIGH)
738 rate_bitmap = 0x00000f00;
739 else if (rssi_level == DM_RATR_STA_MIDDLE)
740 rate_bitmap = 0x00000ff0;
741 else
742 rate_bitmap = 0x00000ff5;
743 break;
744 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
745 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
746 if (rssi_level == DM_RATR_STA_HIGH) {
747 rate_bitmap = 0x000f0000;
748 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
749 rate_bitmap = 0x000ff000;
750 } else {
751 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
752 rate_bitmap = 0x000ff015;
753 else
754 rate_bitmap = 0x000ff005;
755 }
756 break;
757 default:
758 /* case WIRELESS_11_24N: */
759 /* case WIRELESS_11_5N: */
760 rate_bitmap = 0x0fffffff;
761 break;
762 }
763
764 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
765 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n",
766 rssi_level, WirelessMode, rate_bitmap));
767
768 return rate_bitmap;
769 }
770
771 /*-----------------------------------------------------------------------------
772 * Function: odm_RefreshRateAdaptiveMask()
773 *
774 * Overview: Update rate table mask according to rssi
775 *
776 * Input: NONE
777 *
778 * Output: NONE
779 *
780 * Return: NONE
781 *
782 * Revised History:
783 * When Who Remark
784 * 05/27/2009 hpfan Create Version 0.
785 *
786 *---------------------------------------------------------------------------*/
odm_RefreshRateAdaptiveMask(struct odm_dm_struct * pDM_Odm)787 void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm)
788 {
789 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
790 return;
791 /* */
792 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
793 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
794 /* HW dynamic mechanism. */
795 /* */
796 odm_RefreshRateAdaptiveMaskCE(pDM_Odm);
797 }
798
odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct * pDM_Odm)799 void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm)
800 {
801 u8 i;
802 struct adapter *pAdapter = pDM_Odm->Adapter;
803
804 if (pAdapter->bDriverStopped) {
805 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
806 return;
807 }
808
809 if (!pDM_Odm->bUseRAMask) {
810 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
811 return;
812 }
813
814 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
815 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
816
817 if (IS_STA_VALID(pstat)) {
818 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
819 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
820 ("RSSI:%d, RSSI_LEVEL:%d\n",
821 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level));
822 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level);
823 }
824 }
825 }
826 }
827
828 /* Return Value: bool */
829 /* - true: RATRState is changed. */
ODM_RAStateCheck(struct odm_dm_struct * pDM_Odm,s32 RSSI,bool bForceUpdate,u8 * pRATRState)830 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState)
831 {
832 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
833 const u8 GoUpGap = 5;
834 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
835 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
836 u8 RATRState;
837
838 /* Threshold Adjustment: */
839 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
840 /* Here GoUpGap is added to solve the boundary's level alternation issue. */
841 switch (*pRATRState) {
842 case DM_RATR_STA_INIT:
843 case DM_RATR_STA_HIGH:
844 break;
845 case DM_RATR_STA_MIDDLE:
846 HighRSSIThreshForRA += GoUpGap;
847 break;
848 case DM_RATR_STA_LOW:
849 HighRSSIThreshForRA += GoUpGap;
850 LowRSSIThreshForRA += GoUpGap;
851 break;
852 default:
853 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
854 break;
855 }
856
857 /* Decide RATRState by RSSI. */
858 if (RSSI > HighRSSIThreshForRA)
859 RATRState = DM_RATR_STA_HIGH;
860 else if (RSSI > LowRSSIThreshForRA)
861 RATRState = DM_RATR_STA_MIDDLE;
862 else
863 RATRState = DM_RATR_STA_LOW;
864
865 if (*pRATRState != RATRState || bForceUpdate) {
866 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
867 *pRATRState = RATRState;
868 return true;
869 }
870 return false;
871 }
872
873 /* 3============================================================ */
874 /* 3 Dynamic Tx Power */
875 /* 3============================================================ */
876
odm_DynamicTxPowerInit(struct odm_dm_struct * pDM_Odm)877 void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm)
878 {
879 struct adapter *Adapter = pDM_Odm->Adapter;
880 struct dm_priv *pdmpriv = &Adapter->HalData->dmpriv;
881
882 pdmpriv->bDynamicTxPowerEnable = false;
883 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
884 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
885 }
886
887 /* 3============================================================ */
888 /* 3 RSSI Monitor */
889 /* 3============================================================ */
890
odm_RSSIMonitorCheck(struct odm_dm_struct * pDM_Odm)891 void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm)
892 {
893 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
894 return;
895
896 /* */
897 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
898 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
899 /* HW dynamic mechanism. */
900 /* */
901 odm_RSSIMonitorCheckCE(pDM_Odm);
902 } /* odm_RSSIMonitorCheck */
903
FindMinimumRSSI(struct adapter * pAdapter)904 static void FindMinimumRSSI(struct adapter *pAdapter)
905 {
906 struct dm_priv *pdmpriv = &pAdapter->HalData->dmpriv;
907
908 /* 1 1.Unconditionally set RSSI */
909 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
910 }
911
odm_RSSIMonitorCheckCE(struct odm_dm_struct * pDM_Odm)912 void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm)
913 {
914 struct adapter *Adapter = pDM_Odm->Adapter;
915 struct dm_priv *pdmpriv = &Adapter->HalData->dmpriv;
916 int i;
917 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
918 u8 sta_cnt = 0;
919 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
920 struct sta_info *psta;
921 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
922
923 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED))
924 return;
925
926 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
927 psta = pDM_Odm->pODM_StaInfo[i];
928 if (IS_STA_VALID(psta) &&
929 (psta->state & WIFI_ASOC_STATE) &&
930 memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) &&
931 memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) {
932 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
933 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
934
935 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
936 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
937 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
938 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
939 }
940 }
941
942 for (i = 0; i < sta_cnt; i++) {
943 if (PWDB_rssi[i] != 0) {
944 ODM_RA_SetRSSI_8188E(&Adapter->HalData->odmpriv,
945 PWDB_rssi[i] & 0xFF,
946 (PWDB_rssi[i] >> 16) & 0xFF);
947 }
948 }
949
950 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */
951 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
952 else
953 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
954
955 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */
956 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
957 else
958 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
959
960 FindMinimumRSSI(Adapter);
961 Adapter->HalData->odmpriv.RSSI_Min = pdmpriv->MinUndecoratedPWDBForDM;
962 }
963
964 /* 3============================================================ */
965 /* 3 Tx Power Tracking */
966 /* 3============================================================ */
967
odm_TXPowerTrackingInit(struct odm_dm_struct * pDM_Odm)968 void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm)
969 {
970 odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
971 }
972
odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct * pDM_Odm)973 void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm)
974 {
975 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
976 pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
977 if (*(pDM_Odm->mp_mode) != 1)
978 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
979 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl);
980
981 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
982 }
983
ODM_TXPowerTrackingCheck(struct odm_dm_struct * pDM_Odm)984 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm)
985 {
986 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
987 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
988 /* HW dynamic mechanism. */
989 odm_TXPowerTrackingCheckCE(pDM_Odm);
990 }
991
odm_TXPowerTrackingCheckCE(struct odm_dm_struct * pDM_Odm)992 void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm)
993 {
994 struct adapter *Adapter = pDM_Odm->Adapter;
995
996 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
997 return;
998
999 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */
1000 phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
1001
1002 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
1003 return;
1004 } else {
1005 rtl88eu_dm_txpower_tracking_callback_thermalmeter(Adapter);
1006 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
1007 }
1008 }
1009
1010 /* 3============================================================ */
1011 /* 3 SW Antenna Diversity */
1012 /* 3============================================================ */
1013
odm_InitHybridAntDiv(struct odm_dm_struct * pDM_Odm)1014 void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm)
1015 {
1016 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
1017 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n"));
1018 return;
1019 }
1020
1021 rtl88eu_dm_antenna_div_init(pDM_Odm);
1022 }
1023
odm_HwAntDiv(struct odm_dm_struct * pDM_Odm)1024 void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm)
1025 {
1026 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
1027 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n"));
1028 return;
1029 }
1030
1031 rtl88eu_dm_antenna_diversity(pDM_Odm);
1032 }
1033
1034 /* EDCA Turbo */
ODM_EdcaTurboInit(struct odm_dm_struct * pDM_Odm)1035 void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm)
1036 {
1037 struct adapter *Adapter = pDM_Odm->Adapter;
1038
1039 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1040 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1041 Adapter->recvpriv.bIsAnyNonBEPkts = false;
1042
1043 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VO_PARAM)));
1044 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VI_PARAM)));
1045 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BE_PARAM)));
1046 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BK_PARAM)));
1047 } /* ODM_InitEdcaTurbo */
1048
odm_EdcaTurboCheck(struct odm_dm_struct * pDM_Odm)1049 void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm)
1050 {
1051 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1052 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1053 /* HW dynamic mechanism. */
1054 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n"));
1055
1056 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1057 return;
1058
1059 odm_EdcaTurboCheckCE(pDM_Odm);
1060 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n"));
1061 } /* odm_CheckEdcaTurbo */
1062
odm_EdcaTurboCheckCE(struct odm_dm_struct * pDM_Odm)1063 void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm)
1064 {
1065 struct adapter *Adapter = pDM_Odm->Adapter;
1066 u32 trafficIndex;
1067 u32 edca_param;
1068 u64 cur_tx_bytes = 0;
1069 u64 cur_rx_bytes = 0;
1070 u8 bbtchange = false;
1071 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv);
1072 struct recv_priv *precvpriv = &(Adapter->recvpriv);
1073 struct registry_priv *pregpriv = &Adapter->registrypriv;
1074 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv);
1075 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1076
1077 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */
1078 goto dm_CheckEdcaTurbo_EXIT;
1079
1080 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX)
1081 goto dm_CheckEdcaTurbo_EXIT;
1082
1083 /* Check if the status needs to be changed. */
1084 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1085 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1086 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1087
1088 /* traffic, TX or RX */
1089 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1090 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1091 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1092 /* Uplink TP is present. */
1093 trafficIndex = UP_LINK;
1094 } else {
1095 /* Balance TP is present. */
1096 trafficIndex = DOWN_LINK;
1097 }
1098 } else {
1099 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1100 /* Downlink TP is present. */
1101 trafficIndex = DOWN_LINK;
1102 } else {
1103 /* Balance TP is present. */
1104 trafficIndex = UP_LINK;
1105 }
1106 }
1107
1108 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1109 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1110 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1111 else
1112 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1113
1114 usb_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
1115
1116 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1117 }
1118
1119 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1120 } else {
1121 /* Turn Off EDCA turbo here. */
1122 /* Restore original EDCA according to the declaration of AP. */
1123 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1124 usb_write32(Adapter, REG_EDCA_BE_PARAM,
1125 Adapter->HalData->AcParam_BE);
1126 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1127 }
1128 }
1129
1130 dm_CheckEdcaTurbo_EXIT:
1131 /* Set variables for next time. */
1132 precvpriv->bIsAnyNonBEPkts = false;
1133 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1134 precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1135 }
1136
