1#include <dt-bindings/interrupt-controller/mips-gic.h>
2
3/ {
4	#address-cells = <1>;
5	#size-cells = <1>;
6	compatible = "mediatek,mt7621-soc";
7
8	cpus {
9		cpu@0 {
10			compatible = "mips,mips1004Kc";
11		};
12
13		cpu@1 {
14			compatible = "mips,mips1004Kc";
15		};
16	};
17
18	cpuintc: cpuintc@0 {
19		#address-cells = <0>;
20		#interrupt-cells = <1>;
21		interrupt-controller;
22		compatible = "mti,cpu-interrupt-controller";
23	};
24
25	aliases {
26		serial0 = &uartlite;
27	};
28
29	cpuclock: cpuclock@0 {
30		#clock-cells = <0>;
31		compatible = "fixed-clock";
32
33		/* FIXME: there should be way to detect this */
34		clock-frequency = <880000000>;
35	};
36
37	sysclock: sysclock@0 {
38		#clock-cells = <0>;
39		compatible = "fixed-clock";
40
41		/* This is normally 1/4 of cpuclock */
42		clock-frequency = <220000000>;
43	};
44
45	palmbus: palmbus@1E000000 {
46		compatible = "palmbus";
47		reg = <0x1E000000 0x100000>;
48		ranges = <0x0 0x1E000000 0x0FFFFF>;
49
50		#address-cells = <1>;
51		#size-cells = <1>;
52
53		sysc: sysc@0 {
54			compatible = "mtk,mt7621-sysc";
55			reg = <0x0 0x100>;
56		};
57
58		wdt: wdt@100 {
59			compatible = "mtk,mt7621-wdt";
60			reg = <0x100 0x100>;
61		};
62
63		gpio: gpio@600 {
64			#gpio-cells = <2>;
65			#interrupt-cells = <2>;
66			compatible = "mediatek,mt7621-gpio";
67			gpio-controller;
68			interrupt-controller;
69			reg = <0x600 0x100>;
70			interrupt-parent = <&gic>;
71			interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
72		};
73
74		i2c: i2c@900 {
75			compatible = "mediatek,mt7621-i2c";
76			reg = <0x900 0x100>;
77
78			clocks = <&sysclock>;
79
80			resets = <&rstctrl 16>;
81			reset-names = "i2c";
82
83			#address-cells = <1>;
84			#size-cells = <0>;
85
86			status = "disabled";
87
88			pinctrl-names = "default";
89			pinctrl-0 = <&i2c_pins>;
90		};
91
92		i2s: i2s@a00 {
93			compatible = "mediatek,mt7621-i2s";
94			reg = <0xa00 0x100>;
95
96			clocks = <&sysclock>;
97
98			resets = <&rstctrl 17>;
99			reset-names = "i2s";
100
101			interrupt-parent = <&gic>;
102			interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
103
104			txdma-req = <2>;
105			rxdma-req = <3>;
106
107			dmas = <&gdma 4>,
108				<&gdma 6>;
109			dma-names = "tx", "rx";
110
111			status = "disabled";
112		};
113
114		memc: memc@5000 {
115			compatible = "mtk,mt7621-memc";
116			reg = <0x300 0x100>;
117		};
118
119		cpc: cpc@1fbf0000 {
120			     compatible = "mtk,mt7621-cpc";
121			     reg = <0x1fbf0000 0x8000>;
122		};
123
124		mc: mc@1fbf8000 {
125			    compatible = "mtk,mt7621-mc";
126			    reg = <0x1fbf8000 0x8000>;
127		};
128
129		uartlite: uartlite@c00 {
130			compatible = "ns16550a";
131			reg = <0xc00 0x100>;
132
133			clocks = <&sysclock>;
134			clock-frequency = <50000000>;
135
136			interrupt-parent = <&gic>;
137			interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
138
139			reg-shift = <2>;
140			reg-io-width = <4>;
141			no-loopback-test;
142		};
143
144		spi0: spi@b00 {
145			status = "disabled";
146
147			compatible = "ralink,mt7621-spi";
148			reg = <0xb00 0x100>;
149
150			clocks = <&sysclock>;
151
152			resets = <&rstctrl 18>;
153			reset-names = "spi";
154
155			#address-cells = <1>;
156			#size-cells = <0>;
157
158			pinctrl-names = "default";
159			pinctrl-0 = <&spi_pins>;
160		};
161
162		gdma: gdma@2800 {
163			compatible = "ralink,rt3883-gdma";
164			reg = <0x2800 0x800>;
165
166			resets = <&rstctrl 14>;
167			reset-names = "dma";
168
169			interrupt-parent = <&gic>;
170			interrupts = <0 13 4>;
171
172			#dma-cells = <1>;
173			#dma-channels = <16>;
174			#dma-requests = <16>;
175
176			status = "disabled";
177		};
178
179		hsdma: hsdma@7000 {
180			compatible = "mediatek,mt7621-hsdma";
181			reg = <0x7000 0x1000>;
182
183			resets = <&rstctrl 5>;
184			reset-names = "hsdma";
185
186			interrupt-parent = <&gic>;
187			interrupts = <0 11 4>;
188
189			#dma-cells = <1>;
190			#dma-channels = <1>;
191			#dma-requests = <1>;
192
193			status = "disabled";
194		};
195	};
196
197	pinctrl: pinctrl {
198		compatible = "ralink,rt2880-pinmux";
199		pinctrl-names = "default";
200		pinctrl-0 = <&state_default>;
201
202		state_default: pinctrl0 {
203		};
204
205		i2c_pins: i2c {
206			i2c {
207				group = "i2c";
208				function = "i2c";
209			};
210		};
211
212		spi_pins: spi {
213			spi {
214				group = "spi";
215				function = "spi";
216			};
217		};
218
219		uart1_pins: uart1 {
220			uart1 {
221				group = "uart1";
222				function = "uart1";
223			};
224		};
225
226		uart2_pins: uart2 {
227			uart2 {
228				group = "uart2";
229				function = "uart2";
230			};
231		};
232
233		uart3_pins: uart3 {
234			uart3 {
235				group = "uart3";
236				function = "uart3";
237			};
238		};
239
240		rgmii1_pins: rgmii1 {
241			rgmii1 {
242				group = "rgmii1";
243				function = "rgmii1";
244			};
245		};
246
247		rgmii2_pins: rgmii2 {
248			rgmii2 {
249				group = "rgmii2";
250				function = "rgmii2";
251			};
252		};
253
254		mdio_pins: mdio {
255			mdio {
256				group = "mdio";
257				function = "mdio";
258			};
259		};
260
261		pcie_pins: pcie {
262			pcie {
263				group = "pcie";
264				function = "pcie rst";
265			};
266		};
267
268		nand_pins: nand {
269			spi-nand {
270				group = "spi";
271				function = "nand1";
272			};
273
274			sdhci-nand {
275				group = "sdhci";
276				function = "nand2";
277			};
278		};
279
280		sdhci_pins: sdhci {
281			sdhci {
282				group = "sdhci";
283				function = "sdhci";
284			};
285		};
286	};
287
288	rstctrl: rstctrl {
289		compatible = "ralink,rt2880-reset";
290		#reset-cells = <1>;
291	};
292
293	clkctrl: clkctrl {
294		compatible = "ralink,rt2880-clock";
295		#clock-cells = <1>;
296	};
297
298	sdhci: sdhci@1E130000 {
299		status = "disabled";
300
301		compatible = "ralink,mt7620-sdhci";
302		reg = <0x1E130000 0x4000>;
303
304		interrupt-parent = <&gic>;
305		interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
306	};
307
308	xhci: xhci@1E1C0000 {
309		status = "okay";
310
311		compatible = "mediatek,mt8173-xhci";
312		reg = <0x1e1c0000 0x1000
313		       0x1e1d0700 0x0100>;
314		reg-names = "mac", "ippc";
315
316		clocks = <&sysclock>;
317		clock-names = "sys_ck";
318
319		interrupt-parent = <&gic>;
320		interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
321	};
322
323	gic: interrupt-controller@1fbc0000 {
324		compatible = "mti,gic";
325		reg = <0x1fbc0000 0x2000>;
326
327		interrupt-controller;
328		#interrupt-cells = <3>;
329
330		mti,reserved-cpu-vectors = <7>;
331
332		timer {
333			compatible = "mti,gic-timer";
334			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
335			clocks = <&cpuclock>;
336		};
337	};
338
339	nand: nand@1e003000 {
340		status = "disabled";
341
342		compatible = "mtk,mt7621-nand";
343		bank-width = <2>;
344		reg = <0x1e003000 0x800
345			0x1e003800 0x800>;
346		#address-cells = <1>;
347		#size-cells = <1>;
348	};
349
350	ethsys: syscon@1e000000 {
351		compatible = "mediatek,mt7621-ethsys",
352			     "syscon";
353		reg = <0x1e000000 0x1000>;
354		#clock-cells = <1>;
355	};
356
357	ethernet: ethernet@1e100000 {
358		compatible = "mediatek,mt7621-eth";
359		reg = <0x1e100000 0x10000>;
360
361		clocks = <&sysclock>;
362		clock-names = "ethif";
363
364		#address-cells = <1>;
365		#size-cells = <0>;
366
367		resets = <&rstctrl 6 &rstctrl 23>;
368		reset-names = "fe", "eth";
369
370		interrupt-parent = <&gic>;
371		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
372
373		mediatek,ethsys = <&ethsys>;
374
375		mediatek,switch = <&gsw>;
376
377		mdio-bus {
378			#address-cells = <1>;
379			#size-cells = <0>;
380
381			phy1f: ethernet-phy@1f {
382				reg = <0x1f>;
383				phy-mode = "rgmii";
384			};
385		};
386	};
387
388	gsw: gsw@1e110000 {
389		compatible = "mediatek,mt7621-gsw";
390		reg = <0x1e110000 0x8000>;
391		interrupt-parent = <&gic>;
392		interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
393	};
394
395	pcie: pcie@1e140000 {
396		compatible = "mediatek,mt7621-pci";
397		reg = <0x1e140000 0x100     /* host-pci bridge registers */
398			0x1e142000 0x100    /* pcie port 0 RC control registers */
399			0x1e143000 0x100    /* pcie port 1 RC control registers */
400			0x1e144000 0x100>;  /* pcie port 2 RC control registers */
401
402		#address-cells = <3>;
403		#size-cells = <2>;
404
405		pinctrl-names = "default";
406		pinctrl-0 = <&pcie_pins>;
407
408		device_type = "pci";
409
410		bus-range = <0 255>;
411		ranges = <
412			0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
413			0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
414		>;
415
416		#interrupt-cells = <1>;
417		interrupt-map-mask = <0xF0000 0 0 1>;
418		interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
419				<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
420				<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
421
422		status = "disabled";
423
424		resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
425		reset-names = "pcie0", "pcie1", "pcie2";
426		clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
427		clock-names = "pcie0", "pcie1", "pcie2";
428
429		pcie@0,0 {
430			reg = <0x0000 0 0 0 0>;
431			#address-cells = <3>;
432			#size-cells = <2>;
433			ranges;
434			bus-range = <0x00 0xff>;
435		};
436
437		pcie@1,0 {
438			reg = <0x0800 0 0 0 0>;
439			#address-cells = <3>;
440			#size-cells = <2>;
441			ranges;
442			bus-range = <0x00 0xff>;
443		};
444
445		pcie@2,0 {
446			reg = <0x1000 0 0 0 0>;
447			#address-cells = <3>;
448			#size-cells = <2>;
449			ranges;
450			bus-range = <0x00 0xff>;
451		};
452	};
453};
454