1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
3 * Copyright 2016 NXP
4 */
5
6 #ifndef __DPAA2_ETH_H
7 #define __DPAA2_ETH_H
8
9 #include <linux/netdevice.h>
10 #include <linux/if_vlan.h>
11 #include <linux/fsl/mc.h>
12
13 #include <soc/fsl/dpaa2-io.h>
14 #include <soc/fsl/dpaa2-fd.h>
15 #include "dpni.h"
16 #include "dpni-cmd.h"
17
18 #include "dpaa2-eth-trace.h"
19
20 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
21
22 #define DPAA2_ETH_STORE_SIZE 16
23
24 /* Maximum number of scatter-gather entries in an ingress frame,
25 * considering the maximum receive frame size is 64K
26 */
27 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
28
29 /* Maximum acceptable MTU value. It is in direct relation with the hardware
30 * enforced Max Frame Length (currently 10k).
31 */
32 #define DPAA2_ETH_MFL (10 * 1024)
33 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
34 /* Convert L3 MTU to L2 MFL */
35 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
36
37 /* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo
38 * frames in the Rx queues (length of the current frame is not
39 * taken into account when making the taildrop decision)
40 */
41 #define DPAA2_ETH_TAILDROP_THRESH (64 * 1024)
42
43 /* Buffer quota per queue. Must be large enough such that for minimum sized
44 * frames taildrop kicks in before the bpool gets depleted, so we compute
45 * how many 64B frames fit inside the taildrop threshold and add a margin
46 * to accommodate the buffer refill delay.
47 */
48 #define DPAA2_ETH_MAX_FRAMES_PER_QUEUE (DPAA2_ETH_TAILDROP_THRESH / 64)
49 #define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256)
50 #define DPAA2_ETH_REFILL_THRESH DPAA2_ETH_MAX_FRAMES_PER_QUEUE
51
52 /* Maximum number of buffers that can be acquired/released through a single
53 * QBMan command
54 */
55 #define DPAA2_ETH_BUFS_PER_CMD 7
56
57 /* Hardware requires alignment for ingress/egress buffer addresses */
58 #define DPAA2_ETH_TX_BUF_ALIGN 64
59
60 #define DPAA2_ETH_RX_BUF_SIZE 2048
61 #define DPAA2_ETH_SKB_SIZE \
62 (DPAA2_ETH_RX_BUF_SIZE + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
63
64 /* Hardware annotation area in RX/TX buffers */
65 #define DPAA2_ETH_RX_HWA_SIZE 64
66 #define DPAA2_ETH_TX_HWA_SIZE 128
67
68 /* PTP nominal frequency 1GHz */
69 #define DPAA2_PTP_CLK_PERIOD_NS 1
70
71 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
72 * to 256B. For newer revisions, the requirement is only for 64B alignment
73 */
74 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256
75 #define DPAA2_ETH_RX_BUF_ALIGN 64
76
77 /* We are accommodating a skb backpointer and some S/G info
78 * in the frame's software annotation. The hardware
79 * options are either 0 or 64, so we choose the latter.
80 */
81 #define DPAA2_ETH_SWA_SIZE 64
82
83 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
84 struct dpaa2_eth_swa {
85 struct sk_buff *skb;
86 struct scatterlist *scl;
87 int num_sg;
88 int sgt_size;
89 };
90
91 /* Annotation valid bits in FD FRC */
92 #define DPAA2_FD_FRC_FASV 0x8000
93 #define DPAA2_FD_FRC_FAEADV 0x4000
94 #define DPAA2_FD_FRC_FAPRV 0x2000
95 #define DPAA2_FD_FRC_FAIADV 0x1000
96 #define DPAA2_FD_FRC_FASWOV 0x0800
97 #define DPAA2_FD_FRC_FAICFDV 0x0400
98
99 /* Error bits in FD CTRL */
100 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR)
101 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \
102 FD_CTRL_SBE | \
103 FD_CTRL_FSE | \
104 FD_CTRL_FAERR)
105
106 /* Annotation bits in FD CTRL */
107 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */
108
109 /* Frame annotation status */
110 struct dpaa2_fas {
111 u8 reserved;
112 u8 ppid;
113 __le16 ifpid;
114 __le32 status;
115 };
116
117 /* Frame annotation status word is located in the first 8 bytes
118 * of the buffer's hardware annoatation area
119 */
120 #define DPAA2_FAS_OFFSET 0
121 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
122
123 /* Timestamp is located in the next 8 bytes of the buffer's
124 * hardware annotation area
125 */
126 #define DPAA2_TS_OFFSET 0x8
127
128 /* Frame annotation egress action descriptor */
129 #define DPAA2_FAEAD_OFFSET 0x58
130
131 struct dpaa2_faead {
132 __le32 conf_fqid;
133 __le32 ctrl;
134 };
135
136 #define DPAA2_FAEAD_A2V 0x20000000
137 #define DPAA2_FAEAD_UPDV 0x00001000
138 #define DPAA2_FAEAD_UPD 0x00000010
139
140 /* Accessors for the hardware annotation fields that we use */
dpaa2_get_hwa(void * buf_addr,bool swa)141 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
142 {
143 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
144 }
145
dpaa2_get_fas(void * buf_addr,bool swa)146 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
147 {
148 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
149 }
150
dpaa2_get_ts(void * buf_addr,bool swa)151 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa)
152 {
153 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
154 }
155
dpaa2_get_faead(void * buf_addr,bool swa)156 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
157 {
158 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
159 }
160
161 /* Error and status bits in the frame annotation status word */
162 /* Debug frame, otherwise supposed to be discarded */
163 #define DPAA2_FAS_DISC 0x80000000
164 /* MACSEC frame */
165 #define DPAA2_FAS_MS 0x40000000
166 #define DPAA2_FAS_PTP 0x08000000
167 /* Ethernet multicast frame */
168 #define DPAA2_FAS_MC 0x04000000
169 /* Ethernet broadcast frame */
170 #define DPAA2_FAS_BC 0x02000000
171 #define DPAA2_FAS_KSE 0x00040000
172 #define DPAA2_FAS_EOFHE 0x00020000
173 #define DPAA2_FAS_MNLE 0x00010000
174 #define DPAA2_FAS_TIDE 0x00008000
175 #define DPAA2_FAS_PIEE 0x00004000
176 /* Frame length error */
177 #define DPAA2_FAS_FLE 0x00002000
178 /* Frame physical error */
179 #define DPAA2_FAS_FPE 0x00001000
180 #define DPAA2_FAS_PTE 0x00000080
181 #define DPAA2_FAS_ISP 0x00000040
182 #define DPAA2_FAS_PHE 0x00000020
183 #define DPAA2_FAS_BLE 0x00000010
184 /* L3 csum validation performed */
185 #define DPAA2_FAS_L3CV 0x00000008
186 /* L3 csum error */
187 #define DPAA2_FAS_L3CE 0x00000004
188 /* L4 csum validation performed */
189 #define DPAA2_FAS_L4CV 0x00000002
190 /* L4 csum error */
191 #define DPAA2_FAS_L4CE 0x00000001
192 /* Possible errors on the ingress path */
193 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \
194 DPAA2_FAS_EOFHE | \
195 DPAA2_FAS_MNLE | \
196 DPAA2_FAS_TIDE | \
197 DPAA2_FAS_PIEE | \
198 DPAA2_FAS_FLE | \
199 DPAA2_FAS_FPE | \
200 DPAA2_FAS_PTE | \
201 DPAA2_FAS_ISP | \
202 DPAA2_FAS_PHE | \
203 DPAA2_FAS_BLE | \
204 DPAA2_FAS_L3CE | \
205 DPAA2_FAS_L4CE)
206
207 /* Time in milliseconds between link state updates */
208 #define DPAA2_ETH_LINK_STATE_REFRESH 1000
209
210 /* Number of times to retry a frame enqueue before giving up.
211 * Value determined empirically, in order to minimize the number
212 * of frames dropped on Tx
213 */
214 #define DPAA2_ETH_ENQUEUE_RETRIES 10
215
216 /* Driver statistics, other than those in struct rtnl_link_stats64.
217 * These are usually collected per-CPU and aggregated by ethtool.
218 */
219 struct dpaa2_eth_drv_stats {
220 __u64 tx_conf_frames;
221 __u64 tx_conf_bytes;
222 __u64 tx_sg_frames;
223 __u64 tx_sg_bytes;
224 __u64 tx_reallocs;
225 __u64 rx_sg_frames;
226 __u64 rx_sg_bytes;
227 /* Enqueues retried due to portal busy */
228 __u64 tx_portal_busy;
229 };
230
231 /* Per-FQ statistics */
232 struct dpaa2_eth_fq_stats {
233 /* Number of frames received on this queue */
234 __u64 frames;
235 };
236
237 /* Per-channel statistics */
238 struct dpaa2_eth_ch_stats {
239 /* Volatile dequeues retried due to portal busy */
240 __u64 dequeue_portal_busy;
241 /* Number of CDANs; useful to estimate avg NAPI len */
242 __u64 cdan;
243 /* Number of frames received on queues from this channel */
244 __u64 frames;
245 /* Pull errors */
246 __u64 pull_err;
247 };
248
249 /* Maximum number of queues associated with a DPNI */
250 #define DPAA2_ETH_MAX_RX_QUEUES 16
251 #define DPAA2_ETH_MAX_TX_QUEUES 16
252 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
253 DPAA2_ETH_MAX_TX_QUEUES)
254
255 #define DPAA2_ETH_MAX_DPCONS 16
256
257 enum dpaa2_eth_fq_type {
258 DPAA2_RX_FQ = 0,
259 DPAA2_TX_CONF_FQ,
260 };
261
262 struct dpaa2_eth_priv;
263
264 struct dpaa2_eth_fq {
265 u32 fqid;
266 u32 tx_qdbin;
267 u16 flowid;
268 int target_cpu;
269 struct dpaa2_eth_channel *channel;
270 enum dpaa2_eth_fq_type type;
271
272 void (*consume)(struct dpaa2_eth_priv *priv,
273 struct dpaa2_eth_channel *ch,
274 const struct dpaa2_fd *fd,
275 struct napi_struct *napi,
276 u16 queue_id);
277 struct dpaa2_eth_fq_stats stats;
278 };
279
280 struct dpaa2_eth_channel {
281 struct dpaa2_io_notification_ctx nctx;
282 struct fsl_mc_device *dpcon;
283 int dpcon_id;
284 int ch_id;
285 struct napi_struct napi;
286 struct dpaa2_io *dpio;
287 struct dpaa2_io_store *store;
288 struct dpaa2_eth_priv *priv;
289 int buf_count;
290 struct dpaa2_eth_ch_stats stats;
291 };
292
293 struct dpaa2_eth_hash_fields {
294 u64 rxnfc_field;
295 enum net_prot cls_prot;
296 int cls_field;
297 int size;
298 };
299
300 /* Driver private data */
301 struct dpaa2_eth_priv {
302 struct net_device *net_dev;
303
304 u8 num_fqs;
305 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
306
307 u8 num_channels;
308 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
309
310 struct dpni_attr dpni_attrs;
311 u16 dpni_ver_major;
312 u16 dpni_ver_minor;
313 u16 tx_data_offset;
314
315 struct fsl_mc_device *dpbp_dev;
316 u16 bpid;
317 struct iommu_domain *iommu_domain;
318
319 bool tx_tstamp; /* Tx timestamping enabled */
320 bool rx_tstamp; /* Rx timestamping enabled */
321
322 u16 tx_qdid;
323 u16 rx_buf_align;
324 struct fsl_mc_io *mc_io;
325 /* Cores which have an affine DPIO/DPCON.
326 * This is the cpu set on which Rx and Tx conf frames are processed
327 */
328 struct cpumask dpio_cpumask;
329
330 /* Standard statistics */
331 struct rtnl_link_stats64 __percpu *percpu_stats;
332 /* Extra stats, in addition to the ones known by the kernel */
333 struct dpaa2_eth_drv_stats __percpu *percpu_extras;
334
335 u16 mc_token;
336
337 struct dpni_link_state link_state;
338 bool do_link_poll;
339 struct task_struct *poll_thread;
340
341 /* enabled ethtool hashing bits */
342 u64 rx_hash_fields;
343 };
344
345 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
346 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
347 | RXH_L4_B_2_3)
348
349 /* default Rx hash options, set during probing */
350 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \
351 RXH_L4_B_0_1 | RXH_L4_B_2_3)
352
353 #define dpaa2_eth_hash_enabled(priv) \
354 ((priv)->dpni_attrs.num_queues > 1)
355
356 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
357 #define DPAA2_CLASSIFIER_DMA_SIZE 256
358
359 extern const struct ethtool_ops dpaa2_ethtool_ops;
360 extern int dpaa2_phc_index;
361
dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv * priv,u16 ver_major,u16 ver_minor)362 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
363 u16 ver_major, u16 ver_minor)
364 {
365 if (priv->dpni_ver_major == ver_major)
366 return priv->dpni_ver_minor - ver_minor;
367 return priv->dpni_ver_major - ver_major;
368 }
369
370 /* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but the skb built around
371 * the buffer also needs space for its shared info struct, and we need
372 * to allocate enough to accommodate hardware alignment restrictions
373 */
dpaa2_eth_buf_raw_size(struct dpaa2_eth_priv * priv)374 static inline unsigned int dpaa2_eth_buf_raw_size(struct dpaa2_eth_priv *priv)
375 {
376 return DPAA2_ETH_SKB_SIZE + priv->rx_buf_align;
377 }
378
379 static inline
dpaa2_eth_needed_headroom(struct dpaa2_eth_priv * priv,struct sk_buff * skb)380 unsigned int dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv,
381 struct sk_buff *skb)
382 {
383 unsigned int headroom = DPAA2_ETH_SWA_SIZE;
384
385 /* For non-linear skbs we have no headroom requirement, as we build a
386 * SG frame with a newly allocated SGT buffer
387 */
388 if (skb_is_nonlinear(skb))
389 return 0;
390
391 /* If we have Tx timestamping, need 128B hardware annotation */
392 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
393 headroom += DPAA2_ETH_TX_HWA_SIZE;
394
395 return headroom;
396 }
397
398 /* Extra headroom space requested to hardware, in order to make sure there's
399 * no realloc'ing in forwarding scenarios
400 */
dpaa2_eth_rx_head_room(struct dpaa2_eth_priv * priv)401 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv)
402 {
403 return priv->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN -
404 DPAA2_ETH_RX_HWA_SIZE;
405 }
406
dpaa2_eth_queue_count(struct dpaa2_eth_priv * priv)407 static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv)
408 {
409 return priv->dpni_attrs.num_queues;
410 }
411
412 #endif /* __DPAA2_H */
413
