1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2003 Digi International (www.digi.com) 4 * Scott H Kilau <Scott_Kilau at digi dot com> 5 */ 6 7 #ifndef _DGNC_CLS_H 8 #define _DGNC_CLS_H 9 10 /** 11 * struct cls_uart_struct - Per channel/port Classic UART. 12 * 13 * key - W = read write 14 * - R = read only 15 * - U = unused 16 * 17 * @txrx: (WR) Holding Register. 18 * @ier: (WR) Interrupt Enable Register. 19 * @isr_fcr: (WR) Interrupt Status Register/Fifo Control Register. 20 * @lcr: (WR) Line Control Register. 21 * @mcr: (WR) Modem Control Register. 22 * @lsr: (WR) Line Status Register. 23 * @msr: (WR) Modem Status Register. 24 * @spr: (WR) Scratch Pad Register. 25 */ 26 struct cls_uart_struct { 27 u8 txrx; 28 u8 ier; 29 u8 isr_fcr; 30 u8 lcr; 31 u8 mcr; 32 u8 lsr; 33 u8 msr; 34 u8 spr; 35 }; 36 37 /* Where to read the interrupt register (8bits) */ 38 #define UART_CLASSIC_POLL_ADDR_OFFSET 0x40 39 40 #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF 41 42 #define UART_16654_FCR_TXTRIGGER_16 0x10 43 #define UART_16654_FCR_RXTRIGGER_16 0x40 44 #define UART_16654_FCR_RXTRIGGER_56 0x80 45 46 /* Received CTS/RTS change of state */ 47 #define UART_IIR_CTSRTS 0x20 48 49 /* Receiver data TIMEOUT */ 50 #define UART_IIR_RDI_TIMEOUT 0x0C 51 52 /* 53 * These are the EXTENDED definitions for the Exar 654's Interrupt 54 * Enable Register. 55 */ 56 #define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */ 57 #define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ 58 #define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ 59 #define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ 60 #define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow Control Enable */ 61 #define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */ 62 #define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */ 63 #define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */ 64 65 extern struct board_ops dgnc_cls_ops; 66 67 #endif /* _DGNC_CLS_H */ 68
