1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2003 Digi International (www.digi.com)
4 * Scott H Kilau <Scott_Kilau at digi dot com>
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/serial.h>
13 #include <linux/serial_reg.h>
14 #include <linux/pci.h>
15
16 #include "dgnc_driver.h"
17 #include "dgnc_cls.h"
18 #include "dgnc_tty.h"
19
cls_set_cts_flow_control(struct channel_t * ch)20 static inline void cls_set_cts_flow_control(struct channel_t *ch)
21 {
22 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
23 unsigned char ier = readb(&ch->ch_cls_uart->ier);
24 unsigned char isr_fcr = 0;
25
26 /*
27 * The Enhanced Register Set may only be accessed when
28 * the Line Control Register is set to 0xBFh.
29 */
30 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
31
32 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
33
34 /* Turn on CTS flow control, turn off IXON flow control */
35 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
36 isr_fcr &= ~(UART_EXAR654_EFR_IXON);
37
38 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
39
40 /* Write old LCR value back out, which turns enhanced access off */
41 writeb(lcrb, &ch->ch_cls_uart->lcr);
42
43 /*
44 * Enable interrupts for CTS flow, turn off interrupts for
45 * received XOFF chars
46 */
47 ier |= (UART_EXAR654_IER_CTSDSR);
48 ier &= ~(UART_EXAR654_IER_XOFF);
49 writeb(ier, &ch->ch_cls_uart->ier);
50
51 /* Set the usual FIFO values */
52 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
53
54 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
55 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
56 &ch->ch_cls_uart->isr_fcr);
57
58 ch->ch_t_tlevel = 16;
59 }
60
cls_set_ixon_flow_control(struct channel_t * ch)61 static inline void cls_set_ixon_flow_control(struct channel_t *ch)
62 {
63 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
64 unsigned char ier = readb(&ch->ch_cls_uart->ier);
65 unsigned char isr_fcr = 0;
66
67 /*
68 * The Enhanced Register Set may only be accessed when
69 * the Line Control Register is set to 0xBFh.
70 */
71 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
72
73 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
74
75 /* Turn on IXON flow control, turn off CTS flow control */
76 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
77 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
78
79 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
80
81 /* Now set our current start/stop chars while in enhanced mode */
82 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
83 writeb(0, &ch->ch_cls_uart->lsr);
84 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
85 writeb(0, &ch->ch_cls_uart->spr);
86
87 /* Write old LCR value back out, which turns enhanced access off */
88 writeb(lcrb, &ch->ch_cls_uart->lcr);
89
90 /*
91 * Disable interrupts for CTS flow, turn on interrupts for
92 * received XOFF chars
93 */
94 ier &= ~(UART_EXAR654_IER_CTSDSR);
95 ier |= (UART_EXAR654_IER_XOFF);
96 writeb(ier, &ch->ch_cls_uart->ier);
97
98 /* Set the usual FIFO values */
99 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
100
101 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
102 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
103 &ch->ch_cls_uart->isr_fcr);
104 }
105
cls_set_no_output_flow_control(struct channel_t * ch)106 static inline void cls_set_no_output_flow_control(struct channel_t *ch)
107 {
108 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
109 unsigned char ier = readb(&ch->ch_cls_uart->ier);
110 unsigned char isr_fcr = 0;
111
112 /*
113 * The Enhanced Register Set may only be accessed when
114 * the Line Control Register is set to 0xBFh.
115 */
116 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
117
118 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
119
120 /* Turn off IXON flow control, turn off CTS flow control */
121 isr_fcr |= (UART_EXAR654_EFR_ECB);
122 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
123
124 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
125
126 /* Write old LCR value back out, which turns enhanced access off */
127 writeb(lcrb, &ch->ch_cls_uart->lcr);
128
129 /*
130 * Disable interrupts for CTS flow, turn off interrupts for
131 * received XOFF chars
132 */
133 ier &= ~(UART_EXAR654_IER_CTSDSR);
134 ier &= ~(UART_EXAR654_IER_XOFF);
135 writeb(ier, &ch->ch_cls_uart->ier);
136
137 /* Set the usual FIFO values */
138 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
139
140 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
141 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
142 &ch->ch_cls_uart->isr_fcr);
143
144 ch->ch_r_watermark = 0;
145 ch->ch_t_tlevel = 16;
146 ch->ch_r_tlevel = 16;
147 }
148
cls_set_rts_flow_control(struct channel_t * ch)149 static inline void cls_set_rts_flow_control(struct channel_t *ch)
150 {
151 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
152 unsigned char ier = readb(&ch->ch_cls_uart->ier);
153 unsigned char isr_fcr = 0;
154
155 /*
156 * The Enhanced Register Set may only be accessed when
157 * the Line Control Register is set to 0xBFh.
158 */
159 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
160
161 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
162
163 /* Turn on RTS flow control, turn off IXOFF flow control */
164 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
165 isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
166
167 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
168
169 /* Write old LCR value back out, which turns enhanced access off */
170 writeb(lcrb, &ch->ch_cls_uart->lcr);
171
172 /* Enable interrupts for RTS flow */
173 ier |= (UART_EXAR654_IER_RTSDTR);
174 writeb(ier, &ch->ch_cls_uart->ier);
175
176 /* Set the usual FIFO values */
177 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
178
179 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
180 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
181 &ch->ch_cls_uart->isr_fcr);
182
183 ch->ch_r_watermark = 4;
184 ch->ch_r_tlevel = 8;
185 }
186
cls_set_ixoff_flow_control(struct channel_t * ch)187 static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
188 {
189 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
190 unsigned char ier = readb(&ch->ch_cls_uart->ier);
191 unsigned char isr_fcr = 0;
192
193 /*
194 * The Enhanced Register Set may only be accessed when
195 * the Line Control Register is set to 0xBFh.
196 */
197 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
198
199 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
200
201 /* Turn on IXOFF flow control, turn off RTS flow control */
202 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
203 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
204
205 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
206
207 /* Now set our current start/stop chars while in enhanced mode */
208 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
209 writeb(0, &ch->ch_cls_uart->lsr);
210 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
211 writeb(0, &ch->ch_cls_uart->spr);
212
213 /* Write old LCR value back out, which turns enhanced access off */
214 writeb(lcrb, &ch->ch_cls_uart->lcr);
215
216 /* Disable interrupts for RTS flow */
217 ier &= ~(UART_EXAR654_IER_RTSDTR);
218 writeb(ier, &ch->ch_cls_uart->ier);
219
220 /* Set the usual FIFO values */
221 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
222
223 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
224 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
225 &ch->ch_cls_uart->isr_fcr);
226 }
227
cls_set_no_input_flow_control(struct channel_t * ch)228 static inline void cls_set_no_input_flow_control(struct channel_t *ch)
229 {
230 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
231 unsigned char ier = readb(&ch->ch_cls_uart->ier);
232 unsigned char isr_fcr = 0;
233
234 /*
235 * The Enhanced Register Set may only be accessed when
236 * the Line Control Register is set to 0xBFh.
237 */
238 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
239
240 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
241
242 /* Turn off IXOFF flow control, turn off RTS flow control */
243 isr_fcr |= (UART_EXAR654_EFR_ECB);
244 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
245
246 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
247
248 /* Write old LCR value back out, which turns enhanced access off */
249 writeb(lcrb, &ch->ch_cls_uart->lcr);
250
251 /* Disable interrupts for RTS flow */
252 ier &= ~(UART_EXAR654_IER_RTSDTR);
253 writeb(ier, &ch->ch_cls_uart->ier);
254
255 /* Set the usual FIFO values */
256 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
257
258 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
259 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
260 &ch->ch_cls_uart->isr_fcr);
261
262 ch->ch_t_tlevel = 16;
263 ch->ch_r_tlevel = 16;
264 }
265
266 /*
267 * Determines whether its time to shut off break condition.
268 *
269 * No locks are assumed to be held when calling this function.
270 * channel lock is held and released in this function.
271 */
cls_clear_break(struct channel_t * ch,int force)272 static inline void cls_clear_break(struct channel_t *ch, int force)
273 {
274 unsigned long flags;
275
276 if (!ch)
277 return;
278
279 spin_lock_irqsave(&ch->ch_lock, flags);
280
281 if (!ch->ch_stop_sending_break) {
282 spin_unlock_irqrestore(&ch->ch_lock, flags);
283 return;
284 }
285
286 /* Turn break off, and unset some variables */
287 if (ch->ch_flags & CH_BREAK_SENDING) {
288 if (time_after(jiffies, ch->ch_stop_sending_break) || force) {
289 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
290
291 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
292 ch->ch_flags &= ~(CH_BREAK_SENDING);
293 ch->ch_stop_sending_break = 0;
294 }
295 }
296 spin_unlock_irqrestore(&ch->ch_lock, flags);
297 }
298
cls_copy_data_from_uart_to_queue(struct channel_t * ch)299 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
300 {
301 int qleft = 0;
302 unsigned char linestatus = 0;
303 unsigned char error_mask = 0;
304 ushort head;
305 ushort tail;
306 unsigned long flags;
307
308 if (!ch)
309 return;
310
311 spin_lock_irqsave(&ch->ch_lock, flags);
312
313 head = ch->ch_r_head;
314 tail = ch->ch_r_tail;
315
316 qleft = tail - head - 1;
317 if (qleft < 0)
318 qleft += RQUEUEMASK + 1;
319
320 /*
321 * Create a mask to determine whether we should
322 * insert the character (if any) into our queue.
323 */
324 if (ch->ch_c_iflag & IGNBRK)
325 error_mask |= UART_LSR_BI;
326
327 while (1) {
328 linestatus = readb(&ch->ch_cls_uart->lsr);
329
330 if (!(linestatus & (UART_LSR_DR)))
331 break;
332
333 /* Discard character if we are ignoring the error mask. */
334 if (linestatus & error_mask) {
335 linestatus = 0;
336 readb(&ch->ch_cls_uart->txrx);
337 continue;
338 }
339
340 /*
341 * If our queue is full, we have no choice but to drop some
342 * data. The assumption is that HWFLOW or SWFLOW should have
343 * stopped things way way before we got to this point.
344 */
345 while (qleft < 1) {
346 tail = (tail + 1) & RQUEUEMASK;
347 ch->ch_r_tail = tail;
348 ch->ch_err_overrun++;
349 qleft++;
350 }
351
352 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
353 | UART_LSR_FE);
354 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
355
356 qleft--;
357
358 if (ch->ch_equeue[head] & UART_LSR_PE)
359 ch->ch_err_parity++;
360 if (ch->ch_equeue[head] & UART_LSR_BI)
361 ch->ch_err_break++;
362 if (ch->ch_equeue[head] & UART_LSR_FE)
363 ch->ch_err_frame++;
364
365 head = (head + 1) & RQUEUEMASK;
366 ch->ch_rxcount++;
367 }
368
369 ch->ch_r_head = head & RQUEUEMASK;
370 ch->ch_e_head = head & EQUEUEMASK;
371
372 spin_unlock_irqrestore(&ch->ch_lock, flags);
373 }
374
375 /* Make the UART raise any of the output signals we want up */
cls_assert_modem_signals(struct channel_t * ch)376 static void cls_assert_modem_signals(struct channel_t *ch)
377 {
378 unsigned char out;
379
380 if (!ch)
381 return;
382
383 out = ch->ch_mostat;
384
385 if (ch->ch_flags & CH_LOOPBACK)
386 out |= UART_MCR_LOOP;
387
388 writeb(out, &ch->ch_cls_uart->mcr);
389
390 /* Give time for the UART to actually drop the signals */
391 usleep_range(10, 20);
392 }
393
cls_copy_data_from_queue_to_uart(struct channel_t * ch)394 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
395 {
396 ushort head;
397 ushort tail;
398 int n;
399 int qlen;
400 uint len_written = 0;
401 unsigned long flags;
402
403 if (!ch)
404 return;
405
406 spin_lock_irqsave(&ch->ch_lock, flags);
407
408 if (ch->ch_w_tail == ch->ch_w_head)
409 goto exit_unlock;
410
411 /* If port is "stopped", don't send any data to the UART */
412 if ((ch->ch_flags & CH_FORCED_STOP) ||
413 (ch->ch_flags & CH_BREAK_SENDING))
414 goto exit_unlock;
415
416 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
417 goto exit_unlock;
418
419 n = 32;
420
421 head = ch->ch_w_head & WQUEUEMASK;
422 tail = ch->ch_w_tail & WQUEUEMASK;
423 qlen = (head - tail) & WQUEUEMASK;
424
425 n = min(n, qlen);
426
427 while (n > 0) {
428 /*
429 * If RTS Toggle mode is on, turn on RTS now if not already set,
430 * and make sure we get an event when the data transfer has
431 * completed.
432 */
433 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
434 if (!(ch->ch_mostat & UART_MCR_RTS)) {
435 ch->ch_mostat |= (UART_MCR_RTS);
436 cls_assert_modem_signals(ch);
437 }
438 ch->ch_tun.un_flags |= (UN_EMPTY);
439 }
440
441 /*
442 * If DTR Toggle mode is on, turn on DTR now if not already set,
443 * and make sure we get an event when the data transfer has
444 * completed.
445 */
446 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
447 if (!(ch->ch_mostat & UART_MCR_DTR)) {
448 ch->ch_mostat |= (UART_MCR_DTR);
449 cls_assert_modem_signals(ch);
450 }
451 ch->ch_tun.un_flags |= (UN_EMPTY);
452 }
453 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
454 ch->ch_w_tail++;
455 ch->ch_w_tail &= WQUEUEMASK;
456 ch->ch_txcount++;
457 len_written++;
458 n--;
459 }
460
461 if (len_written > 0)
462 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
463
464 exit_unlock:
465 spin_unlock_irqrestore(&ch->ch_lock, flags);
466 }
467
cls_parse_modem(struct channel_t * ch,unsigned char signals)468 static void cls_parse_modem(struct channel_t *ch, unsigned char signals)
469 {
470 unsigned char msignals = signals;
471 unsigned long flags;
472
473 if (!ch)
474 return;
475
476 /*
477 * Do altpin switching. Altpin switches DCD and DSR.
478 * This prolly breaks DSRPACE, so we should be more clever here.
479 */
480 spin_lock_irqsave(&ch->ch_lock, flags);
481 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
482 unsigned char mswap = signals;
483
484 if (mswap & UART_MSR_DDCD) {
485 msignals &= ~UART_MSR_DDCD;
486 msignals |= UART_MSR_DDSR;
487 }
488 if (mswap & UART_MSR_DDSR) {
489 msignals &= ~UART_MSR_DDSR;
490 msignals |= UART_MSR_DDCD;
491 }
492 if (mswap & UART_MSR_DCD) {
493 msignals &= ~UART_MSR_DCD;
494 msignals |= UART_MSR_DSR;
495 }
496 if (mswap & UART_MSR_DSR) {
497 msignals &= ~UART_MSR_DSR;
498 msignals |= UART_MSR_DCD;
499 }
500 }
501 spin_unlock_irqrestore(&ch->ch_lock, flags);
502
503 /* Scrub off lower bits. They signify delta's */
504 signals &= 0xf0;
505
506 spin_lock_irqsave(&ch->ch_lock, flags);
507 if (msignals & UART_MSR_DCD)
508 ch->ch_mistat |= UART_MSR_DCD;
509 else
510 ch->ch_mistat &= ~UART_MSR_DCD;
511
512 if (msignals & UART_MSR_DSR)
513 ch->ch_mistat |= UART_MSR_DSR;
514 else
515 ch->ch_mistat &= ~UART_MSR_DSR;
516
517 if (msignals & UART_MSR_RI)
518 ch->ch_mistat |= UART_MSR_RI;
519 else
520 ch->ch_mistat &= ~UART_MSR_RI;
521
522 if (msignals & UART_MSR_CTS)
523 ch->ch_mistat |= UART_MSR_CTS;
524 else
525 ch->ch_mistat &= ~UART_MSR_CTS;
526 spin_unlock_irqrestore(&ch->ch_lock, flags);
527 }
528
529 /* Parse the ISR register for the specific port */
cls_parse_isr(struct dgnc_board * brd,uint port)530 static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
531 {
532 struct channel_t *ch;
533 unsigned char isr = 0;
534 unsigned long flags;
535
536 /*
537 * No need to verify board pointer, it was already
538 * verified in the interrupt routine.
539 */
540
541 if (port >= brd->nasync)
542 return;
543
544 ch = brd->channels[port];
545
546 /* Here we try to figure out what caused the interrupt to happen */
547 while (1) {
548 isr = readb(&ch->ch_cls_uart->isr_fcr);
549
550 if (isr & UART_IIR_NO_INT)
551 break;
552
553 /* Receive Interrupt pending */
554 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
555 cls_copy_data_from_uart_to_queue(ch);
556 dgnc_check_queue_flow_control(ch);
557 }
558
559 /* Transmit Hold register empty pending */
560 if (isr & UART_IIR_THRI) {
561 spin_lock_irqsave(&ch->ch_lock, flags);
562 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
563 spin_unlock_irqrestore(&ch->ch_lock, flags);
564 cls_copy_data_from_queue_to_uart(ch);
565 }
566
567 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
568 }
569 }
570
571 /* Channel lock MUST be held before calling this function! */
cls_flush_uart_write(struct channel_t * ch)572 static void cls_flush_uart_write(struct channel_t *ch)
573 {
574 if (!ch)
575 return;
576
577 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
578 &ch->ch_cls_uart->isr_fcr);
579
580 /* Must use *delay family functions in atomic context */
581 udelay(10);
582
583 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
584 }
585
586 /* Channel lock MUST be held before calling this function! */
cls_flush_uart_read(struct channel_t * ch)587 static void cls_flush_uart_read(struct channel_t *ch)
588 {
589 if (!ch)
590 return;
591
592 /*
593 * For complete POSIX compatibility, we should be purging the
594 * read FIFO in the UART here.
595 *
596 * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
597 * incorrectly flushes write data as well as just basically trashing the
598 * FIFO.
599 *
600 * Presumably, this is a bug in this UART.
601 */
602
603 udelay(10);
604 }
605
606 /* Send any/all changes to the line to the UART. */
cls_param(struct tty_struct * tty)607 static void cls_param(struct tty_struct *tty)
608 {
609 unsigned char lcr = 0;
610 unsigned char uart_lcr = 0;
611 unsigned char ier = 0;
612 unsigned char uart_ier = 0;
613 uint baud = 9600;
614 int quot = 0;
615 struct dgnc_board *bd;
616 struct channel_t *ch;
617 struct un_t *un;
618
619 if (!tty)
620 return;
621
622 un = (struct un_t *)tty->driver_data;
623 if (!un)
624 return;
625
626 ch = un->un_ch;
627 if (!ch)
628 return;
629
630 bd = ch->ch_bd;
631 if (!bd)
632 return;
633
634 /* If baud rate is zero, flush queues, and set mval to drop DTR. */
635 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
636 ch->ch_r_head = 0;
637 ch->ch_r_tail = 0;
638 ch->ch_e_head = 0;
639 ch->ch_e_tail = 0;
640 ch->ch_w_head = 0;
641 ch->ch_w_tail = 0;
642
643 cls_flush_uart_write(ch);
644 cls_flush_uart_read(ch);
645
646 /* The baudrate is B0 so all modem lines are to be dropped. */
647 ch->ch_flags |= (CH_BAUD0);
648 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
649 cls_assert_modem_signals(ch);
650 ch->ch_old_baud = 0;
651 return;
652 } else if (ch->ch_custom_speed) {
653 baud = ch->ch_custom_speed;
654 /* Handle transition from B0 */
655 if (ch->ch_flags & CH_BAUD0) {
656 ch->ch_flags &= ~(CH_BAUD0);
657
658 /*
659 * Bring back up RTS and DTR...
660 * Also handle RTS or DTR toggle if set.
661 */
662 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
663 ch->ch_mostat |= (UART_MCR_RTS);
664 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
665 ch->ch_mostat |= (UART_MCR_DTR);
666 }
667
668 } else {
669 int iindex = 0;
670 int jindex = 0;
671
672 ulong bauds[4][16] = {
673 { /* slowbaud */
674 0, 50, 75, 110,
675 134, 150, 200, 300,
676 600, 1200, 1800, 2400,
677 4800, 9600, 19200, 38400 },
678 { /* slowbaud & CBAUDEX */
679 0, 57600, 115200, 230400,
680 460800, 150, 200, 921600,
681 600, 1200, 1800, 2400,
682 4800, 9600, 19200, 38400 },
683 { /* fastbaud */
684 0, 57600, 76800, 115200,
685 131657, 153600, 230400, 460800,
686 921600, 1200, 1800, 2400,
687 4800, 9600, 19200, 38400 },
688 { /* fastbaud & CBAUDEX */
689 0, 57600, 115200, 230400,
690 460800, 150, 200, 921600,
691 600, 1200, 1800, 2400,
692 4800, 9600, 19200, 38400 }
693 };
694
695 /*
696 * Only use the TXPrint baud rate if the terminal
697 * unit is NOT open
698 */
699 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
700 (un->un_type == DGNC_PRINT))
701 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
702 else
703 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
704
705 if (ch->ch_c_cflag & CBAUDEX)
706 iindex = 1;
707
708 if (ch->ch_digi.digi_flags & DIGI_FAST)
709 iindex += 2;
710
711 jindex = baud;
712
713 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) &&
714 (jindex < 16)) {
715 baud = bauds[iindex][jindex];
716 } else {
717 baud = 0;
718 }
719
720 if (baud == 0)
721 baud = 9600;
722
723 /* Handle transition from B0 */
724 if (ch->ch_flags & CH_BAUD0) {
725 ch->ch_flags &= ~(CH_BAUD0);
726
727 /*
728 * Bring back up RTS and DTR...
729 * Also handle RTS or DTR toggle if set.
730 */
731 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
732 ch->ch_mostat |= (UART_MCR_RTS);
733 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
734 ch->ch_mostat |= (UART_MCR_DTR);
735 }
736 }
737
738 if (ch->ch_c_cflag & PARENB)
739 lcr |= UART_LCR_PARITY;
740
741 if (!(ch->ch_c_cflag & PARODD))
742 lcr |= UART_LCR_EPAR;
743
744 #ifdef CMSPAR
745 if (ch->ch_c_cflag & CMSPAR)
746 lcr |= UART_LCR_SPAR;
747 #endif
748
749 if (ch->ch_c_cflag & CSTOPB)
750 lcr |= UART_LCR_STOP;
751
752 switch (ch->ch_c_cflag & CSIZE) {
753 case CS5:
754 lcr |= UART_LCR_WLEN5;
755 break;
756 case CS6:
757 lcr |= UART_LCR_WLEN6;
758 break;
759 case CS7:
760 lcr |= UART_LCR_WLEN7;
761 break;
762 case CS8:
763 default:
764 lcr |= UART_LCR_WLEN8;
765 break;
766 }
767
768 uart_ier = readb(&ch->ch_cls_uart->ier);
769 ier = uart_ier;
770 uart_lcr = readb(&ch->ch_cls_uart->lcr);
771
772 if (baud == 0)
773 baud = 9600;
774
775 quot = ch->ch_bd->bd_dividend / baud;
776
777 if (quot != 0 && ch->ch_old_baud != baud) {
778 ch->ch_old_baud = baud;
779 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
780 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
781 writeb((quot >> 8), &ch->ch_cls_uart->ier);
782 writeb(lcr, &ch->ch_cls_uart->lcr);
783 }
784
785 if (uart_lcr != lcr)
786 writeb(lcr, &ch->ch_cls_uart->lcr);
787
788 if (ch->ch_c_cflag & CREAD)
789 ier |= (UART_IER_RDI | UART_IER_RLSI);
790 else
791 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
792
793 /*
794 * Have the UART interrupt on modem signal changes ONLY when
795 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
796 */
797 if ((ch->ch_digi.digi_flags & CTSPACE) ||
798 (ch->ch_digi.digi_flags & RTSPACE) ||
799 (ch->ch_c_cflag & CRTSCTS) ||
800 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
801 !(ch->ch_c_cflag & CLOCAL))
802 ier |= UART_IER_MSI;
803 else
804 ier &= ~UART_IER_MSI;
805
806 ier |= UART_IER_THRI;
807
808 if (ier != uart_ier)
809 writeb(ier, &ch->ch_cls_uart->ier);
810
811 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
812 cls_set_cts_flow_control(ch);
813 } else if (ch->ch_c_iflag & IXON) {
814 if ((ch->ch_startc == _POSIX_VDISABLE) ||
815 (ch->ch_stopc == _POSIX_VDISABLE))
816 cls_set_no_output_flow_control(ch);
817 else
818 cls_set_ixon_flow_control(ch);
819 } else {
820 cls_set_no_output_flow_control(ch);
821 }
822
823 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
824 cls_set_rts_flow_control(ch);
825 } else if (ch->ch_c_iflag & IXOFF) {
826 if ((ch->ch_startc == _POSIX_VDISABLE) ||
827 (ch->ch_stopc == _POSIX_VDISABLE))
828 cls_set_no_input_flow_control(ch);
829 else
830 cls_set_ixoff_flow_control(ch);
831 } else {
832 cls_set_no_input_flow_control(ch);
833 }
834
835 cls_assert_modem_signals(ch);
836
837 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
838 }
839
840 /* Board poller function. */
cls_tasklet(unsigned long data)841 static void cls_tasklet(unsigned long data)
842 {
843 struct dgnc_board *bd = (struct dgnc_board *)data;
844 struct channel_t *ch;
845 unsigned long flags;
846 int i;
847 int state = 0;
848 int ports = 0;
849
850 if (!bd)
851 return;
852
853 spin_lock_irqsave(&bd->bd_lock, flags);
854 state = bd->state;
855 ports = bd->nasync;
856 spin_unlock_irqrestore(&bd->bd_lock, flags);
857
858 /*
859 * Do NOT allow the interrupt routine to read the intr registers
860 * Until we release this lock.
861 */
862 spin_lock_irqsave(&bd->bd_intr_lock, flags);
863
864 if ((state == BOARD_READY) && (ports > 0)) {
865 for (i = 0; i < ports; i++) {
866 ch = bd->channels[i];
867
868 /*
869 * NOTE: Remember you CANNOT hold any channel
870 * locks when calling input.
871 * During input processing, its possible we
872 * will call ld, which might do callbacks back
873 * into us.
874 */
875 dgnc_input(ch);
876
877 /*
878 * Channel lock is grabbed and then released
879 * inside this routine.
880 */
881 cls_copy_data_from_queue_to_uart(ch);
882 dgnc_wakeup_writes(ch);
883
884 dgnc_carrier(ch);
885
886 /*
887 * The timing check of turning off the break is done
888 * inside clear_break()
889 */
890 if (ch->ch_stop_sending_break)
891 cls_clear_break(ch, 0);
892 }
893 }
894
895 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
896 }
897
898 /* Classic specific interrupt handler. */
cls_intr(int irq,void * voidbrd)899 static irqreturn_t cls_intr(int irq, void *voidbrd)
900 {
901 struct dgnc_board *brd = voidbrd;
902 uint i = 0;
903 unsigned char poll_reg;
904 unsigned long flags;
905
906 if (!brd)
907 return IRQ_NONE;
908
909 spin_lock_irqsave(&brd->bd_intr_lock, flags);
910
911 poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
912 if (!poll_reg) {
913 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
914 return IRQ_NONE;
915 }
916
917 for (i = 0; i < brd->nasync; i++)
918 cls_parse_isr(brd, i);
919
920 tasklet_schedule(&brd->helper_tasklet);
921
922 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
923
924 return IRQ_HANDLED;
925 }
926
cls_disable_receiver(struct channel_t * ch)927 static void cls_disable_receiver(struct channel_t *ch)
928 {
929 unsigned char tmp = readb(&ch->ch_cls_uart->ier);
930
931 tmp &= ~(UART_IER_RDI);
932 writeb(tmp, &ch->ch_cls_uart->ier);
933 }
934
cls_enable_receiver(struct channel_t * ch)935 static void cls_enable_receiver(struct channel_t *ch)
936 {
937 unsigned char tmp = readb(&ch->ch_cls_uart->ier);
938
939 tmp |= (UART_IER_RDI);
940 writeb(tmp, &ch->ch_cls_uart->ier);
941 }
942
943 /*
944 * This function basically goes to sleep for seconds, or until
945 * it gets signalled that the port has fully drained.
946 */
cls_drain(struct tty_struct * tty,uint seconds)947 static int cls_drain(struct tty_struct *tty, uint seconds)
948 {
949 unsigned long flags;
950 struct channel_t *ch;
951 struct un_t *un;
952
953 if (!tty)
954 return -ENXIO;
955
956 un = (struct un_t *)tty->driver_data;
957 if (!un)
958 return -ENXIO;
959
960 ch = un->un_ch;
961 if (!ch)
962 return -ENXIO;
963
964 spin_lock_irqsave(&ch->ch_lock, flags);
965 un->un_flags |= UN_EMPTY;
966 spin_unlock_irqrestore(&ch->ch_lock, flags);
967
968 /* NOTE: Do something with time passed in. */
969
970 /* If ret is non-zero, user ctrl-c'ed us */
971
972 return wait_event_interruptible(un->un_flags_wait,
973 ((un->un_flags & UN_EMPTY) == 0));
974 }
975
cls_send_start_character(struct channel_t * ch)976 static void cls_send_start_character(struct channel_t *ch)
977 {
978 if (!ch)
979 return;
980
981 if (ch->ch_startc != _POSIX_VDISABLE) {
982 ch->ch_xon_sends++;
983 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
984 }
985 }
986
cls_send_stop_character(struct channel_t * ch)987 static void cls_send_stop_character(struct channel_t *ch)
988 {
989 if (!ch)
990 return;
991
992 if (ch->ch_stopc != _POSIX_VDISABLE) {
993 ch->ch_xoff_sends++;
994 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
995 }
996 }
997
cls_uart_init(struct channel_t * ch)998 static void cls_uart_init(struct channel_t *ch)
999 {
1000 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
1001 unsigned char isr_fcr = 0;
1002
1003 writeb(0, &ch->ch_cls_uart->ier);
1004
1005 /*
1006 * The Enhanced Register Set may only be accessed when
1007 * the Line Control Register is set to 0xBFh.
1008 */
1009 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
1010
1011 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
1012
1013 /* Turn on Enhanced/Extended controls */
1014 isr_fcr |= (UART_EXAR654_EFR_ECB);
1015
1016 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
1017
1018 /* Write old LCR value back out, which turns enhanced access off */
1019 writeb(lcrb, &ch->ch_cls_uart->lcr);
1020
1021 /* Clear out UART and FIFO */
1022 readb(&ch->ch_cls_uart->txrx);
1023
1024 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1025 &ch->ch_cls_uart->isr_fcr);
1026 usleep_range(10, 20);
1027
1028 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1029
1030 readb(&ch->ch_cls_uart->lsr);
1031 readb(&ch->ch_cls_uart->msr);
1032 }
1033
cls_uart_off(struct channel_t * ch)1034 static void cls_uart_off(struct channel_t *ch)
1035 {
1036 writeb(0, &ch->ch_cls_uart->ier);
1037 }
1038
1039 /*
1040 * The channel lock MUST be held by the calling function.
1041 * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
1042 */
cls_get_uart_bytes_left(struct channel_t * ch)1043 static uint cls_get_uart_bytes_left(struct channel_t *ch)
1044 {
1045 unsigned char left = 0;
1046 unsigned char lsr = 0;
1047
1048 if (!ch)
1049 return 0;
1050
1051 lsr = readb(&ch->ch_cls_uart->lsr);
1052
1053 /* Determine whether the Transmitter is empty or not */
1054 if (!(lsr & UART_LSR_TEMT)) {
1055 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1056 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1057 left = 1;
1058 } else {
1059 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1060 left = 0;
1061 }
1062
1063 return left;
1064 }
1065
1066 /*
1067 * Starts sending a break thru the UART.
1068 * The channel lock MUST be held by the calling function.
1069 */
cls_send_break(struct channel_t * ch,int msecs)1070 static void cls_send_break(struct channel_t *ch, int msecs)
1071 {
1072 if (!ch)
1073 return;
1074
1075 /* If we receive a time of 0, this means turn off the break. */
1076 if (msecs == 0) {
1077 if (ch->ch_flags & CH_BREAK_SENDING) {
1078 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1079
1080 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1081 ch->ch_flags &= ~(CH_BREAK_SENDING);
1082 ch->ch_stop_sending_break = 0;
1083 }
1084 return;
1085 }
1086
1087 /*
1088 * Set the time we should stop sending the break.
1089 * If we are already sending a break, toss away the existing
1090 * time to stop, and use this new value instead.
1091 */
1092 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1093
1094 /* Tell the UART to start sending the break */
1095 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1096 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1097
1098 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1099 ch->ch_flags |= (CH_BREAK_SENDING);
1100 }
1101 }
1102
1103 /*
1104 * Sends a specific character as soon as possible to the UART,
1105 * jumping over any bytes that might be in the write queue.
1106 *
1107 * The channel lock MUST be held by the calling function.
1108 */
cls_send_immediate_char(struct channel_t * ch,unsigned char c)1109 static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
1110 {
1111 if (!ch)
1112 return;
1113
1114 writeb(c, &ch->ch_cls_uart->txrx);
1115 }
1116
1117 struct board_ops dgnc_cls_ops = {
1118 .tasklet = cls_tasklet,
1119 .intr = cls_intr,
1120 .uart_init = cls_uart_init,
1121 .uart_off = cls_uart_off,
1122 .drain = cls_drain,
1123 .param = cls_param,
1124 .assert_modem_signals = cls_assert_modem_signals,
1125 .flush_uart_write = cls_flush_uart_write,
1126 .flush_uart_read = cls_flush_uart_read,
1127 .disable_receiver = cls_disable_receiver,
1128 .enable_receiver = cls_enable_receiver,
1129 .send_break = cls_send_break,
1130 .send_start_character = cls_send_start_character,
1131 .send_stop_character = cls_send_stop_character,
1132 .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
1133 .get_uart_bytes_left = cls_get_uart_bytes_left,
1134 .send_immediate_char = cls_send_immediate_char
1135 };
1136
